MXPA99003535A - Apparatus and method for generating on-screen-display messages using field doubling - Google Patents

Abstract

An apparatus and concomitant method for generating an OSD message by constructing an OSD bitstream defining a single field of OSD data. The OSD bitstream contains an OSD header and OSD data. An OSD unit retrieves pixel control information from the OSD header which is programmed by a processor of a decoding/displaying system. The OSD header contains information including various pointers, that are used to provide instructions as to the treatment of the OSD data. If a top field pointer and a bottom field pointer are set to an identical value in the OSD header, then the OSD unit will repeat each OSD line in the other field for an OSD region.

Description

DEVICE AND METHOD FOR GENERATING SCREEN DEPLOYMENT MESSAGES USING FIELD DOUBLE FIELD OF THE INVENTION The present invention relates to a method and apparatus for generating Display Display (OSD) messages using a "field doubling mode". More particularly, this invention relates to a method and apparatus that reduces the bandwidth requirements of the memory of a decoding / display system by repeating a higher field of screen display data in the lower field for a region. of screen display. BACKGROUND OF THE INVENTION Screen display messages play an important role in consumer electronic products by providing users with interactive information such as menus to guide them through the use and configuration of the product. Other important functions of screen display include the ability to provide subtitling and the display of channel logos. However, the improved standard of digital video technology presents a major problem for generating and displaying display messages on the screen. For example, there are specific requirements for High Definition Television (HDTV) that a high definition television must display up to 216 characters in four (4) "windows" compared to the current requirements of the National Television Systems Committee (NTSC). a maximum of 128 characters in a "window". These new requirements represent severe difficulties in the decoding / display system used to decode and display television signals (eg, high-definition television, National Committee of Television Systems, MPEG, and the like) which must decode the data streams encoded and present the decoded data to a deployment system with minimal delays. Since on-screen display messages must be displayed (overlaid) with the video data, the decoding / deployment system microprocessor must allocate a portion of the memory bandwidth to perform on-screen display functions, thereby increasing the requirement. of the bandwidth of the memory of a decoding / deployment system and the overloading of general physical equipment. Thus, it is necessary to have a method and apparatus to generate display messages on the screen without increasing the physical equipment requirements, for example, the bandwidth of the memory, of a decoding / deployment system. Brief Description of the Invention The invention relates to a concomitant apparatus and method for generating screen display messages by constructing a valid screen display bit stream with instructions in the on-screen display header to repeat a higher field of display data on screen in the bottom field for a region of screen display.

More specifically, in accordance with the invention, a screen display unit retrieves a screen display bit stream from a storage device. The screen display bit stream contains a screen display header and screen display data. The on-screen display header contains control information that is used to program a color palette of the on-screen display unit and to provide instructions on how to process display data on the screen. The control information is programmed by a processor of a decoding / deployment system. The control information includes two pixel data pointers to be displayed on the screen, a "Top Display Block Flagsignator" and a "Display Pointer". Bottom block of screen display ". These flags (flags) inform the display unit where the display pixel data are located on the upper and lower screen in the memory, respectively. When both pointers are set to the same value, the display unit repeats a display line of pixels in the other field. Namely, the upper and lower fields share the same display data on the screen. These and other aspects of the invention will be described with respect to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings: Figure 1 is a block diagram of a decoding / deployment system including an on-screen display unit in accordance with an aspect of the invention; Figure 2 illustrates the structure of a pixel data stream displayed on a sample screen that implements Field Dubbing; Figure 3 is a block diagram that discloses the structure of a memory that has several on-screen display headers and bitmap (blocks) of lower and upper field of screen display and their relationships to a displayed frame; and Figure 4 is a flow diagram illustrating the method for constructing a valid screen display data stream by implementing Field Dubbing. Detailed Description of the Drawings Figure 1 illustrates a block diagram of a decoding / unfolding system for television signals 100 (hereinafter the decoding system). The decoding system comprises a processor 130, a random access memory (RAM) 140, a read-only memory (ROM) 142, an on-screen display unit 150, a video decoder 160, and a mixer 170. The output of the mixer 170 is coupled to a display device 190 via the path 180. The present invention is described below in accordance with the MPEG standards, International Standards ISO / I EC 1 1 172 (1991) (generally referred to as MPEG-1 format) and 13818 (1995) (generally referred to as M-PEG format). 2) . However, those skilled in the art will understand that the present invention can be applied or adapted to other decoding systems by implementing other coding / decoding formats. In the preferred embodiment, the decoding system 100 performs real-time audio and video decompression of various data streams (bitstreams) 120. The bitstreams 120 may comprise elementary audio and video streams that are encoded in accordance with MPEG-1 and MPEG-2 standards. The coded bitstreams 120 are generated by an encoder (not shown) and are transmitted to the decoding system through a communication channel. The encoded bitstreams contain a coded representation of a plurality of images and may include the audio information associated with those images, for example, a stream of multimedia data. The multimedia source can be a high-definition television station, a video disc, a cable television station and the like. In turn, the decoding system 100 decodes the coded data streams to produce a plurality of decoded images for display on the screen 190 in synchronization with the associated audio information. However, for the purpose of this invention, the audio decoding function of the decoding system 100 is irrelevant and therefore not described. More specifically, the processor 130 receives bit streams 120 and bitstreams 1 10 as inputs. The bitstreams 1 10 may comprise several control signals or other data streams that are not included in the bit streams 120. For example, a channel decoder or transport unit (not shown) may be displayed between the channel of transmission and the decoding system 100 for performing the analysis and routing of data packets in data streams or control streams. In the preferred embodiment, the processor 130 performs various control functions, including but not limited to, providing control data to the video decoder 160 and the display unit 1 50, managing access to the memory and controlling the display of the images displayed. Although the present invention discloses a single processor, those skilled in the art will understand that the processor 130 may comprise several dedicated devices for managing specific functions, for example, a memory controller, a microprocessor interface unit, and sim ilar ones. The processor 1 30 receives bit streams 120 and writes the data packets in the memory 140 via a video decoder 160. Optionally, the bitstreams can pass through a (FI FO) com thinker from First into First. Exit (not shown) before transferring them via memory data bus to memory. Additionally, there is generally another memory (not shown) that is used only by the processor 130. The memory 140 is used to store a plurality of data including compressed data, decoded images and the display bitmap. As such, the memory is generally mapped into several compensators, for example a bit compensator for storing compressed data, a screen display compensator for storing the display bitmap on the screen, several frame compensators for storing frames of images and a display compensator to store decoded images. In accordance with MPEG standards, the video decoder 160 decodes the compressed data in the memory 140 to reconstruct the encoded images in the memory. In some cases, the decoded image is a difference signal that is added to a stored reference image to produce the actual image in accordance with the compression technique used to encode the image (e.g., to facilitate decoding of a compensated image of movement). Once an image is reconstructed, it is stored in the deployment compensator pending deployment via the mixer 170. Similarly, the display unit 150 uses the memory 140 to store the display bitmap on the screen or the Display deployment specification. The on-screen display unit allows a user (manufacturer) to define a bitmap for each field that can be superimposed on the decoded image The on-screen display bitmap can contain information that is stored on a storage device, by example, a read-only memory, on the configuration and options of a particular electronic consumer product.Alternatively, the on-screen display bitmap may contain information regarding subtitling and channel logos that is transmitted from a cable television, a disk video and the like A screen-map bitmap is defined as a set of regions (usually rectangular in shape) of programmable size and position, each of which has a unique palette of available colors. screen display is written to the screen display compensator of the memory 140 which is determined by the user for this purpose. However, those skilled in the art will understand that a read-only memory 142 or other equivalent storage devices can also serve this function. When the on-screen display function is activated for a particular picture or frame, the processor 130 manipulates the data in the memory 140 to construct a screen display bitstream. The on-screen display bitstream contains an on-screen display header and on-screen display data (data that defines the screen display pixels).

More specifically, the processor 130 programs (formats and stores) the on-screen display header in the memory 140. The on-screen display header contains information on the locations of the top and bottom of the field bit maps. On-screen display, palette data, pointing to the next header block and various display modes that include resolution, color and screen display compression. Once the on-screen display header is programmed, the processor 130 may manipulate the on-screen display data in the memory 140 according to a particular implementation. Alternatively, the processor can simply program the on-screen display header with pointers to the screen display data in the memory, where the stored screen display data is retrieved without modification to form the screen display bitstream. A detailed description of the various on-screen display flags is described below with reference to Figure 2. Then, the processor 130 reports the active state, ie display on active screen, to the screen display unit 150, the which responds by requesting the processor 130 to access the on-screen display bit stream stored in the memory 140. The on-screen display bitstream is formed and retrieved as the display unit reads the on-screen display headers, followed each one by its associated screen display data. After receiving the screen display bits stream, the screen display unit processes the screen display pixel data in accordance with the instructions or modes selected in the screen display header. Then, the display unit expects a pair of display counters (not shown) to achieve counting values that identify the correct position on the screen to insert the display information (messages). In the correct position, the display unit sends its output to the mixer 170. The output of the display unit 150 is a stream or sequence of digital words representing respective luminance and chrominance components in the display display. New memory accesses are requested as required to maintain the necessary data flow (screen display bitstream) through the display unit to produce a large screen display image. When the last byte of the screen display pixel data for the current screen display region is read from the memory, the next screen display header is read and the process is repeated and includes the last display region on the screen for the current box. Those skilled in the art will understand that the order of constructing and retrieving the screen display bitstream can be modified as described above. For example, the on-screen display header can be read from the memory when the processor is formatting the on-screen display data, or the on-screen display data can be processed and displayed as on-screen display messages by the display unit on screen without having to recover all the current of display bits on the screen. Since the screen display pixel data is superimposed on the decoded image, the mixer 170 serves to selectively mix or multiplex the decoded image with the display pixel data. Namely, the mixer 170 has the ability to display at each pixel location, a screen display pixel, a pixel of the decoded image or a (mixed) combination of both types of pixels. This ability allows the display of Subtitling (only pixel data to be displayed on the screen) or the display of transparent channel logos (a combination of both on-screen display pixels and decoded image pixels) in a decoded image. The video decoder 160 and a screen display unit 150 form streams or sequences of digital words that represent respective luminance and chrominance components. These sequences of digital words representative of video components are coupled via a mixer 170 to a digital-to-analog converter (DAC) 185. The digital words representing luminance and chrominance are converted to analog luminance and chrominance signals by the respective sections of the digital to analog converter. The screen display unit 150 can be used to display a bitmap defined anywhere on the drop-down screen, regardless of the size and location of the active video area. This bitmap can be defined independently for each field and specified as a collection of on-screen display regions. A region is commonly a rectangular area specified by its boundary and by a bitmap that defines its content. The bitmap is displayed in a plurality of screen display lines, where each on-screen display line represents a line of screen display pixels in a screen display region. Each region has associated a palette that defines a plurality of colors (for example, 4 or 16 colors) that can be used in that region. If required, one of these colors may be transparent, allowing the background to be seen through as described above. However, the handling of screen display functions for a frame increases the computational hardware load of the processor 130 and more important, imposes severe limitations on the bandwidth of the processor memory because the processor 130 must address the memory requests from the video decoder 160 and the display unit 150. As such, the present invention reduces the size of the screen display bitstream by implementing the Field Doubling Mode. By repeating each screen display line for the upper and lower fields, the amount of screen display data to be stored and read from the memory 140 is reduced by 50%. Figure 2 illustrates the structure of a display bit stream of sample 200 that implements "Field Doubling". The screen display bit stream comprises a plurality of screen display headers 210, each followed by screen display data 220. In one embodiment, the header consists of five 64-bit words, followed by any number of 64-bit screen display data words (bitmap). The screen display header 210 contains information regarding the display region coordinates on screen 214, the various inputs of the palette 216 for a particular display region, and various function codes (bits). Those skilled in the art will understand that the screen display header can be of any length. A longer header can provide more information and options, for example, a palette with more inputs, but with the disadvantage of incurring greater computation expense, that is, more read and write cycles are required to implement the deployment functions in screen. In fact, the content of the on-screen display header is illustrative of a particular embodiment and is not limited to the specific configuration illustrated in Figure 2. The palette 216 contains a plurality of entries wherein each entry contains a representation of levels of chrominance and luminance for a screen display pixel. The palette information 216 is used to program the display palette on the screen. The function codes (bits) 212 contain information relating to various modes, including but not limited to, display options and display current bitstream options. The selection of the function codes 212 is controlled by the processor 130. The on-screen display region coordinates 214 contain the positions of the left and right edges of a display region, i.e. the start and stop positions of the display. row and column start and stop positions. These coordinates define the location where a display region will appear in a displayed box. However, a conventional television screen employs an interlaced deployment technique, a form of sub-employment, where every third line of an image is initially displayed (scanned). Once the initial scan is complete, a second exploration of the remaining group of lines is done starting from the upper part of the image. Namely, the odd numbered lines (usually referred to as "upper field" or "upper block") of an image or frame is initially scanned, followed by a subsequent scan of the even numbered lines (generally referred to as "lower field" or "lower field"). lower block ") at a later time. For interleaved display, the region coordinates 214 include the positions (pointers) of the upper field 240 and lower field pixel bitmaps 242 in the memory 140 for the corresponding on-screen display region. Finally, the screen display region coordinates 214 include a "next header flag" 244 to signal the next header block in the memory 140. In the preferred embodiment, the processor 130 may selectively set the flag of the upper block 240 to same value as the lower block flag 242. This setting causes the screen display unit 150 to interpret the locations of the display data on the screen for the upper and lower fields to be located in the same memory location. This facility causes the display unit 150 to display the same on-screen display data for the upper and lower fields in a region of on-screen display. In essence, the screen display unit repeats a screen display line of pixels in the other field (Field Dubbing). As such, only the processor 130 is required to generate one-half of the display data. Namely, the size of the screen display bitstream is reduced by approximately 50%. The screen display data 220 contains bitmap data in order from left to right and top to bottom. Screen display data is generally used to define the color index to the on-screen display palette for each pixel in the bitmap image formation. If Field Dubbing is implemented for an interlaced deployment, screen display data 220 defines screen display data for only a single field 230. As the upper and lower block flags are set to the same value, the display unit On screen 150 you only need to read a single field of display data against two fields. The decision on which field (top or bottom) to repeat, is determined by the processor 130. Generally, the selection of one field over the other would not produce a noticeable difference. Figure 3 illustrates a block diagram describing the structure of a memory 340 having various headers 340 and bitmaps (blocks) of upper and lower field of screen display 310-330 and their relations to a displayed frame 350 having a plurality of screen display regions 352 and 354. To illustrate, for each "active screen display" box, the screen display unit 150 requests memory accesses that start at the memory location indicated by the register 305 The screen display unit 150 reads the first screen display header block 310 to determine where the display field bitmaps are located in upper screen 312 and lower 314 for a screen display region 1 352 When the screen display data of both fields are read by the display unit, the display unit sends a new address of header to processor 130 using the "following header flag" which is stored in the first screen display header 310. This process continues until the last display region is processed and displayed for the currently displayed frame. Figure 3 illustrates a region 2 of screen display 354, where the Field Doubling is implemented. The screen display unit 150 reads the second screen display header block 320 to determine where the display field bitmaps are located on top screen 326 and bottom 234 for a display region 2 on screen 354. As the lower and upper block flags are set to the same value, the screen display unit 150 only reads a single field (upper field 326) of screen display data. The single screen display data field is repeated for screen display region 2 354. The bottom field display bitmap 324 is not used or read from memory. In fact, for certain types of screen display data, the processor 130 may not build the lower field display bitmap 324. This mode of operation allows the processor 130 to gain a 2: 1 ratio in the mode of normal display where the screen display bitstream carries both fields of display data. The savings are more significant where the display regions are particularly large. If Field Dubbing is implemented, the display deployment resolution on the screen is vertically reduced by 50%, since each successive pair of horizontal display lines displays the same information. However, a reduction in screen display resolution in exchange for a higher display deployment message speed is acceptable and appropriate for several on-screen deployment implementations, ie, Subtitling, Subtitling requires rapid deployment of screen display messages that generally relate spoken words to a series of frames (images). As it is desirable to see Subtitling as the images are displayed, the reduction in resolution is an acceptable change. Additionally, because the screen display messages in the Subtitle are displayed only briefly, the reduced resolution is generally not noticeable. Thus, Field Doubling reduces the number of memory operations without limiting the deployment capabilities of a particular deployment deployment on the screen. Finally, although Field Dubbing can be implemented for a screen display header 210, the screen display unit 150 supports multiple header blocks that can each have a different resolution mode. Thus, the display unit is able to display different types of resolutions or formats on the same video screen. For example, different display regions can be displayed on the screen in different resolutions depending on the screen display data that is being displayed. The implementation of Field Dubbing is controlled by the user via the processor 130. This control can be implemented using computer programs that detect the need to minimize memory access by the display unit 150. For example, the decoder Video 160 may receive a series of complicated encoded frames that require additional memory access. To minimize memory access conflicts between the on-screen display unit and the video decoder, the processor can shift the increased demand of the video decoder by implementing Field Dubbing in the on-screen display bitstream. Finally, an alternative embodiment of the present invention incorporates a single bit in the on-screen display header to indicate whether the "Field Doubling Mode" is activated. When this dedicated bit is activated, the on-screen display unit will repeat the on-screen display data so that each screen display line is repeated in the other field. Figure 4, illustrates a method 400 for constructing a stream of screen display bits to implement Field Dubbing. The method is generally taken up from a storage device, for example, a memory, and executed by the processor 130. The screen display bitstream is generated by the processor 130 and is processed by the display unit 150. The method 400 constructs a stream of screen display bits by generating an on-screen display header having a plurality of control information including several pointers, followed by a plurality of data bytes. With reference to Figure 4, method 400 begins at step 405 and proceeds to step 410 where method 400 determines whether Field Doubling is enabled for a display region. If the request is answered negatively, method 400 proceeds to step 415 where the display data bytes are generated on the screen using non-field doubling format. Then, method 400 proceeds to step 440. In the request in step 410 it is answered affirmatively, method 400 proceeds to step 420 where the lower and upper field pointers are set to the same value in the on-screen display header. As the upper and lower field flags (block) are set to the same value, the screen display unit 150 will only have to read a single field of display data on the screen. In step 430, a single on-screen display data field is arranged in the on-screen display data bytes. Namely, the on-screen display bitstream only carries on-screen display data for each third screen display line, where each on-screen display line comprises enough on-screen display pixels for the on-screen display unit to display on screen. 150 display a single horizontal line in a display region. In step 440, method 400 determines if there is another display header on the screen. A new on-screen display header may be required if the various modes represented by the function bits 212 are modified. Similarly, a new heading is required for each new display region in a table. If the request is answered negatively, method 400 proceeds to step 450 where method 400 terminates. If the request is answered affirmatively, method 400 proceeds to step 410 where steps 410-430 are repeated for each display header in additional screen In this manner, the on-screen display bit stream may comprise display data bytes in field doubling screen and display data bytes in non-field doubling screen. A novel method and apparatus for constructing a screen display bit stream that implements field doubling using a single display pixel field has now been shown and described. However, many changes, modifications, variations and other uses and applications of the present invention will be apparent to those skilled in the art after consideration of this specification and the accompanying drawings, which disclose the embodiments thereof. All mentioned changes, modifications, variations and other uses and applications that do not deviate from the spirit and scope of the invention are considered covered by the invention, which will be limited only by the following claims.

Claims (13)

1. CLAIMS 1. Method for constructing an on-screen display bitstream having a screen display header and on-screen display data, said method comprising the steps of: establishing a first field flag and a second field flag to a identical value in the screen display header; and generating on-screen display data that defines a plurality of on-screen display data bytes that have a single display data field. The method of claim 1, wherein said first field flag is an upper field flag and said second field flag is a lower field flag. 3. The method of claim 1, further comprising the step of: generating screen display data defining a plurality of on-screen display data bytes that have on-screen display data not simple. 4. Method for constructing a stream of screen display bits having a screen display header and screen display data, said method comprising the steps of: setting a bit in the on-screen display header where such a bit is use to indicate a field dubbing mode; and generating on-screen display data that defines a plurality of on-screen display data bytes that have a single display data field. 5. A screen display bit stream stored in a storage medium comprising: a header having a first field flag and a second field flag, wherein said field flags are set to an identical value; and a plurality of display data bytes on the screen, coupled to said header, defining a single display data field. 6. The screen display bit stream of claim 5, wherein said first field flag is an upper field flag and said second field flag is a lower field flag. 7. The deployment bitstream in FIG. The screen of claim 5, wherein said plurality of screen display data bytes further defines display data in non-simple field display. 8. Apparatus for generating an on-screen display display stream having a screen display header and screen display data comprising: a storage medium for storing the on-screen display header and on-screen display data; and a processor, coupled to such storage means, to set a first field flag and a second field flag to an identical value and to read such a screen display header and said screen display data defining a single field of screen display data to form the screen display bitstream. 9. The apparatus of claim 8, wherein said storage means is a read-only memory (ROM). 10. The apparatus of claim 8, wherein said storage means is a random access memory (RAM). The apparatus of claim 8, wherein said first field flag is an upper field flag and said second field flag is a lower field flag. 12. Apparatus for generating an on-screen display message comprising: a storage means for storing a screen display bitstream having a header and display data on the screen; a processor, coupled to such storage means, to establish a first field pointer and a second field pointer to an identical value in said screen display header and to format such screen display data by defining a single data field of screen display; and an on-screen display unit, coupled to said processor, for processing such display screen bitstream to form the on-screen display message. The apparatus of claim 12, wherein said first field flag is an upper field flag and said second field flag is a lower field flag.