MXPA99002286A - Television system for displaying main and auxiliary images with color error correction provisions - Google Patents

Abstract

A television system utilizes a common signal processing unit (e.g., a common chrominance demodulator) for processing a combined video signal suitable for coupling to a display device for producing an image having a portion attributable to a main video signal and a portion attributable to an auxiliary video signal. If the common signal processing unit relies upon the color information (e.g., color burst) contained in the main video signal, and the main signal is either non-existent or lacking such color information, then a substitute color information signal will be generated so that the combined video signal may be processed to produce a color auxiliary image, and a monochrome (or non-existent) main image.

Description

TELEVISION SYSTEM FOR SHOWING MAIN AND AUXILIAR IMAGES WITH ERROR CORRECTION PROVISIONS OF COLOR The present invention relates generally to television systems and more particularly to television systems that are capable of producing a video signal to display a main image and an auxiliary image. The television signal processing systems are known and produce a video signal which, when displayed by a display device, will produce an image having a main image with an auxiliary image inserted in (image-in-picture or PIP). ) or near (image out of picture, or POP) the main image. The two video images shown are commonly associated with video signals derived from different video sources (for example, one from a first tuner tuned to a station and one from a second tuner tuned to another station or from a video source such as video tape recorder or laser disc player). In order to create the image-in-picture or out-of-picture image described above, generally the auxiliary image video signal is decoded (demodulated) into luminance information and color difference information and then re-encoded to be coupled with the video signal of the main image. This re-encoding is particularly critical in the chrominance channel, where the saturation (level) and color (phase) of the auxiliary image is modulated by (and therefore depends on) the main signal synchronization signal for maintain adequate saturation and color when the combined signal (main and auxiliary) is decoded by the main chrominance decoder. A prior art television system 100, including a modulated chrominance picture-in-picture system is shown in Figure 1. A luminance / main chrominance separator 104 is coupled to a main video source 102 and produces components separate main luminance YM and CM chrominance. Then, the main luminance components YM and CM chrominance are coupled to a layer switch 106. An auxiliary luminance / chrominance separator 110 is coupled to an auxiliary video source 108 and produces separate auxiliary components of luminance YA and chrominance CA. The auxiliary chroma component CA is demodulated using the auxiliary synchronization reference by the chrominance demodulator 112 to form color difference signals R-Y and B-Y. Then, the color difference signals RY and BY are processed (i.e., compressed) by an image-in-picture processor 114 and coupled to a chroma modulator 118. The chroma modulator 118 re-modulates the difference signals using the main color synchronization reference to form the AC chrominance component signal. The re-modulated chrominance component signal CA and the auxiliary luminance signal YA are coupled to the layer switch 106.

The layer switch 106 combines the two sets of video signals of components YM, CM and YA.CA into a series of video signals of combined components Y, C. The combined chrominance signal C is demodulated using the main synchronization reference by the chrominance demodulator 118 to form color difference signals RY and BY. The combined color difference signals RY and BY, and the combined luminance signal Y are coupled to an activator circuit and array processor 120, which in response produces the signals of the deployment trigger R, G and B. In the system above mentioned, the chrominance demodulator 118, uses timing information (synchronization) and color reference (color synchronization) of the main luminance and chrominance components to process the combined luminance and chrominance signals because the color reference and timing information are removed during the auxiliary signal processing. Chrominance demodulator 118, may include a color buffer circuit to suppress chrominance artifacts (e.g., confetti) in monochromatic images. As such, if the color buffer circuit determines that the (main) video signal does not contain a color synchronization, then the circuit will responsibly buffer all of the chrominance information. Unfortunately, if the video signal used to produce a main image does not exist or is monochromatic and does not contain color information (or the information is noisy or can not be used for any other reason) then the main and auxiliary images will be displayed as images in black and white, even if the auxiliary video signal included color information. For example, the main image video signal may not include a synchronization signal (e.g., black and white or monochromatic signal) or the synchronization signal may be very small or distorted (e.g., noisy conditions, broken antenna). or distortion of the tuner through the video band). These conditions may cause loss of color in the auxiliary image. The present invention recognizes that the problem of color loss in an image-in-picture when receiving a monochromatic main image is due to common signal processing circuits susceptible to deactivating a color image component of an auxiliary video signal when the main video signal is, or seems to be, monochromatic. A controller generates a substitute color image component in response to the detection of a monochromatic main signal. In this way the invention allows an image of an image out of image or image-in-color image to be displayed in color, even if the main signal is monochromatic, has attenuated or noisy chrominance information, or is not present. The invention will be described with reference to the accompanying drawings in which: Figure 1 is a block diagram of a modulated chrominance television apparatus of the prior art image-in-picture type.; Figure 2 is a block diagram of a television set showing the invention; Figure 3 is a detailed block diagram of a clock set in synchronization suitable for use in the apparatus of Figure 2; Figure 4 is a detailed block diagram of a synchronization sample accumulator suitable for use in the apparatus of Figure 2; and Figure 5 is a detailed block diagram of a magnitude and phase calculator suitable for use in the apparatus of Figure 2. Similar reference denominators in the different figures refer to the same or similar elements. Figure 2 illustrates a television apparatus 200 including the invention, which includes a first video source 202 for providing a first composite video signal CV1, a second video source 208 for providing a second composite video signal CV2, and a video-s source (ie, high bandwidth) 225 to provide a video-s signal having separate components of luminance SY and chrominance SC. A video signal processing unit 1000 processes the three video signals to form an output luminance signal YO and an output chrominance signal CO. The output chrominance signal CO is demodulated by the chrominance demodulation unit 218. The output of the chrominance demodulation unit 218 and the output luminance signal YO are processed by an activating unit and matrix processor 220 to produce signals RGB for activating a display unit 222. For television receiver applications, the first and second video sources 8 and 9 may each include, for example, a conventional tuner, detector and intermediate frequency amplifier. The sources may also include baseband video inputs. The monitor can be omitted for television monitor applications. The demodulation unit 218, the activating unit and matrix processor 220, the display unit 222 and the associated control circuits can be of a conventional design, the details of which are omitted. In the exemplary embodiment of Figure 2, the video signal processing unit 1000 is a digital signal processing unit which can be, for example, an integrated circuit. The video signal processing unit 1000 includes a main video signal processing channel for producing a main video signal YM, CM, an auxiliary video signal processing channel for producing an auxiliary video signal YA, CA, a switch 206 for selectively joining the main video signals YM, CM and auxiliary YA.CA to form the output signal YO.CO. The switch 206 is controlled by a controller (not shown) to form the output video signal YO, CO which, when displayed, will produce an image having a main image with an auxiliary image inserted inside (image-in-image) ) or near (image outside image) the main image. Of course, the switch can also pass just one video signal for deployment. The video signal processing unit 1000 includes a summing amplifier 227 which receives the separate luminance components SY and chrominance SC of a video-s signal and in response produces a third CVS composite video signal. The CVS composite video signal representative of the video-s and the first composite video signal CV1 and second composite video signal CV2 are coupled to a switch of the main selector 201 and a switch of the auxiliary selector 203. The selector switches are controlled by a controller (not shown). The video signal processing unit 1000 includes a clock set in synchronization 300 which is phase locked to the color synchronization reference signal of the CVM main video signal and produces a first clock signal 1Fc which has substantially the same frequency (approximately 3.58 MHz) than the main color synchronization and a second 4Fc clock signal having a frequency of approximately four times (14.32 MHz) the frequency of color synchronization. These two clock signals are used to synchronize the different elements in the video signal processing unit 1000. The clock set in synchronization has been included in the circuits of the black-and-white detector 250 and will be described in detail later. The video signal processing unit 1000 includes a time generator 280 that generates various time signals used through the video signal processing unit. The time generator 280 is synchronized with the clock signal 4Fc from the clock set in synchronization 300 and with the deflection time signal DEF of the display driver 300 to generate a number of time signals including horizontal synchronization (HS) signals, vertical synchronization (VS), synchronization gate (BG) and closed synchronization gate (BG CLOSED). The main video signal processing channel of the video processing unit 1000 comprises the main selector switch 201, which couples one of the first CV1, second CV2 and third CVS composite video signals to an analog-to-digital converter ( A / D) 207. The analog-to-digital converter 207 samples the main composite video signal at a sampling rate of approximately four times the frequency of the color subcarrier to produce a video data stream, CVM main video signal . The sampling clock signal 4Fc is set in phase to the color synchronization reference of the selected main signal by a clock set in synchronization 300, which is shown "in Figure 3 and to be described later. main CVM is coupled to a luminance / chrominance separator, illustratively the comb filter 204 and a black-and-white detector 250. The black-and-white detector 250 determines whether the CVM main video signal is a color video signal at determine if, for example, the CVM main video signal includes a color reference (color synchronization) The black and white detector 250 produces a MAIN output = BLACK and WHITE signal indicative of presence (0) or absence ( 1) of the valid color information in the CVM main video signal, the comb filter 204 separates the CVM main video signal into a YM main luminance component and a c-component. main rominancia CM. The main luminance component YM is converted into an analogue luminance component YM by a digital-to-analog converter (D / A) 209. In response to a controller (not shown) a switch 290a selectively couples either the main luminance component (analog) YM or the video-s luminance component SY to the layer switch 206 as a YM main luminance signal. The main chrominance component CM is coupled to a switch 270, which responds to the MAIN output signal = BLACK and WHITE of the black-and-white detector 250. When the MAIN output signal = BLACK AND WHITE of the detector 250 indicates that the signal main video CVM is a color signal, the switch 270 couples the main chrominance component CM of the CVM main video signal to a digital-to-analog converter 275. When the MAIN output signal = BLACK AND WHITE of the target detector and black 250 indicates that the CVM main video signal is not a color signal, the switch 270 couples a CMS substitute chrominance signal to the digital-to-analog converter 275. The digital-to-analog converter 275 converts the selected chrominance signal ( CM or CMS) in a CM analog chrominance signal. A switch 290b selectively couples either the main chrominance component (analog) CM or the chrominance component of video-s SC to the layer switch 206 as a main chrominance signal CM. The switch 290 is controlled by a controller (not shown). The CMS substitute chrominance signal comprises, for example, a zero amplitude color signal with a color synchronization reference of 3.58 MHz which is produced by a substitute chrominance unit 265. The substitute chrominance unit 265 comprises a switch 260 which responds to the sync gate signal BG from the time unit 280. The sync gate signal BG is synchronized to the selected CVM main video signal and is high only during the portion corresponding to the back porch of each extinction pulse horizontal. The CMS substitute chrominance signal is formed by coupling a substitute timing reference signal (the 1FC clock) to the switch 270 during the synchronization portion of the main video signal and by coupling a substitute color signal (a chrominance value of zero amplitude) to switch 270 during the observable portion of the main video signal. When the black-and-white detector 250 indicates that the CVM main video signal is not a color signal, then the 3.58 MHz color synchronization of the substitute chrominance signal CMS is used by the chrominance demodulator 218 to demodulate the output chrominance signal CO. It is important to note that a color buffer circuit (not shown) in a chrominance demodulator 218 will suppress the color information of the received signal (ie CO) if a color synchronization is absent. Conversely, the color buffer circuit will not suppress color information if color synchronization is present. Therefore, the CMS substitute chrominance signal must also include valid amplitude information (color saturation). To prevent the deployment of undesirable color artifacts in the main black and white image, the CMS substitute chrominance signal has an amplitude of zero during the non-synchronization portion (i.e., shown). The auxiliary video processing channel of the video processing unit 1000 comprises the auxiliary selector switch 203, which couples one of the first CV1, second CV2 and third CVS composite video signals to the analog-to-digital converter 205. analog to digital converter 205 samples the selected auxiliary composite video signal at a sampling rate of approximately four times the frequency of the color subcarrier to produce a video data stream, auxiliary video signal CVA. The auxiliary video signal CVA is coupled to a luminance / chrominance separator 210 (eg, a low pass filter and a band pass filter) which separates the selected auxiliary video signal CVA into an auxiliary luminance component YM and a auxiliary chrominance component CM. The auxiliary chroma component CA is coupled to a chrominance decoding unit (ie, demodulator) 212, where it is decoded to form color difference vectors (B-Y) A and (R-Y) A. Chrominance decoder 212 may be implemented as standard using the color synchronization reference of the auxiliary chroma component CA. However, the exemplary embodiment of the video processing unit 1000 only includes a clock source which is set to the color synchronization reference of the CVM main video signal. As such, the chrominance decoder 212 operates asynchronously with respect to the color synchronization reference of the auxiliary chroma signal CA. An exemplary host to provide this function is described in the United States Patent No. 4, 558, 348. The auxiliary luminance component YA and the color difference signals (BY) A and (RY) A are coupled to the storage unit and image-in-picture compression 214, which comprises the signals YA, (BY) A, (RY) A using for example, a sub-sampling technique, and stores the compressed signals YA, (BY) A, (RY) A in a memory. To produce an image-in-picture image, the auxiliary video signal YA, (BY) A, (RY) A is subjected to horizontal compression (i.e., reduction of the nu of picture elements per line) and horizontal compression ( that is, reduction of the nu of lines per field). To produce a side-by-side image (out-of-picture image), the auxiliary video signal YA, (BY) A, (RY) A can be compressed on only one axis, for example, horizontal, where the auxiliary image image out of image will retain the full resolution on the other axis, that is, vertical (there will be no missing lines). The compressed color difference signals (BY) A, (RY) A are coupled to the chrominance encoder unit (i.e., modulator) 216, which encodes the signals using the color synchronization reference to form a compressed signal of auxiliary chrominance CA. The compressed auxiliary chrominance signal CA is coupled to the digital-to-analog multiplier converter 221, which produces a compressed analog signal of auxiliary chroma CA. The saturation level of the auxiliary chrominance signal CA is adjusted by varying the gain term PIP C DAC GAIN of the digital-to-analog multiplier converter 221. The pair of luminance signals / auxiliary chrominance YA.CA is coupled to the switch 206 together with (as described above) the luminance signal pair / main chrominance YM.CM. The switch 206 is controlled by a controller (not shown) to selectively combine the luminance signal pairs / main chrominance YM.CM and auxiliary YA, AC in a pair of luminance signal / output chrominance YO, CO which, when it is processed and displayed, it will produce the desired image-in-image or image-out-of-image effect. The switch 206 can produce an image-in-picture effect on the screen 222 by coupling the luminance signal / main chrominance signal YM, CM to the demodulation units 218 and matrix 220 during the portion of time in which the main image the auxiliary luminance / chrominance signal pair YA.CA will be displayed and coupled to the demodulation units 218 and matrix 220 during the portion of time in which the small image (image-in-image) is to be displayed. The demodulation unit 218 demodulates the output chrominance signal CO of the video signal processing unit 1000 to produce the color difference signals (B-Y) O and (R-Y) O. The luminance output signal YO and the color difference output signals (BY) O and (RY) O are coupled to an activator and matrix unit 220 to produce the RGB signals for the display unit 222. It is important to note that the chrominance demodulator 218 uses the color synchronization reference of the luminance signal pair / main chrominance YM.CM to demodulate the luminance signal pair / output chrominance YO.CO of the video signal processing unit 1000 If the luminance / main chrominance signal does not include color synchronization (eg, monochromatic video signal) then the chrominance demodulator 218 will not be able to demodulate the color information contained in the luminance / auxiliary chrominance signal pair YA, AC. Therefore, without the substitute CMS chrominance signal as described above, the television apparatus 200 of Figure 2 will not be able to produce an image-in-image color image (or out-of-image image) with a monochromatic main image. . The invention addresses the aforementioned problem by detecting whether the main image is monochromatic, generating a CMS replacement chrominance signal with a synchronization reference and replacing the main chrominance signal with the replacement signal. With reference to Figure 2, the black-and-white detector 250 will now be explained in detail. The black-and-white detector 250 receives the chrominance component CM of the main video signal CVM of the comb filter 204, determines whether the signal Main video CVM is a color video signal and produces a MAIN output = BLACK and WHITE signal indicating whether the main CVM video signal is black and white or not. the black-and-white detector 250 includes a synchronization accumulator (or quadrature phase detector) 400, which orders and totalizes the corrected odd and even polarity samples of the CM main chrominance signal occurring during the synchronization interval in a first group of X samples (occurring at synchronization peaks) and a quadrature group of Y samples (occurring at zero synchronization junctions). The numbers X and Y represent the coordinates of the synchronization vector in a Cartesian (rectangular) coordinate system. An exemplary accumulator is shown in Figure 4 and is described below. The X and Y coordinates of the synchronization vector are then applied to the magnitude and phase calculator 500 (a rectangular to polar coordinate converter) which converts the XY coordinates from rectangular to polar coordinate form (R, f) having a term of magnitude R and a term of phase angle (f). One approach to providing this conversion would be to apply the X and Y values to the address entries of a read-only memory (ROM) programmed with the corresponding values of radius and angle. However, such a configuration would require a relatively large memory. An approach used in exemplary mode eliminates the need for large memory when calculating angles using trigonometric sine, cosine or tangent approximations. Figure 5 exemplifies a coordinate system converter of this type (rectangular to polar) and is described in detail below. The term of magnitude R is coupled to a filter 215, which provides a term of filtered magnitude Ravg at an output. The filter 215 improves system performance by reducing errors caused by parasitic or erroneous magnitude terms by recurrently filtering the term of magnitude R, thus providing an average Ravg balance of the most recent magnitude terms. An appropriate implementation of filter 215 would be, for example, a recurring filter that provides a balance average of the eight most recent terms of magnitude. Then, the filtered magnitude term Ravg is coupled to an input B of a digital comparator 213. A minimum level signal provided by a minimum level signal source NOT SYNCHRONIZED 211 is coupled to an input A of digital comparator 213. The comparator 213 produces a MASTER = BLACK and WHITE bi-level output signal that will be set at a low level (ie 0) if the signal at input B (Ravg) is greater than the signal at input A (minimum) . The minimum level, which can be adjustable, represents a minimum magnitude level of a valid color synchronization. If the magnitude of Ravg is less than the magnitude of the minimum level, then the output of the comparator 213 will produce a high output signal MAIN = BLACK and WHITE indicating that the CVM main video signal is not a color signal. A low output signal indicates that the CVM main video signal is not a color signal. A low output signal indicates that the CVM main video signal is a color signal. A correct auxiliary image saturation level (ie, pale to live) can be produced by adjusting the auxiliary saturation level according to the main synchronization amplitude. In exemplary mode this is achieved by feeding the main synchronization level (Ravg) to the digital-to-analog multiplier converter 221 as the gain term PIP C DAC GAIN. When the main video signal CVM is a color video signal, a switch 217 couples the filtered magnitude term Ravg to the digital-to-analog converter 221 as the gain reference signal PIP C DAC GAIN. When the CVM main video signal is not a color video signal, the switch 217 couples a substitute (fixed or adjustable) magnitude term AUX SAT LEVEL (a level corresponding to, for example, a 40 IRE synchronization) to the converter from digital to analog 221 as the gain reference signal PIP C DAC GAIN. The substitute magnitude term is selected to produce a saturation level in the auxiliary color image that is similar to the nominal saturation level in the main image if the main image was a color image. Figure 3 shows an exemplary clock mode set in synchronization 300. The purpose of the clock set in synchronization is to produce two output clock signals that are fixed to the color synchronization reference of the CVM main video signal in a first operation mode (fixed). The first 1Fc signal has a frequency equal to the main color synchronization frequency (subcarrier), approximately 3.58 MHz. The second 4Fc signal has a frequency equal to four times the main color synchronization frequency (subcarrier), approximately 14.32 MHz. These two clock signals are used in the video signal processing unit 1000 for, for example, timing and sampling purposes. If there is no main color synchronization reference (ie, the main video is black and white) then the clock set in synchronization operates in a second mode (not set or "free running"). In the second mode, the clock 1Fc is set at a nominal frequency of 3.58 MHz. The clock signal 4Fc is still a precise multiple of four times the clock signal 1 Fc. The clock set in synchronization 300 receives the term phase angle f produced by the magnitude and phase calculator 500. This term f applies to an adder 303, a frequency error detector 301 and a fixation detector 302. The output of the fixing detector 302 is applied to a switch 304 which couples the frequency error output of the detector 301 to another input of the adder 303 when the fixing detector indicates that the system is not fixed. The frequency error detector measures the rate of change of the phase signal f from line to line and is essentially a differentiator and can be implemented by storing the phase of a previous line in a block and subtracting the current and values from previous phase to obtain the derivative with respect to time. Since the phase derivative with respect to time is equal to the frequency, the output of the frequency error detector is proportional to the frequency error when the system is not fixed. In this out-of-attachment condition, the fixing detector 302 allows the switch 304 to add the frequency error signal to the phase angle signal f in the adder 303. It has been found that this "increase" of the signal angle of phase when the circuit is out of fixation desirably improves the speed of phase fixation. However, once fixed the fixing detector 302 opens the switch 304 removing the frequency error signal of the adder 303 and later the phase control is only by means of the phase angle signal f. The output of adder 303, as mentioned above, comprises the synchronization phase angle signal f when the system is set (switch 304 open) and comprises the sum of the synchronization phase angle signal f and the error signal of Frequency when the system is out of fixation. The output signal of the adder is applied to a limiter circuit 305 which provides limitation as will be described later. The limited signal is applied to a binary speed multiplier 308. The purpose of the binary speed multiplier 308 is to generate pulses of current to charge and discharge a capacitor in a circuit filter (not shown) in a voltage-controlled crystal oscillator ( VCXO) 309 and thus control the oscillation frequency of the voltage-controlled crystal oscillator 309. The number or speed of production of current pulses is proportional to the phase angle signal f. In response to the magnitude of the phase angle signal f, the binary speed multi-plicator 308 generates positive current pulses to charge the circuit capacitor and increase the VCO frequency or negative current pulses to discharge the circuit capacitor and reduce the VCO frequency. In the setting, the magnitude of the phase angle signal f approaches zero and only enough pulses are produced to maintain the fixing condition. The reason for limiting the phase angle signal f in the limiter 305 is to avoid large phase or frequency errors having a great influence on the operation of the circuit. When the system is set and the synchronization phase angle is greater than a predetermined limiting or minimum value, it is desirable to limit the magnitude of the synchronization phase angle signal so as to limit the maximum charge or discharge currents applied to the capacitor. of circuit in the voltage-controlled crystal oscillator 309. An exemplary "limiting" value when the system is fixed is a phase angle of approximately 3.5 degrees. When it is out of fixation, the limiting level is increased (by a factor of ten or more) to improve the rate of re-acquisition fixation. As mentioned above, if the main CVM video signal is a black and white (monochromatic) signal (ie, it has no synchronization signal to fix to) then the clock set in synchronization will operate in the second or unfixed mode . The switch 307 receives a FREE OPERATION signal corresponding to the MAIN and BLACK output signal of the comparator 213. In response to this signal, the switch 307 will illustratively couple the contents of a programmable register 306 to the speed multiplier. binary 308. The binary speed multiplier 308 will in turn cause the voltage-controlled crystal oscillator to operate at a fixed frequency. The data stored in register 306 is calculated (or determined empirically) to be data that will produce nominally correct output clock frequencies 1Fc and 4Fc. Figure 4 is a detailed logic diagram of a suitable implementation of the synchronization accumulator (or quadrature phase detector) 400 of Figure 2. Briefly reviewing, the function of the accumulator is to sample the synchronization at four times the subcarrier frequency of color (4Fc) thus producing a sample for each 90 degrees of the synchronization signal. When the circuit is fixed, even samples occur at the synchronization peaks, thus forming the samples "in phase" or "X" and the nons samples occur at the junctions of synchronization axes to form the "quadrature phase" samples or "Y". Taken together, these two values, X and Y, represent the synchronization vector in a rectangular coordinate system. The function of the accumulator 400 is to perform the arithmetic operations necessary to order and adequately totalize the samples including the removal of the direct current component or "pedestal" value (for example, around the black level) of the synchronization samples produced by the analog to digital converter 207. In more detail, the CVM video signal samples produced by the analog-to-digital converter 207 have the form of a binary without a sign. Since synchronization appears during the tracking portion of horizontal synchronization, it will have a pedestal or direct current value around the black level. The exact value may be unknown or may vary with the source of the signal. To remove this component from the synchronization measurements, the CVM video signal from the analog-to-digital converter 207 is first converted from unsigned binary to a complement form of two by inverting the most significant bit (MSB) by an inverter 401. This change in the arithmetic form facilitates the addition and subtraction of samples in the accumulator. The two add-on samples from the inverter 401 are then applied to an adder / subtracter 402 comprising an exclusive "O" gate 404 and a full adder 406. The selection of addition or subtraction modes is controlled by the 1Fc clock signal which is on the color subcarrier frequency (one fourth of the 4Fc clock speed of the voltage controlled glass oscillator 309). The output of the adder / subtractor is stored in two fasteners connected in series 410 and 414 and fed back to the adder summing input. By timing fixings at the sample rate 4Fc and changing from addition to subtraction every two sample periods using the 1Fc clock, the samples in phase "X" will be accumulated in fixer 410 and the quadrature phase samples "Y" will be accumulated in the fixator 414. As the adder / subtractor alternates between addition and subtraction every two sample periods of the 4Fc clock, the "X" samples are alternately added and subtracted to produce the accumulated value "X" in the fixer 410. The sum and subtract alternate samples of the values of X (for example, + X0, -X2, + X4, -X6. + X8, -X10. Etc.) results in the cancellation of the direct current component of X. The synchronization component of X does not cancel because the polarity or synchronization "sign" alternates every two samples and in this way the synchronization samples are added. Accordingly, synchronization samples accumulate and the direct current component or pedestal portion of the samples is simply canceled. The same result occurs for the samples Y. To confine the samples X and Y to synchronization only, the output of the adder 406 (a sum of 13 bits) is applied to the fixer of the accumulator 410 via a synchronization gate 408 which is activated for 48 of the 4Fc clock periods during the synchronization interval of each line. A typical tuning (NTSC) will have 8 complete cycles corresponding to 32 samples of the 4-Fc clock. The synchronization gateway was made intentional and substantially wider than the synchronization width to ensure capture of all synchronization cycles in the case of substantial time errors in the video source. At the end of the synchronization gate period (48 samples of the 4Fc clock) a closed synchronization gate signal (provided by the timing unit 280) is applied to the fasteners 416 and 418 which store the accumulated synchronization vector data X and And for the rest of the line during which time the data converted to polar form by the magnitude and phase calculator 500 times, the magnitude term is filtered by the filter 215 and compared to a minimum level by the comparator 213 to produce the signal of MAIN output = BLACK and WHITE indicating that the main video signal is monochromatic or colored, as explained above. Figure 5 is a detailed logic diagram illustrating the magnitude and phase calculator 500 which converts the rectangular synchronization coordinates X and Y to polar coordinate form (magnitude and angle). In order to provide polar conversion, the X and Y coordinates of the synchronization accumulator 400 are applied to respective inputs of a comparison and division circuit 510 via the respective complement circuits of one each comprising an inverter or complementor (501 or 503) and a switch multiplexing (502 or 504) controlled by the sign bit of the input signal. This converts the coordinates of the complement of two to binary without sign to facilitate the subsequent comparisons and division of magnitude. For example, when the sign of X is "0" (bit 13, indicating a positive number) the remaining 12 bits of the magnitude of X are passed directly to the input X of circuit 510 via multiplexer 502. However, if the X sign is negative (binary "1", indicating a negative number) then the multiplex switch 502 couples the 12 magnitude bits complemented to the X input of the circuit 510 thus converting X to unsigned binary form. The magnitude bits (for example, 1-12) of the input signal Y are converted in the same way to unsigned form under the control of the sign bit Y (bit 13) for application to the Y input of the comparison circuit and division 510. Internally, the comparison and division circuit 510 includes a magnitude comparator to identify the largest of X and Y and produces this value as an "L" (ie, "larger") signal. The "L" signal is used to represent the "MAGNITUDE" of the polar synchronization vector for its application to the synchronization level comparator 213. Now considering the details of the polar conversion function of the magnitude and phase 500 calculator, this conversion is based on an approximation that for small angles (eg below 45 degrees) the tangent arc of the angle defined by the rectangular coordinates X and Y is approximately equal to the smallest of X and Y divided by the largest of X and Y. The comparison and division circuit 510 includes a magnitude detector, as explained above, which determines the relative sizes of X and Y. This detector is used internally to make a division of the smallest signal among the largest (represented as "S / L") and this number is used to represent the 7 least significant bits of the polar angle that cover a range of 45 degrees (an observer). To cover a complete circle (360 degrees) the calculator 500 adds or subtracts angles of 0, 90 or 180 degrees, depending on the operator according to the following Table 1 (below). The identification of specific octants of the synchronization vector is provided by a three-bit octant identification signal. The most significant bit B2 comprises the sign bit of the input signal "Y". The second most significant bit B1 comprises the sign bit of the input signal "X". The least significant bit BO comprises the exclusive "O" (via XOR 512) of the sign bit of the input signal "X" with the output of the magnitude comparator X <; And in circuit 510. Table 1 (below) identifies octants 0-7 in terms of this three-bit code. TABLE 1 oct bin angle oct angle bin 0 000 S / L 4 100 - (S / L) 1 001 90-S / L 5 101 - (90-S / L) 2 010 90 + S / L 6 110 - (90 + S / L) 3 011 180-S / L 7 111 - (180-S / L) In more detail, the arithmetic calculations of the synchronization vector angle are performed in the calculator 500 by a complete adder 520 that by means of an exclusive "O" gate 514 and inverter 522 is able to add or subtract. Two multiplexer switches 516 and 518 are provided which provide the numerical equivalent of fixed angles of 0, 90 and 180 degrees to an input of adder 420. By selecting the appropriate fixed angle and combining it arithmetically (for example, add or subtract) with the approximation of the tangent arc of the synchronization angle (the signal S / L) any synchronization angle in the 0-3 octants can be represented. The remaining octants 4-7 are calculated by inverting the corresponding octant of the 0-3 octants. This is done by the exclusive gate "O" 528 connected to the output of adder 420.

As an example of the calculation of the synchronization angle, it is assumed that the vectors X and Y are positive and that X is greater than Y. This defines a synchronization vector in the octant "0" that is between zero and forty-five degrees and whose angular value is approximately equal to Y / X (the smallest divided by the largest). Since X is positive, the multiplex switch 516 will select the "zero" constant as an output corresponding to zero angular degrees. Since X is assumed to be larger than Y, the comparator signal X < And it will also be zero, thus making the multiplex switch 518 select the output of the switch 516, which is zero degrees, as indicated above. The adder 522 for this condition adds a constant of zero (from switches 516 and 518) to the tangent arc approach (S / L) of the comparison and division circuit 510 and as the sign of Y is zero (Y is positive) the exclusive "O" gate of output 528 will pass this value (+ S / L) as the synchronization phase angle f. For different octants, the adder 520 adds different constants to S / L as shown in the circle with dashed line inserted in the output of the adder and also shown in Table 1 above. For example, for a synchronization vector that is in octant 1, the angle of the complete vector is the value of S / L subtracted from the 90 degree reference provided by switch 516. In octant 2 the value of 90 degrees is sum to the S / L value and in octant 3, the synchronization vector is determined by subtracting the S / L value of 180 degrees. For the remaining octants 4-7, the value of the synchronization vector is exactly as for the corresponding octants 0-3, except that the output of the adder 520 is inverted by the exclusive "O" gate 528, reversing the angle sign of synchronization phase indicated. Referring now to Figure 2, the term of magnitude R produced by the magnitude and phase calculator 500 is coupled to the minimum comparator 213 via the filter 215 (eg, a recurring filter). The filtered magnitude term Ravg is compared to a minimum level signal provided by a minimum level signal source NO SYNCHRONIZATION 211. For purposes of general system adjustment, the minimum level source 211 is programmable to provide a number of values of reference. Illustratively, the synchronization reference values of 16, 32, 64 and 128 are available. In terms of IRE signal levels, these correspond to synchronization amplitudes of 1, 2, 4 and 8 IRE levels. The comparator 213 compares the Ravg signal (which is equivalent to the "largest" of the X and Y vector components measured by the magnitude and phase calculator 500) with the synchronization reference level provided by the minimum level source 211 and produces as output the MAIN = BLACK and WHITE signal when the magnitude signal "L" is less than the minimum synchronization level signal. The time constant of this synchronization detector can be relatively long (for example, at a field speed rather than a line speed). As mentioned above, the switch 290a selectively couples either the main (analog) luminance component YM or the video-s luminance component SY to the layer switch 206 as a main luminance signal YM. Likewise, the switch 290b selectively couples either the main chrominance component (analog) CM or the chrominance component of video-s SC to the layer switch 206 as a main chrominance signal CM. Both switches respond to a controller (not shown). The inventors recognize that if the main image of the image to be displayed is derived from the video information contained in the video-s signals, then it is desirable to couple the video-s signals directly to the layer switch (instead of to use a separate comb version of the combined video-s signals). However, since the resolution of the auxiliary video signal is dramatically reduced by, for example, sub-sampling in the image-in-picture storage and compression unit 214, the average observer will not distinguish any substantial difference between an auxiliary video image -s and a composite video version of the combined video-s auxiliary image. Therefore, the video processing unit 1000 does not include a similar interrupting capacity for the auxiliary channel. The operation of the switch 290a depends only on whether the video-s input is selected for processing by the main processing channel or not. If the video-s signal is selected for processing by the main processing channel, even if the video-s signal is a black and white signal, then the switch 290a will couple the video-s luminance signal to the layer switch 206. The operation of the switch 290b depends on whether the video-s input is selected for processing by the main processing channel or not and whether the video-s signal is a color signal. If the video-s input is not selected for processing by the main processing channel, then the main channel will process the selected video input (i.e., CV1 or CV2) in the manner described above. If the video-s signal is selected for processing by the auxiliary processing channel, then the composite CVS signal will be processed by the auxiliary processing channel in the previously described manner. If the video-s signal is selected for processing by the main processing channel and the video-s signal is a color signal, then the switches 290a and 290b will couple the SY-video luminance signal and the signal of chrominance SC, respectively, to the layer switch 206. However, if the selected video-s signal is a black and white signal, then the switch 290b will couple the chrominance signal CM to the layer switch 206. This is due to that the black-and-white video-s signal does not contain the necessary color information that would allow the chrominance demodulator 218 to demodulate an auxiliary color signal. Therefore, the conventional video signal CVS produced by the summing amplifier 227 (which in this case is black and white) will be processed by the main channel, which will detect that the signal is black and white and in response, couples a replacement chrominance signal to switch 290b. The exemplary embodiment uses a black-and-white detector 250 that includes a clock set in synchronization (BLC) 300. However, it should be noted that the clock set in synchronization 300 need not be part of the black-and-white detector 250. The clock set in synchronization 300 is included in the black-and-white detector 250 because the inventors recognized that it was possible to construct a black-and-white detector using circuits common to a clock set in synchronization, namely, a synchronization accumulator, a magnitude and phase calculator and a synchronization level detector. By combining these common elements, the inventors were able to achieve certain synergistic effects, for example, reducing the cost and complexity of the circuits while increasing the reliability of the circuits. The combination described above of the clock set in synchronization and the black-and-white detector is not readily apparent because the clock set in synchronization must be modified to accommodate said configuration. For example, the clock set in synchronization depends on the output of the phase component of the magnitude and phase calculator to operate properly. In the absence of this phase component (ie, when the main signal is a black and white signal) the clock set in synchronization will not operate properly. The solution in this embodiment was the free-running mode described above with respect to the clock set in synchronization of Figure 3. It will be apparent to those skilled in the art, that although the invention has been described in terms of the specific examples, it can be realizing modifications and changes to the described modalities without departing from the essence of the invention. Therefore, it should be understood that the appended claims are intended to cover all modifications that naturally flow from the foregoing description and examples. It should be noted that although the invention has been described in terms of a system in which the auxiliary signal processing operations (e.g., for size reduction in an image-in-picture system) use components of luminance and chrominance, the invention is also applicable in systems in which the auxiliary signal processing operations utilize a composite video signal that contains both lumen and chromanance components in a single signal.

Claims (4)

1. REIVI NDICACIO N ES 1. Apparatus comprising: means for combining a first video signal (VC 1; CV2; CVS; SY, SC) and a second video signal (VC 1; CV2; CVS) to provide an output video signal (YO.CO) ) coupled to a display device (22) to produce an image comprising a first portion representative of said first video signal and a second portion representative of said second video signal; a detector (250) for detecting when said first video signal includes less than a predetermined level of chrominance information; means (265) for generating a substitute chrominance signal (CMS); and means (270) coupled to said detector (250) to include such a substitute chrominance signal (CMS) in said first video signal in response to said first video signal including less than such predetermined level of chrominance information.
2. 2. The apparatus of claim 1, wherein said detector (250) comprises: meters (400, 500) for determining a phase (f) and a magnitude (R) of a subcarrier reference component of said first signal of video; and measures (213) coupled to said determining means (400, 500) to compare such magnitude (R) of said subcarrier reference component to a predetermined minimum level and produce a signal (PRI NCI PAL - WHITE YN EGRO) indicative of said comparison. The apparatus of claim 1 or claim 2, wherein said detector comprises: med ios (300) to produce a first clock signal (1 Fc) substantially fixed to a subcarrier reference component of said first video signal , and to produce a second clock signal (4Fc) having a frequency substantially equal to a multiple of the frequency of said first clock signal. The apparatus of any preceding claim, wherein said substitute chrominance signal (CMS) comprises a subcarrier reference component and an observable component, such observable component has a substantially zero amplitude level. RESU MEN A television system uses a common signal processing unit (e.g., a common chrominance demodulator) to process a combined video signal suitable for coupling to a display device to produce an image having a portion attributable to a main video signal and a portion attributable to an auxiliary video signal. If the common signal processing unit is based on the color information (eg, color synchronization) contained in the main video signal, and the main signal is either non-existent or lacks said color information, then a signal The substitute color information will be generated so that a combined video signal can be processed to produce an auxiliary color image, and a monochromatic (or non-existent) main image.