MXPA99000967A - Digital to analogue converter and method to connect from digital to analog - Google Patents

Abstract

In a digital-to-analog converter comprising a pulse width modulation signal generator for generating a pulse width modulation signal by pulse width modulation of a real fixed value with a count value, and a low step to remove a high frequency component of the pulse width modulation signal to produce an analog signal, a difference between a current objective digital value and a previous objective digital value is multiplied by a coefficient determined from a constant of time of the low pass filter and a cycle of the target fixed value, and the multiplied value is added to the previous fixed fixed value to calculate the fixed value re

Description

DIGITAL TO ANALOGUE CONVERTER AND METHOD TO CONVERT FROM DIGITAL TO .ANALOGICAL BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a digital-to-analog converter for converting a digital signal to an analog signal, and relates to its method.

Description of the Related Art A digital-to-analog converter of a pulse width modulation (PWM) system is known. This type of digital-to-analog converter feeds a pulse signal, which is modulated by pulse width according to a digital value, to a low pass filter, and converts it to an analog value. A digital-to-analog converter of a pulse density modulation (PDM) system is also known. This type of digital-to-analog converter feeds a pulse signal, which is modulated by pulse density according to a digital value, to a low-pass filter, and converts it to an analog value. In any of those digital-to-analog converters, the response speed (conversion speed REF.29370 digital / analog) depends on a time constant of the low pass filter. FIGURE 1 is a functional block diagram of a conventional digital-to-analog converter of a PWM system. The digital-to-analog converter shown in FIGURE 1 comprises a PWM signal that generates the section 103 having a counter 101 and a comparator 102, and a low pass filter 104. The counter 101 cyclically counts a count value 105 having the same number of bits as the number of fixed bits of a D / A conversion, and produces the count value 105 for the comparator 102. The comparator 102 compares the value of the count 105 with a fixed digital value 106, and produces a signal PWM 107 for the low pass filter 104. More specifically, the comparator 102 modulates the fixed digital value 106 by pulse width using the count value 105 (a varying working relationship). The pulse signal, which is obtained by modulating the fixed digital value 106 by pulse width, is the PWM signal 107. The low pass filter 104 removes a high frequency component from the PWM signal 107, thereby producing a value of voltage corresponding to digital value 106, that is, an analog signal 108.

The previous digital-to-analog converter of a PWM system has the advantage that the scale of a circuit is smaller than that of a general digital-to-analog converter of the resistance array type. However, in the previous digital-to-analog converter of a PWM system, the response speed depends on the time constant of the low-pass filter 104. To obtain the same degree of response speed as the general digital-to-analog converter of the resistance array type, the operating frequency of the counter 101 provided in the PWM signal generating the section 103 must be increased further, and this increases the current consumption.

BRIEF DESCRIPTION OF THE INVENTION An object of the present invention is to provide a digital-to-analog converter, which can achieve a high response speed when operating with a low speed counter to a minimum to reduce current consumption, and its method . The present invention provides a digital-to-analog converter comprising: a pulse width modulator for modulating a fixed current value by pulse width using the value of a count to generate a pulse width modulation signal; a low pass filter to remove a high frequency component of the pulse width modulation signal to produce an analog signal; and a calculator of the real fixed value to multiply a difference between a current target fixed value and a previous fixed target value by a coefficient determined from a time constant of the low pass filter and a target fixed value cycle, and to add the multiplied value to the previous fixed target values to calculate the current fixed value. According to the previous structured analog-to-analog converter, the pulse modulation is performed using the current fixed value, which may contain a variation, which is larger than a target digital value in a unit time, at analog output value of the low pass filter. The analog signal, which is the analog output of the low pass filter, can vary at higher speeds. As a result, it is not necessary to perform pulse width modulation with the value of the frequency count that is most needed. This can reduce the current consumption. Also, the present invention provides a digital-to-analog converter comprising a pulse density modulator, instead of the pulse width modulator, to invert the upper and lower bits of the count value to modulate the fixed value by pulse density. current with the value of the inverted count and to send it to the low pass filter. According to the above structured analog-to-analog converter, the analog signal having high stability and a small number of fluctuations compared to the pulse width modulator can be generated. In addition, the present invention provides a digital-to-analog converter comprising a coefficient adjustment function for changing the coefficient, whereby the difference between the target fixed value and the previous fixed fixed value is multiplied according to the polarity of the the difference. According to the previous structured digital-to-analog converter, since the response speed can be adjusted exactly by positive and negative changes, it is possible to achieve a high response speed using the low-speed operating frequency, thereby making it possible to reduce the current consumption. In addition, the present invention provides a digital-to-analog converter comprising: a determination section to determine whether or not the actual fixed value exceeds a fixed capable interval; and a selection section for selecting the current target fixed value as the real fixed value when the actual fixed value exceeds the fixed capable interval as a result of the determination. / According to the previous structured digital-to-analog converter, the A / D conversion procedure in the vicinity of the maximum value of the fixed capable interval and the minimum value thereof can be executed without having a complicated procedure. In other words, the A / D procedure can be executed exactly without increasing the current consumption. Also, the present invention provides a digital-to-analog converter comprising: a determination section for determining whether or not the actual fixed value exceeds a fixed capable interval; and a correction section to extend a fixed cycle to decrease the coefficient, whereby the difference between the fixed objective fixed value and the previous fixed fixed value are multiplied to calculate the cycle of the real fixed value when the real fixed value exceeds the capable interval fixed as a result of the determination. According to the previous structured analog-to-analog converter, an analog signal can be generated at a higher speed even in the vicinity of the maximum value of the fixed capable interval and the minimum value thereof. Therefore, the function that generates the PWM or PDM signal can be operated at low speed throughout the fixed capable interval, thus making it possible to improve the reduction in current consumption.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing a general digital-to-analog converter of the PWM type; Figure 2 is a block diagram showing a digital-to-analog converter according to a first embodiment of the present invention; Figure 3 is a block diagram showing a digital-to-analog converter according to a second embodiment of the present invention; Figure 4 is a block diagram of a mobile radio terminal apparatus according to a third embodiment of the present invention; Figure 5 is a block diagram showing a digital-to-analog converter according to a fourth embodiment of the present invention; and Figure 6 is a block diagram showing a digital-to-analog converter according to a fifth embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED MODALITIES The modalities of the digital-to-analog converter of the present invention will be described specifically with reference to the drawings. (First mode) Figure 2 is a block diagram showing the digital-to-analog converter according to the first embodiment of the present invention. The digital-to-analog converter shown in Figure 2 comprises a signal generating section PWM 203 having a counter 201 and a comparator 202, and a low pass filter 204, and a fixed value calculator 205. The fixed value calculator 205 obtains a difference between a current target digital value 206 and a previous target digital value 206. Next, the fixed value calculator 205 multiplies the difference obtained by a coefficient, which is determined by a time constant of the low pass filter 204 and a fixed cycle of the target digital value 206. Next, the fixed value calculator 205 adds the multiplied value to the previous objective digital value 206 to calculate the actual fixed value 207 which corresponds to the current target digital value. The counter 201 cyclically counts a counting value 208 having the same number of bits as the number of bits to be used in a digital-to-analog conversion. The value of the count 208 produced by the counter 202 is sent to the comparator 202. The comparator 202 compares the value of the count 208 with the real fixed value 207. Next, the comparator 202 produces the PWM signal 207, which has been obtained in based on the result of the comparison, the low pass filter 204. In other words, the comparator 202 modulates the real fixed value 207 by pulse width using the value of the count 208. Then, the comparator 202 produces the PWM signal 209, which is the result of the modulation, to the low pass filter 204. As mentioned above, the real fixed value 207 is multiplied by the coefficient to obtain a numerical value, which is larger than the target digital value 206. By therefore, the pulse width of the PWM signal, which has been obtained by modulating the real fixed value 207 by pulse width, is larger than the target digital value 206. The low pass filter 204 produces an analog voltage of which removes a high frequency component. The PWM signal 209 is modulated by pulse width by the actual fixed value 207, which is larger than the target digital value 206. Therefore, the analog voltage produced by the low pass filter 204 rises abruptly since the Pulse width of the PWM signal in a high level state is large. Next, the operation of the previous structured digital-to-analog converter will be explained. It is assumed that the current target digital value is DCRU, the previous target digital value is DPRE, the digital target fixed cycle 206 is T, the time constant of the low pass filter is Ct, a ratio of the digital value to the analog voltage is R, and the step time is t. If the objective digital value 206 is set directly on the comparator 202, the analog voltage produced by the low pass filter 204 can be expressed by the following equations (1) and (2): When DCUR >; DPRE, Analogue Voltage = RX [DPRE + (Do - DPRE). { l-exp (-t / Ct)} ] ... (1) When DPRE > DCUR, Analog Voltage = RX [DPRE + (DQR - DPRE). { exp (-t / Ct)} ] ... (2) In this case, the actual analog voltage becomes small since the variation of the digital value is multiplied by the coefficient. { l-exp (-t / Ct)} ] o. { exp (-t / Ct)} ] • Due to this, in this modality, the variation of the digital value is multiplied by the inverse of the coefficient so that such an apparent digital fixed target value becomes large. In other words, the actual fixed value 207 can be calculated from the following equations (3) and (4): When DCUR > DPRE, Real fixed value = DPRE + (DCUR - DPRE) /. { l-exp (-T / Ct)} ... (3) When DPRE > DCU, Real fixed value = DPRE - (DCUR - DPRE) /. { exp (-T / Ct)} ... (4) Also, in the case where the target digital value DCU? which is currently fixed, is exactly the same as the previous objective digital value DPRE, the current analog voltage reaches the analog voltage that corresponds to the target digital value prior DPRE. For this reason, the current target digital value Dcu is set to the target digital value before DPRE again. The actual fixed value 207, which the calculator of the fixed value 205 has calculated from equations (3) and (4), becomes the numerical value, which is sufficiently larger than the objective digital value 206. The comparator 202 modulates by pulse width the actual fixed value 207 using the count value to generate the PWM signal 209. For example, if the calculated fixed fixed value 207 is ten times larger than the target digital value 206, the pulse width of the PWM signal 209 in the high level state is increased 10 times. In comparison with the low pass filter to which the PWM signal having the pulse width obtained by direct pulse modulation the target digital value 206, the use of the low pass filter 204, to which it is fed into the PWM signal 209 which it has such a pulse width of 10 times, resulting in an abrupt increase in the analog voltage. Further, at the time when the analog output of the low pass filter 204 reaches the analog voltage corresponding to the target digital value 206, the target digital value 206 is updated and the actual fixed value 207 to be sent to the comparator 202 is reset. In other words, the fixed value 207, which is greater than the target digital value 206, is set in the comparator, so that the analog output of the low pass filter 204 may vary abruptly. In addition, it is possible to reduce the time required when the analog output of the low pass filter 204 reaches the analog voltage corresponding to the target digital value 206 without increasing the operation speed of the counter 201. Also, at the time when the analog output of the low pass filter 204 reaches the analog voltage corresponding to the target digital value 206, the actual fixed value 207 to be set in the comparator 202 is reset. Therefore, the analog voltage corresponding to the target digital value 206 can be obtained. Thus, according to the first embodiment, the numerical value of the real fixed value 207 to be set in the comparator 202 is increased. As a result, an analog signal 210 can be varied at high speed even if the counter 203 is "operated with the same frequency of operation as in the conventional case." On the contrary, this can decrease the operating frequency of the counter 203, so that the current consumption can be reduced. (Second mode) Figure 3 is a block diagram showing the digital-to-analog converter according to the second embodiment of the present invention.The digital-to-analog converter shown in the Figure 3 further comprises a bit inversion section 301 in addition to the same structural elements as the first mode.The bit inversion section 301 inverts the upper and lower bits of the count value 208 of the '201 counter, and sends the result to the comparator 202. The value of the count reversed by the bit inversion section 301 is known as the value of the inverted count 302. In this way it is provided in the bit inversion section 301, so that the signal produced by the comparator 202 results in a signal (PDM signal) 303, which is modulated by pulse density. In other words, a section that generates the PDM signal 304 is constituted by the counter 201, the bit inversion section 301, and the comparator 202. The signal PDM 303 produced by the section ue generates the signal "PDM 304 is passed through the low pass filter 202 so that it is converted to the analog signal 210. According to the second embodiment, the upper and lower bits of the The value of the count 208 is reversed, and the actual fixed value 207 is modulated by pulse density by using the value of the inverted count 202. Since the pulse width is short in the modulation of the pulse density, the signal can be generated. analog, which is more stable than the pulse width modulation of the first mode, namely, the current consumption can be reduced in a manner similar to the first mode, and an analog signal having a small fluctuation can be generated. mode) This embodiment shows an example of a mobile radio terminal apparatus for effecting a gain control of a transmission gain amplifier by using the digital converter. ital to analog of the PDM system explained in the second modality. FIGURE 4 shows the functional block of the mobile radio terminal apparatus having the digital-to-analog converter of the PDM system of, according to the third embodiment. It should be noted that the same numerical references were added to the portions that have the same functions as the digital-to-analog converter of the PDM system explained in the second embodiment. The device of the mobile radio terminal of the FIGURE 4 comprises an antenna 401, a frequency conversion section 402, a gain control amplifier 403, a quadrature modulator 404, a data modulator 405, a transmit power control section 406, the fixed value calculator 205, the generating section of the PDM signal 204 and the low pass filter 104. The data modulator 405 digitally modulates the information data that must be transmitted to generate a baseband signal. Next, the data modulator 405 produces the baseband signal generated for the quadrature modulator 404. The quadrature modulator 404 modulates the baseband signal in quadrature fashion, and generates an intermediate frequency band signal. Next, the quadrature modulator 404 sends the intermediate frequency band signal to the gain control amplifier 403. The gain control amplifier 403 amplifies the amplitude of the intermediate frequency band signal to send it to the frequency converter 402. The frequency converter 402 converts the amplified intermediate frequency band signal to a radio frequency band, and the radio frequency band is radiated into space through the antenna 401. The transmission power control 406 controls the power level that must be transmitted. Specifically, the transmission power control section 406 sends the digital value, which corresponds to the analog signal having a target power level, to the fixed value computer 205 as the target digital value 206. The fixed value computer 205 generates the real fixed value 207 to which the variation greater than the fixed target value is added by the calculation method explained in the first modality. Next, the fixed value calculator 205 sends the real fixed value 207 to the section generating the PDM signal 304. The section generating the PDM signal 304 converts the PDM signal to the real fixed value 207 as explained in the second embodiment. Next, the PDM signal 303 thus obtained is sent to the low pass filter 204. The low pass filter 204 converts the signal PDM 303 to the analog voltage corresponding to the real fixed value 207 by removing the high frequency component. Next, the low pass filter 204 sends the analog voltage to the gain control amplifier 403 as a transmit gain control signal 400. Next, the gain of the gain control amplifier 403 is controlled by the control signal. transmission gain 400. Thus, according to the third embodiment, the transmission power control that requires the high-speed response can be executed using the digital-to-analog converter of the PDM system that has difficulty responding at high speed due to the time constant of the low pass filter 204. Also, since the counter and the digital-to-analog converter of the PDM system can be operated at low speed, it can be improved (the reduction in power consumption. 4, even if the section generating the signal PWM 203 explained in the first mode is used instead of the section that generates the signal PDM 304, pu ede obtain the same effect as with the third modality.

(Fourth embodiment) The fourth embodiment of the present invention shows an example of the digital-to-analog converter, which determines whether or not the digital value to be set exceeds a certain interval, and which uses the target digital value when the value exceeds the interval, in addition to the structural elements of the digital-to-analog converter of the first mode. FIGURE 5 shows the functional block of the digital-to-analog converter according to the fourth embodiment. It should be noted that the same numerical references were added to the portions that have the same functions as the digital-to-analog converter of the first mode. The digital-to-analog converter shown in FIGURE 5 comprises a section that determines the fixed value 501 and a section that selects the fixed value 502 in addition to the structural elements of the first embodiment. The section determining the fixed value 501 determines whether or not the actual fixed value 207 produced by the fixed value computer 205 exceeds a fixed interval (upper and lower limits of a dynamic range) of the comparator 202, and the result of the determination 503 of the section selecting the fixed value 502, If the result of the determination 503 exceeds the fixed interval, the section that selects the fixed value 502 sends the target digital value 206 to the comparator 202 as a value 504 selected fixed. If the result of the determination 503 does not exceed the fixed interval, the section selecting the fixed value 502 sends the real fixed value 207, which has been sent to the fixed value calculator 205, to the comparator 202 as a value selected fixed 504. In this way, according to the fourth mode, the exact analog signal 210 can be generated in the neighborhood of the maximum value of the fixed interval and the minimum value thereof without having a complicated processing. Also, even if the section that determines the fixed value 501 and the section that selects the fixed value 502, which have been added to the fourth mode, are added to the structure of the second mode, the same effect can be obtained. In addition, the digital-to-analog converter of the fourth embodiment can be added to the apparatus of the mobile radio terminal of the third embodiment, so that the gain control of the transmission gain amplifier can be executed by the digital converter to analogical. In this case, the section that determines the fixed value 501 and the section that selects the fixed value 502 are added to the section that generates the signal PDM 304 of FIGURE 4. Or, the section that generates the signal PWM 203 is used in place of the section that generates the signal PDM 304, and also the section that determines the fixed value 501 and the section that selects the fixed value 502 are used. As a result, the effect of the fourth mode can be obtained in the device of the terminal mobile radio in addition to the effect of the third modality. (Fifth embodiment) The fifth embodiment of the present invention shows an example of the digital-to-analog converter, which determines whether or not the digital value to be set exceeds a certain interval, and which prolongs the fixing cycle used in the calculation of the real fixed value and the coefficient decreases when the value exceeds the interval, in addition to the structural elements of the digital-to-analog converter of the fourth mode. FIGURE 6 shows the functional block of the digital-to-analog converter according to the fifth mode. It should be noted that the same numerical references were added to the portions having the same functions as the analog-to-digital converter of the fourth embodiment. The digital-to-analog converter of this embodiment comprises a fixed-value correction section 601 instead of the fixed-value selection section 502. If the result of the determination 503, which has been produced by the determination section of the fixed value 501 exceeds the upper limit of the fixed interval, the fixed value correction section 601 sets the maximum value of the fixed interval in the comparator 102 as a corrected fixed value 602. Conversely, if the result of the determination 503 is lower than the lower limit of the fixed interval, the fixed-value correction section 601 sets the minimum value of the fixed interval in the comparator 102 as a corrected fixed value 602. The maximum value of the fixed interval and the minimum value thereof are replaced respectively in equations (1) and (2) of the calculation of the analog voltage in the first mode. Next, the digital value converted to the analog voltage obtained after the fixed cycle is calculated. More specifically, the above calculations can be expressed by the following equations (5) a (8) When DCUR > DPRE, Analog Voltage = R X [D ^ + (DOR - D ^). { 1-exp (-T / d)} ] . . (5) When DPRE > DCUR, - Analog voltaj = R X [D ^ + (DCUR - DÉSE). { exp (-T / Ct)} ] . . (6) In this way the analog voltage can be obtained, and the converted digital value can be obtained as follows: When DCUR > DPRE, Converted digital value = DURE - (Eb - D ^). { 1-exp (-T / d)} ] . . (7) When DPRE > DCUR, Converted digital value = - (EbjR - Ebe). { exp (-T / Ct)} ] . . (8) when the fixed digital value is DCUR, the previous fixed value is DPRE, the canned cycle is T, the time constant of the low pass filter is Ct, and the ratio of. The digital value at the analog voltage is R. In this way a converted digital value 603 generated by the fixed value correction section 601 is sent to the fixed value calculator 205. The fixed value calculator 205 uses the converted digital value 603 as the value fixed prior to a subsequent calculation time. According to the fifth embodiment of the present invention, the analog signal 210 can be generated at a maximum response speed over the entire fixed interval. Even if the fixed value determination section 501 and the fixed value correction section 601, which have been added to the fifth mode, are added to the second mode, the same effect can be obtained.

In addition, the digital-to-analog converter of the fifth embodiment can be added to the mobile radio terminal apparatus of the third embodiment, so that the gain control of the transmission gain amplifier can be executed by the digital converter to analogical. In this case, the fixed value determination section 501 and the fixed value correction section 601 are added to the generating section of the PDM signal 304 of FIGURE 4. 0, the generating section of the PWM signal 203 of FIGURE 6 instead of the generator section of the PDM signal 304, and also the fixed value determining section 501 and the fixed value correction section 601 are used. As a result, the effect of the fifth mode in the apparatus of the mobile radio terminal, in addition to the effect of the third modality. As is obvious from the above explanation, according to the present invention, the real fixed value that the variation has, which is greater than the target fixed value, is fixed, so that the analog signal can vary at high speed. Consequently, it is not necessary to carry out pulse width modulation with the value of the counting of the frequency of operation that is most necessary. This can reduce the current consumption.

Also, the value that the variation has, which is greater than the target fixed value, is set, so that the analog signal can be varied at high speed. Consequently, it is necessary to carry out the modulation by density of impulses with the value of the counting of the frequency of operation that is more necessary. This can improve the reduction in the "current consumption." In addition, the analog signal having high stability and a small number of fluctuations compared to the pulse width modulation system can be generated. to be adjusted exactly for positive and negative changes, it is possible to obtain a high-speed response using the low-speed operating frequency, thereby making it possible to reduce the power consumption.This request was based on Japanese Patent Applications No. HEI10 -29326 filed on June 27, 1998, No. HEI10-258355 filed on September 11, 1998 all the contents of which is expressly incorporated herein by reference.

It is noted that in relation to this date, the best method known to the applicant to carry out the aforementioned invention, is that which is clear from the present description of the invention. Having described the invention as above, property is claimed as contained in the following:

Claims (14)

1. A digital-to-analog converter for modulating by pulse width a digital target value to be converted to an analog signal, characterized in that it comprises: a counter for counting a predetermined count value repeatedly; a pulse modulator for modulating, by pulse width, a real fixed value corresponding to the target digital value using the count value produced by the counter to generate a pulse width modulation signal; a low pass filter to remove a high frequency component of the pulse width modulation signal to generate an analog signal; and a calculator of a fixed value for multiplying a difference between a current objective digital value and a previous objective digital value by a coefficient determined from a time constant of the low pass filter and a refresh cycle of the target digital value, and to add the multiplied value to the previous digital value to calculate the real fixed value. The digital-to-analog converter according to claim 1, characterized in that the fixed value calculator changes the coefficient by which the difference between the current digital objective value and the previous objective digital value is multiplied according to a polarity of such difference. The digital-to-analog converter according to claim 1, characterized in that it further comprises ": a determination device for determining whether or not the real fixed value exceeds a fixed capable interval, and a selector for selecting the current digital target value when the calculated fixed real value exceeds the fixed capable interval as a result of the determination, and to select the calculated fixed real value when the calculated real fixed value exists in the fixed capable range to feed the selected value to the pulse width modulator as the real fixed value 4. The digital-to-analog converter according to claim 1, characterized in that it further comprises: a determination device to determine whether or not the current fixed value exceeds a fixed capable interval, and a fixed value corrector for prolong a fixed cycle of the target digital value when the actual digital value exceeds the fixed capable interval The result of the determination, and to decrease the coefficient by which the difference between the current digital objective value and the previous objective digital value are multiplied to calculate the real fixed value. The digital-to-analog converter according to claim 1, characterized in that it further comprises: a determination device to determine whether or not the real fixed value exceeds a fixed capable interval; and a fixed value corrector to select a physical capable maximum value or a fixed fixed minimum value as the real fixed value when the actual fixed value exceeds the fixed capable interval as a result of the determination, and to calculate an analog output value of the filter from low pass to a next update period of the time constant of the low pass filter and the update cycle of the target digital value to obtain the real fixed value corresponding to the calculated value. 6. A digital-to-analog converter for modulating by pulse density a target digital value to be converted to an analog signal, characterized in that it comprises: a counter for counting a predetermined count value repeatedly; a pulse modulator for modulating by pulse density a real fixed value corresponding to the target digital value using the count value produced by the counter to generate a pulse density modulation signal; a low pass filter to remove a high frequency component of the pulse density modulation signal to generate an analog signal; and a fixed value calculator for multiplying a difference between a current objective digital value and a previous objective digital value by a coefficient determined from a time constant of the low pass filter and a refresh cycle of the target digital value, and to add the multiplied value to the previous digital value to calculate the real fixed value. The digital-to-analog converter according to claim 6, characterized in that the pulse density modulator inverts the upper and lower bits of the count value to modulate the real fixed value with the value of the inverted count by pulse density. 8. A mobile radio terminal apparatus, characterized in that it comprises: a digital-to-analog converter according to claim 1; a gain control amplifier for digitally modulating information data to amplify the digital modulation signal. For a gain according to an analog signal produced by the digital-to-analog converter; and a radio unit for converting the amplified analog signal by gain to a radio frequency band to be transmitted. 9. A mobile radio terminal apparatus, characterized in that it comprises: a digital-to-analog converter according to claim 6; a gain control amplifier for digitally modulating information data to amplify the digital modulation signal by a gain according to an analog signal produced by the analog digital converter; and a radio unit for converting the amplified analog signal by gain to a radio frequency band to be transmitted. 10. A method for modulating by pulse width a target digital value to be converted to an analog signal, characterized in that it comprises the steps of: counting a predetermined count value repeatedly; modulating by pulse width a real fixed value corresponding to the target digital value using a count value produced by the counter to generate a modulation signal per pulse width; feeding the pulse width modulation signal to a low pass filter to remove a high frequency component of the pulse width modulation signal to generate an analog signal; multiplying a difference between a current objective digital value and a previous objective digital value by a coefficient determined from a time constant of the low pass filter and a refresh cycle of the target digital value; and adding the multiplied value to the previous objective digital value to calculate the real target value. The method according to claim 10, characterized by further comprising the steps of: determining whether or not the actual fixed value exceeds a fixed capable interval; and selecting the target digital value as the real fixed value when the actual fixed value exceeds the fixed capable range as a result of the determination. * 1

2. The method according to claim 10, characterized in that it comprises the steps of: determining whether or not the real fixed value exceeds a fixed capable interval; and calculating the real fixed value by prolonging the update cycle and decreasing the coefficient by which the difference between the current objective digital value and the previous objective digital value is multiplied when the actual fixed value exceeds the fixed capable interval as a result of the determination. The method according to claim 10, characterized by further comprising the steps of: determining whether or not the actual fixed value exceeds a fixed capable interval; selecting a maximum capable value or a minimum value capable of being the real fixed value when the real fixed value exceeds the fixed capable interval as a result of the determination; and calculating an analog output value of the low pass filter passed to a next update period of the time constant of the low pass filter to produce the analog signal and the fixed cycle of the target digital value when the maximum value or the minimum value they are selected as the real fixed value. 14. A method for modulating by pulse density a target digital value to be converted to an analog signal, characterized in that it comprises: continuing a predetermined count value repeatedly; multiplying a difference between a current objective digital value and a previous objective digital value by a coefficient determined from a time constant of a low pass filter and a refresh cycle of the target digital value; add the multiplied value to the previous digital value to calculate a real fixed value; inverting the upper and lower bits of the count value to modulate by pulse density the real fixed value with the value of the inverted count to generate a pulse density modulation signal; and feeding the pulse density modulation signal to the low pass filter to remove a high frequency component of the pulse density modulation signal to generate an analog signal.