MXPA99000582A - Data transmission method and game system constructed by using the method - Google Patents

Abstract

A new method by which data are transmitted between a game machine and its peripheral devices;and a machine constructed by using the method. Serial transmission data are divided into data of odd bit sequence and data of even bit sequence. The bits of the odd bit sequence data are arranged between pulses of first pulse train signals at certain intervals to generate a first pulse train signal (SDCKA). The bits of the even bit sequence data are arranged between pulses of second pulse train signals at certain intervals to generate a second pulse train signal (SDCKB). The time bases of the first and second pulse sequence signals are mutuallyadjusted so that the clock component of the first pulse train signal is positioned in the data part of the second pulse train signal and the clock component of the second pulse train signal is positioned in the data part of the first pulse train signal. Data are transmitted by using the adjusted first and second pulse train signals (SDCKA, SDCKB).

Description

SYSTEM OF TRANSMISSION OF DATA AND GAME SYSTEM TO USE THE SAME TECHNICAL FIELD The present invention relates to interface technology for providing mutual connection between data processing devices, which conduct data processing, and peripheral devices, which conduct the input / output of information, and the like, and more particularly , refers to a new standard interface technology related to connections between game devices and related peripheral devices.

BACKGROUND OF THE INVENTION The methods of data transmission to be used in data communications between the main unit of an image processing device and peripheral devices related thereto include the following: • Philips, busbar system l2C In this system, Serial data and a serial clock are transmitted through two cables. The data and the clock are physically separated, and the transmission / reception of data and reproduction are possible through the simplest method. The busbar l2C is described, for example, in the Philips bus instruction manual l2C (January 1992). • SGS - Thomson DS link system In this system, a signal, data and strobe signals are transmitted through two wires. A clock signal is reproduced through the data signal and the strobe signal. When the transmitted data changes to a different value, only the data signal changes. When the transmitted data is the same value, only the strobe signal changes. For example, if the data transmitted in the data signal changes from "0" - "1", or "1" - "0", then the strobe signal does not change. If the data transmitted in the data signal does not change, for example, "0" - "0", or "i" _. «< ] »_ Then the strobe signal only changes. Therefore, by adopting an exclusive OR operation for the data signal and the strobe signal, it is possible to reproduce a clock signal. The DS link system is introduced by Nikkei Electronics, Vol. 675, (November 4, 1996, pages 167-171). In consumer-oriented devices, such as gaming devices, it is necessary to use a data transmission system and standard interface connection that can be implemented at low cost. However, in the busbar system I2 mentioned above, since the transition edge of the data signal has the same time as the transition edge of the clock, it is not possible to use the clock signal directly on the reproduction side. of data (demodulation). In addition, in the case of the DS link system, exclusive OR logic is applied to the data signal and the strobe signal to produce a synchronization clock. The data signal must be displayed using this clock. Therefore, the level of simplicity of the interface circuit structure does not adequately satisfy the conditions for domestic gaming devices, where a low cost is a very important requirement. Accordingly, it is an object of the present invention to provide a data transmission system for an interface having inexpensive circuit composition, which can be applied to an image processing device, such as a home gaming system. It is another object of the present invention to provide a data transmission system for an interface, wherein the data can be separated from a signal carrying data through a simple circuit composition.

It is a further object of the present invention to provide a game device and a related peripheral device comprising interfaces, wherein the data can be separated from a signal carrying data through a simple circuit composition. It is yet another object of the present invention to provide a basic technology for developing various types of peripheral devices, proposing a novel interface technology between a game device and a peripheral device.

DESCRIPTION OF THE INVENTION In order to achieve the above objects, the data transmission system according to the present invention is a data transmission system for transmitting data by distributing a serial data item in first and second data signals, wherein the first data signal contains each of the odd-numbered bits of the serial data, respectively distributed among pulses of a first clock formed through a pulse sequence having a uniform range; the second data signal contains each of the even-numbered bits of the serial data, respectively distributed among a pulses of a second clock formed through a pulse sequence having the same frequency as the first clock signal; the first data signal is transmitted so that the pulse edge of its clock signal component is located in the data section of the second data signal on the same time axis; and the second data signal is transmitted so that the pulse edge of its clock signal component is located in the data section of the first clock signal on the time axis (Fig. 10, Fig. 11, Fig. 50, Fig. 54). In addition, in a data transmission system, wherein a data frame defined according to a transmission format comprising, at least, a start pattern carrying start data information, a data pattern carrying data In series, and a final pattern that carries final data information, are transmitted by distributing the data frame between a first and a second data signal, the data transmission system according to the present invention is a data transmission system , wherein the start pattern is created by setting the first data signal to a constant value and setting the second data signal as a first pulse sequence signal; the data pattern is created by forming the first data signal by distributing each of the odd number bits of the serial data respectively between pulses of a second pulse sequence signal having a constant interval, and forming the second data signal distributing each of the bits with even number of the series data respectively between the pulses of a third pulse sequence signal, which is displaced by a prescribed amount of the position on the time axis of the second pulse sequence signal; and the final pattern is created by setting the second data signal to a constant value, and setting the first data signal as a fourth pulse sequence signal. (Fig. 11, Fig. 12, Fig. 50, Fig. 54). Through this composition, it is possible to create a communications interface, where the modulation and demodulation circuits can be composed relative and simply through a small number of data lines (mainly, two data lines). Preferably, the superimposed data are isolated by closing the level of a data signal of the first and second data signals at the pulse edge of the clock signal component of another data signal. In this way, it is possible to isolate the superimposed data through a simple circuit composition (Fig. 10, Fig. 28, Fig. 29, Fig. 50). In a gaming device, which requires the transmission or reproduction of information required for a game by transmitting two data signals (SDCKA, SDCKB) simultaneously to a single device or to a plurality of peripheral devices through a signal transmission path, the game device according to the present invention comprises: means for creating start pattern to create a start pattern represented by two data signals, wherein a first data signal is set to a constant value state (or value) fixed) during a first period, and a second data signal is set to a state of the clock signal during the first period (Fig. 13 (a), Figs. 14, 58, 204c); data pattern creation means for creating a data pattern represented by two data signals, wherein the data that will be transmitted to the peripheral device is divided into two data sequences, and a first data signal is created by inserting each bit of data. the first data sequence respectively between the pulses of a first clock signal, and a second data signal is created by inserting each bit of the second data sequence respectively between the pulses of a second clock signal having the same frequency as, and a prescribed phase difference of, the first clock signal (Figs 10, 204e); means of creating the final pattern to create a final pattern represented by two data signals, wherein the second signal is set to a constant value state (or fixed value) during a second period, and the first signal is set to a clock state during the second period (Figs 13, 58, 204c); and means of creating a frame to create a frame represented by two data signals, containing the start pattern, the data pattern and the final pattern, and transmitting the frame as a transmission unit to the peripheral device (Figs 58, 204c) ). Preferably, the data is serial data, the first data sequence is a data sequence comprising the odd number bits of the serial data, and the second data sequence is a data sequence comprising the even number bits of the serial data. In addition, the prescribed phase difference is determined so that the pulse edge of the clock signal contained in a data signal of the two data signals representing the data pattern is located in the data section of the other signal of data on the time axis, and the pulse edge of the clock signal contained in the other data signal is located in the data section of the aforementioned data signal on the time axis (Figs. ). The game device for implementing the above data transmission method can easily separate the data since one or both of the two data signals comprise a transmission clock component. The modulation and demodulation circuit can be constructed relatively and simply. Preferably, the data pattern comprises a command and a parameter, and the parameter comprises, at least, the direction of the peripheral device connected to the signal transmission path, which is to receive the frame (FIG. 7, FIG. 48). Since the signal format for data communications between the game device and the peripheral device is standardized through a frame format, compatibility between the game device and a plurality of peripheral device types can be easily guaranteed. For the signal transmission path, wired data signal lines, or wireless radio communication channels (Fig. 95), or optical communication channels (Fig. 96) or a combination of these can be used. In a peripheral device for a game device, which sends information required for a game to a game device having an input / output port or a plurality of input / output ports transmitting two data signals simultaneously, the device game according to the present invention comprises: means of creating start pattern to create a start pattern represented by two data signals, wherein a first signal is set to a constant value state (or fixed value) during a first period , and a second signal is set to a clock state during the first period; means for creating a data pattern to create a data pattern represented by two data signals, wherein the data that will be transmitted to the same device is divided into two data sequences and each bit of the first sequence is inserted respectively between pulses of data. a first clock signal, and each bit of the second data sequence is inserted respectively between pulses of a second clock signal having the same frequency as, and a prescribed phase difference of the first clock signal; means for creating the final pattern to create a final pattern represented by two data signals, wherein the second signal is set to a constant value state (or fixed value) during a second period and the first signal is set to a state of clock signal during the second period; and means for creating a frame to create a frame represented by two data signals, containing the start pattern, the data pattern and the final pattern, and transmitting the frame as a transmission unit to the game device. Preferably, the data is serial data that is easily divided into two data sequences, the first data sequence is a sequence of data that - it comprises the odd-numbered bits of the serial data, and the second data sequence is a data sequence comprising the even-numbered bits of the serial data. As well as serial data, block data can also be managed through a buffer to collect the data. Preferably, the prescribed phase difference is determined such that the pulse edge of the clock signal contained in a data signal of the two data signals representing the data pattern is located in the data section of the other clock signal. data on the time axis, and the pulse edge of the clock signal contained in the other data signal is located in the data section of a data signal on the time axis (Fig. 10, Fig. 50) . In this way, it is easily possible to isolate the superimposed data on a data signal through the other clock. Preferably, the data pattern comprises a command and a parameter, and the parameter comprises, at least, the address of the input / output port of the game device, which is to receive the frame (Fig. 48, Fig. 57) . Preferably, the data pattern comprises a command and a parameter, the parameter comprises, at least, a source address indicating the direction on the transmission path of the peripheral device transmitting the frame, and this source address created based on the identification information of the peripheral device representing the type of peripheral device already recorded by the peripheral device, and information related to the input / output port to which the peripheral device is connected as indicated by the game device (Fig. 58). In a peripheral device for conducting data communications with a gaming device comprising an input / output port or a plurality of input / output ports through a data transmission path connecting to one of the input / output ports of the game device, the peripheral device according to the present invention comprises: first storage means for pre-storing the identification information for the peripheral device representing the type of peripheral device; second storage means for storing the input / output port information representing the input / output port to which the data transmission path is connected, as indicated by the game device; and source address creation means for creating a source address for the peripheral device, which is appended to the data that will be transmitted to the game device, based on the peripheral device identification information and the port information. entry / exit (Fig. 58). Through this composition, the game device is able to identify from the received transmission data, the address of the peripheral device over the data transmission path and the type of that peripheral device. In a peripheral device for conducting data communications with a gaming device through a data transmission path by connecting to either an individual input / output port or a plurality of input / output ports provided in the same gaming device , the peripheral device according to the present invention comprises: an individual base connector, which is connected to the data transmission path; an individual expansion connector or plurality of expansion connectors, which are connected to the data transmission path through the base connector, in order to connect other peripheral devices to the data transmission path; and an input / output controller for conducting data communications with the game device through the base connector; wherein the input / output controller comprises: first storage means for pre-storing the peripheral device identification information representing the fact that the device is a peripheral device, which is to be directly connected to the game device; second storage means for storing the input / output port information representing the input / output port to which the data transmission path is connected, as indicated by the game device; connection identification means for creating connection information representing the connection status of the other peripheral devices identifying whether or not an additional peripheral device is connected to any of the expansion connectors; and source address creation means for creating a source address containing the peripheral device identification information, the input / output port information and the connection information, which is to be appended to the transmission data (Fig. 58). Preferably, the identification means determines whether or not there is a connection in the expansion receptacles by identifying the voltage level of a particular terminal of the expansion connectors, which is connected to a composite level displacement circuit so that a voltage of derivation is supplied by the additional peripheral device. "In a peripheral expansion device, which is connected to an expansion connector of the aforementioned peripheral device, the peripheral expansion device according to the present invention comprises: first storage means for storing the connector identification information representing the number of a - expansion connector as indicated by the input / output controller through the expansion connector, then connect to the expansion connector; second storage means for pre-storing the peripheral expansion device information representing the fact that the device is a peripheral device, which is to be connected to the expansion connector; third storage means for storing the input / output port information representing the output input port to which the data transmission path is connected, as indicated by the gaming device through the data transmission path, the base connector and expansion connector; and source address creation means for creating a source address containing the peripheral device expansion information, the input / output port information and the connection information, which is to be appended to the transmission data (Fig. 59). In a gaming device comprising a single input / output port or a plurality of input / output ports for connecting through a main data transmission path (busbar M) a peripheral base device composed so that a individual expansion peripheral device or a plurality of peripheral expansion devices can be connected thereto through auxiliary data transmission paths (bus bar LM), the game device according to the present invention comprises: an input controller / output for conducting intermittent data communications with any of the peripheral devices through the frame signals; wherein the data communications are conducted in accordance with a format by which a relevant peripheral device responds to instructions by the input / output controller; Frame signals include: a start pattern representing the beginning of a data pattern, a data pattern carrying transmission data, and a final pattern representing the end of a data pattern; the data pattern comprises a command and a parameter; the parameter comprises a destination address and a source address; and both the destination address and the source address are created including information regarding the main data transmission path used in communications, the base device classification / peripheral device expansion device involved in communications and the path of auxiliary data transmission used in communications (Fig. 58, Fig. 59). Preferably, the auxiliary data transmission paths are respectively connected in parallel to the main data transmission path, and direct data communications are conducted between the game device and the peripheral expansion devices. Preferably, the base peripheral devices and the peripheral expansion devices each respectively maintain inherent information containing information about the type of the peripheral device and information inherent in the device, and the game device reads this inherent information through the data transmission . The game device can identify the compatibility between the game application and the peripheral device by referring to the inherent information. In this way, it is possible to avoid the use of game devices, which are incompatible with the so-called "connect and use" systems or applications. Preferably the data transmission path is constituted by two data lines, and two data signals formed by dividing the frame signal are used to transmit the two data lines, respectively. In this way, it is possible to apply the method of data transmission according to the present invention to a gaming device. In a base peripheral device for a game device, to which a peripheral individual expansion device or a plurality of peripheral expansion devices can be connected through auxiliary data transmission paths respectively provided, and which is connected to a game device comprising an individual input port / output or a plurality of input / output ports through a main data transmission path, the base peripheral device according to the present invention comprises an input / output controller for conducting intermittent data communications with the game device through frame signals; and the data communications are conducted in accordance with a format by which the input / output controller responds to instructions from the game device; frame signals comprise: a start pattern representing the beginning of a data pattern, a data pattern that carries transmission data and an end pattern representing the end of a data pattern; the data pattern comprises a command and a parameter; the parameter comprises a destination address and a source address; and both the destination address and the source address are created including information regarding the main data transmission path used in communications, the master / slave classification of the peripheral device involved in the communications, and the auxiliary data transmission path used in communications (Fig. 58 and Fig. 59). The base peripheral device for a game device according to the present invention further comprises a connector for connecting to the main data transmission path, and a plurality of expansion connectors for connecting the main data transmission path to the paths of auxiliary data transmission in parallel through the connector. Preferably, the base peripheral device comprises storage means for storing inherent information including the type of peripheral device and information inherent in the device, and this inherent information is transmitted through the data communications in response to a request from the game device. Preferably, the base peripheral device uses the transmission method according to the present invention through a composition, wherein the main data transmission path is constituted by two data lines, and two data signals formed by dividing the frame signal are used to transmit the two data lines, respectively. Through connection to a game device having a plurality of input / output ports, the peripheral device of the above composition conducts data communications with the game device, and creates a source address for itself in the path of transmission of data through the information in relation to the input / output port as indicated by the game device, and information representing the type of peripheral device maintained by the same device. - In a peripheral expansion device for a gaming device, which is connected to a gaming device through an auxiliary data transmission path, a peripheral peripheral device to which peripheral expansion devices can be connected, and a main data transmission path, the peripheral expansion device according to the present invention comprises an input / output controller for conducting intermittent data communications with the game device through frame signals; and data communications are conducted according to a format by which the input / output controller responds to instructions of the game device; Frame signals include: a start pattern representing the beginning of a data pattern, a data pattern that carries transmission data, and an end pattern representing the end of a data pattern; the data pattern comprises a command and a parameter; the parameter comprises a destination address and a source address; and both the destination address and the source address are created including information regarding the main data transmission path used in communications, the base device classification / peripheral device expansion device involved in the communications, and the path of auxiliary data transmission used in communications (Fig. 59). Preferably the main data transmission path consists of two data lines, the auxiliary data transmission path is constituted by two data lines in the upstream direction and two data lines in the downstream direction, and two data signals formed by dividing the frame signal are used to transmit the two lines of data. data respectively. The peripheral expansion device of the above composition conducts data communications with a gaming device comprising a plurality of input / output ports through a peripheral device (base peripheral device) having a plurality of expansion connectors connected in parallel to each other. one of the input / output ports. This creates a source address used in data communications through the information regarding the input / output port, as indicated by the gaming device, and information regarding the used expansion connector, as indicated by the device. peripheral. The source address is simply not an address, but also contains certain information. This type of peripheral device function is suitable for connecting and using systems, and the like. The information storage medium according to the present invention stores programs for making a computer system operate as the aforementioned gaming device (host) or peripheral device.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an illustrative diagram showing examples of a host (gaming device) 1, peripheral device 2 and peripheral expansion device 3; Figure 2 is a block diagram showing a host control system; Figure 3 is a block diagram illustrating the connection relationships between a host and the devices; Figure 4 is a block diagram illustrating the relationships between a host, higher devices and lower devices; Figure 5 is a block diagram illustrating the distribution of the absolute positions; Figure 6 is a block diagram illustrating that the devices have positional permeability when viewed from the host; Figure 7 is a diagram illustrating the composition of a transfer data frame; Figure 8 is a block diagram illustrating the composition of an interface from the software side; Figure 9 is a block diagram illustrating the levels of transmission protocol between a host and a device; Figure 10 is a diagram illustrating a data transmission system; Figure 11 is a diagram illustrating a standard format of a transmission framework; Figure 12 is a diagram illustrating a transmission frame format comprising a CRC option; Figure 13 is a diagram illustrating (a) a start pattern and (b) an end pattern of a synchronization pattern; Figure 14 is a diagram illustrating a CRC option start pattern; Figure 15 is a diagram illustrating an occupancy permit pattern SDCKB; Figure 16 is a diagram illustrating a restart pattern; Figure 17 is a diagram illustrating a communication mode between a host and device function; Figure 18 (a) is a diagram illustrating an aspect of the busbar M, wherein the data communications are conducted intermittently according to a format by which the device functions to respond to the commands of a host; Figure 18 (b) is a diagram illustrating an example wherein the data to be transmitted is long, and the data is transmitted intermittently using a plurality of transmission frames; Figure 19 is a diagram giving an appropriate illustration of the operation of a device; Figure 20 is a diagram illustrating an absolute position (AP) procedure; Figure 21 is a block circuit diagram illustrating a host MIE; Figure 22 is a block circuit diagram illustrating the operational principles of a frame encoder; Figure 23 is a time diagram illustrating the operation of a frame encoder; Figure 24 is a block circuit diagram illustrating the operational principles of an alternate shift register; Figure 25 is a block circuit diagram illustrating the operational principles of an alternative shift register (serial to parallel conversion); Figure 26 is a block circuit diagram illustrating the operational principles of a frame decoder; Figure 27 is a time control diagram illustrating the operation of a frame decoder; Figure 28 is a block circuit diagram illustrating the operational principles of an alternating displacement register (serial to parallel conversion); Figure 29 is a time diagram illustrating the operation of an alternative shift register; Figure 30 is a block diagram giving an approximate illustration of the general composition of a standard controller; Figure 31 is a block diagram illustrating a standard controller MIÉ; Figure 32 is a block diagram illustrating a bus-switching section, which is data-permeable (permeable to position); Figure 33 is a block circuit diagram illustrating a UI device U; Figure 34 is a block circuit diagram illustrating a LEM device MIE; Figure 35 is a flowchart illustrating the identification of a transmission pattern in a MIÉ; Figure 36 is a flowchart illustrating the formation of a standard format frame signal; Figure 37 is a flow diagram illustrating the formation of a frame signal of a format with the CRC option; Figure 38 is a flowchart illustrating the operation through a • occupancy pattern SDCKB; Figure 39 is a flowchart illustrating the transmission of a restart pattern; Figure 40 is a flowchart illustrating a reception operation in a MIÉ; Figure 41 is a flow chart illustrating processing in a case where a start pattern is detected; Figure 42 is a flowchart illustrating the processing in a case where a start pattern comprising CRC is detected; Figure 43 is a flowchart illustrating an example wherein the inherent information carried by the device is read by the host; Figure 44 is a diagram illustrating a plurality of modes for connecting a host, base devices and expansion devices; Figure 45 is a diagram giving a conceptual illustration of the relationship between a guest and the functions (base devices and expansion devices); Figure 46 is a diagram illustrating data communications between a host, base device and expansion device, through a layered model; Figure 47 is a diagram illustrating the connection relationships between a base device and expansion devices; Figure 48 is a diagram illustrating the composition of frame data; Figure 49 is a diagram illustrating a waiting time; Figure 50 is a diagram illustrating the transmission of data through an SDCKA signal and a SDCKB signal; Figure 51 is a diagram illustrating a start pattern and an end pattern; Figure 52 is a diagram illustrating an occupancy permit pattern SDCKB; Figure 53 is a diagram illustrating a restart pattern; Figure 54 is a diagram illustrating a frame format; Figure 55 is a diagram giving an approximate illustration of the data transmission between a host and a peripheral device (base device or expansion device); Figure 56 (a) is a diagram illustrating how data communications are conducted intermittently through a format so that the devices respond to commands transmitted to the devices by the host; Figure 56 (b) is a diagram illustrating an example in which the data to be transmitted is divided into a plurality of data and transmitted intermittently through a plurality of transmission frames, when the data to be transmitted is greater than the volume that can be transmitted by an individual transmission frame; Figure 57 is a diagram illustrating all AP values for a host, base devices and expansion devices; Figure 58 is a diagram illustrating an AP (absolute address) fixation procedure for a base device; Figure 59 is a diagram illustrating an AP (absolute address) fixation method for an expansion device; Figure 60 is a diagram illustrating the transfer of frame data between a host, base device and expansion device; Figure 61 is a diagram illustrating a normal communication procedure between a host and base device (or expansion device); Figure 62 is a diagram illustrating an occupation procedure SDCKB between a host and a base device; Figure 63 is a block diagram illustrating a host MIE; Figure 64 is a block diagram illustrating the composition of a base device; Figure 65 is a block diagram illustrating the composition of a base device MIÉ; Figure 66 is a block diagram illustrating a connection between a base device and an expansion device; Figure 67 is a diagram illustrating a procedure in a case where a base device receives data from a host; FIGURE 68 is a diagram illustrating a procedure in the case where a base device receives data of a volume greater than the host transmission and reception buffer; Figure 69 is a diagram illustrating a procedure in a case where the data is transmitted from a base device to a host; Figure 70 is a diagram illustrating a method in a case where data of a volume greater than the capacity of the MIÉ transmission and reception buffer is transmitted from a base device to a host; Figure 71 is a diagram illustrating a "Device Request" command; Figure 72 is a diagram illustrating a "Request for All States" command; Figure 73 is a diagram that illustrates a "Reset Device "; Figure 74 is a diagram illustrating a" Annihilate Device "command; Figure 75 is a diagram illustrating a "Data Transfer" command; Figure 76 is a diagram illustrating a "Get Condition" command; Figure 77 is a diagram illustrating a "Get Media Information" command; Figure 78 is a diagram illustrating a "Read Block" command; Figure 79 is a diagram illustrating a "Write Block" command; Figure 80 is a diagram illustrating a "Get Ultimate Error" command; Figure 81 is a block diagram showing an example of a base device (game controller) having a relative address; Figure 82 is a block diagram showing an example of a base device (game controller) having an absolute address; Figure 83 is a block diagram showing an example of an expansion device (LCD cartridge) having a relative direction; Figure 84 is a block diagram showing an example of an expansion device (LCD cartridge) having an absolute address; Figure 85 is a block diagram showing an example of an expansion device (memory cartridge) having a relative address; Figure 86 is a block diagram showing an example of an expansion device (memory cartridge) having an absolute address; Figure 87 is a block diagram showing an example of an expansion device (vibration cartridge) having a relative direction. Figure 88 is a block diagram showing an example of an expansion device (vibration cartridge) having an absolute address; Figure 89 is a block diagram showing an example of an expansion device (light gun cartridge) having a relative direction; Figure 90 is a block diagram showing an example of an expansion device (light gun cartridge) having an absolute direction; Figure 91 is a block diagram showing an example of an expansion device (sound input cartridge) having a relative address; Figure 92 is a block diagram showing an example of an expansion device (sound input cartridge) having an absolute address; Figure 93 is a block diagram showing an example of an expansion device (sound output cartridge) with a relative address; Fig. 94 is a block diagram showing an example of an expansion device (sound output cartridge) having an absolute address; Figure 95 is a diagram illustrating an example where a busbar M is constituted by a wireless system (radio); Figure 96 is a diagram illustrating a further example wherein a busbar M is constituted by a wireless system (optical transmission); Figure 97 (a) is a diagram illustrating a busbar connector M of a game controller; Figure 97 (b) is a diagram illustrating an LM busbar connector of a game controller; Figure 98 is a diagram illustrating a further example of a game controller; Figure 99 is a side view illustrating an example of a receptacle of a busbar connector M; Figure 100 (a) is a side view illustrating a busbar connector M; Figure 100 (b) is a top plan view of this plug; Figure 100 (c) is a front view of this plug; Figure 101 is a diagram of a connector provided on the side of the peripheral device (base device) of a bus bar cable M; Figure 102 (a) is a top view of an LM busbar connector receptacle; Figure 102 (b) is a front view of this plug; Figure 103 (a) is a top view of an LM busbar connector plug; and Figure 103 (b) is a front view of this plug.

BEST MODE FOR CARRYING OUT THE INVENTION (Brief description of the Composition) First, a summary of the composition of the system is described with reference to Figure 1 and Figure 2; Figure 1 is an illustrative diagram for describing a game device comprising a computer system; Figure 2 is a block diagram for describing a control system for this game device. The game device (host) 1 comprises: a CPU 1a for executing game programs, and the like; a ROM 1b for storing control programs, data, OS, and the like, for the game device; a CB-ROM device 1c for storing game and data application programs; a busbar controller 1d for controlling the data transfer between the CPU 1a and other sections; a RAM 1e for storing programs and data for the CPU 1a, which is used in the data processing; a pattern processor 1f for generating image signals from drawing data; a sound processor 1 for forming sound signals of sound data; a peripheral interface 1h for retransmitting the data transfer between the CPU 1a and the external peripheral devices; and similar. A portion of RAM 1e is used as a working RAM for peripheral data processing, thus enabling a so-called MA operation. An image signal and a sound signal are supplied to a monitor 4 (for example, a Television monitor) and video and sound images are taken. The peripheral devices comprise basic peripheral devices 2 and peripheral expansion devices 3. The basic peripheral devices 2 are connected to the peripheral interface 1h through a connector 1i, and the peripheral expansion devices 3 are connected to the basic peripheral devices. 2. The basic peripheral devices 2 and the peripheral expansion devices 3 are electrically (or through a logical structure) connected to the host in parallel. The basic peripheral devices 2 are, for example, game controllers, and the peripheral expansion devices 3 are, for example, sound input devices, sound output devices, light beam gun modules, vibration devices, memory devices, or similar. Here, in the first mode of implementation (first interface standard) described below, the peripheral devices are investigated in terms of the function they perform, and are divided as a function of device U and function of device L. This classification represents the fact that, in addition to the cases where an individual peripheral device forms an individual function, there are also cases where a plurality of functions are formed through an individual peripheral device, and cases where an individual function is presented through a plurality of peripheral devices. On the other hand, in the second implementation mode (second interface standard) described below, the peripheral devices are divided into basic peripheral devices and peripheral expansion devices according to the connection relationships between the devices. The modes for implementing the present invention are broadly classified into a first mode of implementation and a second mode of implementation.

(First implementation mode) Initially, the meaning of the terminology used in the first standard of The structure according to the present invention is described with reference to the drawings. -First of all, the data obtained by expanding the data in a series in time is called "serial data". A signal line, which exchanges data in the form of serial data, is referred to as a "serial bus". A bus in series connecting a game device and peripheral devices through the interface standard according to the present invention is called a bus bar M (busbar-M). The registration system identification number initially distributed to the device function of each peripheral device is referred to as the "device identification". A plurality of types, for example, 256 types of device identification can be prepared. It is also possible to have a plurality of the same device numbers in an individual port. The section by which a peripheral device can be connected to the peripheral controller of the game device through the bus bar M is referred to as a "port". The collector bar M allows the active connection of a plurality of ports.

For example, it is possible to support 16 ports, but this mode of implementation refers to an example where four ports are supported (port A, port B, port C, port D). As shown in Figure 3, the game device is referred to as the "host", and a function of a peripheral device connected thereto is referred to as a "device function". Since the "device function" indicates a function of a device, instead of the device itself (product), in addition to the cases where an individual function is performed by an individual device, it is also possible to divide the function of an individual device in a plurality of functions, each of which is taken as a device function. In the busbar M, there is a host device, which is connected to the functions of the device in a tree configuration. Each device function appears as it is believed to be present in the same busbar M. A plurality of device functions, for example, 14 device functions, can be connected to an individual port. The device functions allow the peripheral devices of the game device to function as, for example, a game controller, game palette, game lever, keyboard, imitation control device, imitation gun, engraving device, sound, and the like. As shown in Figure 4, the functions of the device are divided into two types: "upper device function (U)" and "lower device function (L)". The functions of the U device can be connected to the host. The functions of device U have the ability to control the functions of device L. The functions of device L are based on the premise that they are connected, (or can be connected) to a device function U. A busbar M, which links a device function L to a device function U is referred to as an "LM bus". Unless at least one U device function is provided on a port, that port can not be used. In principle, the gaming device controllers form functions of device U, and the expansion devices (connected peripherals) form functions of device L. The bus bar M can be connected, for example, to a maximum of 14 device functions L Furthermore, it is possible to connect a function of device U to a function of device U. In this case, the function of device U connected becomes a function of device L. It is unnecessary for device functions U and device functions L be physically separated, and it is possible for an additional device function logically separated within a device function U to form a device function L. For example, within the control device-IC function (eg, microcomputer or microcontroller) of the peripheral device , the digital control sections and the analog control sections can be set through the function as device functions U and device functions L, respectively, and when an analogous control section, mainly as a function of device L, is not you are using, it is possible to disable that section.

As shown in Figure 5, the numbers are distributed to each device function in order from port A, so that any of the plurality of device functions can be accessed directly by the host at each port of the host. The identification number (or symbol) to have distributed access to each device function is referred to as the "absolute position (AP)". In the bus bar M, a plurality of device functions is distributed to an individual port of the host. The relationship between the number of ports in the • busbar M and the number of APs is expressed by the following equation: (Maximum port number) x (Maximum number of APs distributed to a port) = constant. In the busbar M according to the mode of implementation, the "constant" is taken to represent a bit. In this case, (4 ports (maximum 16 ports)) x (APs for maximum number of ports) = 1 bit. - Of the 16 APs, an AP is reserved for the host port, so there is a maximum of 15 APs distributed to any individual port. Therefore, a maximum of 15 device functions can be used in a port. In addition, since a device function U is connected to a port, the maximum number of device functions L in any port will be 14. The number scale that can be used in a port is determined for each port through the Distributed APs device functions. For example, the AP is composed as follows: Bit 76543210 AP pppp ±±±± Here, "pppp" is the port number (port A = "0000", port B = "0001", port C = "0010", port D = "0011"), and "" is the serial number ("0000" (decimal of "0" - "1111" (decimal of "15")). Therefore the APs for a maximum of device functions It is 15, and the fifteen device functions can be set on a port, indicated in binary values, the AP value of the device function is "00000001" - "00001111" on port A, "00010001" - "00011111" in port B, "00100001" - "00101111" in port C, and "00110001" - "001111111" in port D. Indicated in decimal values, the previous values are 1- 15, 17-31, 33-47 , 49-63 and in hexadecimal values # 01- # 0F, # 11- # 1 F, # 21- # 2F, and # 31- # 3F. The AP of each host port seen from the device function is always the smallest AP value usable on that port, and in port A, it is # 00, in port B, it is # 10 (16), in port C, is # 20 (32), and port D, is # 30 (48). The device function and the host can identify the port to which it is connected through the first four bits of the AP. Access to a device function specifies a device function which is accessed by this AP. Since the designation of an AP distributed to each device function is at the same time the designation of a device function, the host can access each device function of the peripheral device directly. Therefore, as shown in Figure 6, viewed from the host, the host seems to be connected to each device function directly. In other words, each device seems to be connected to the same busbar. The exchange of data between the host and the device function is not conducted through conventional single-path communications, but rather using certain specific instructions, so that the appropriate time and place data can be transmitted and received. These instructions are referred to as "commands". The command data is called a "parameter". A cycle of transmission data is constituted by a frame "for example, 256 bits" comprising a command + parameter, as shown in Figure 7. The parameter may include AP data, data size, and data, or data that will be omitted. In principle, the host gives access to a device function by issuing a command. When the device function has prepared the corresponding data, issue a command to the host and send the data. In the bus bar M, a maximum of 254 commands, for example, can be prepared, and a maximum of 253 bits of data can be transmitted. A location for connecting an expansion device to expand the functions of the peripheral device, such as a game controller operating as a game operation input device, is termed as an "expansion receptacle". In principle, the L devices are connected to expansion receptacles.

A standard game controller may comprise two expansion receptacles, for example. The busbar M can be provided with an equal number of expansion receptacles to the number of device functions L, for example, 14 in the case of this mode of implementation. A circuit that converts certain data to serial data for the bus M, so that it can communicate through the busbar M, is called a "M / F bus bar machine M" (MIÉ). The standard M busbar devices all comprise MIEs of this type. The host incorporates a guest WED, the U device functions, a UI of device function U, and the functions of device L, a WED of device function L. As shown in Figure 8, in order that the host has access to a device function, it is always necessary to operate through software (busbar controller M), which exercises general control over device functions. The device functions are controlled and managed by the busbar controller M. This busbar controller M handles the identification of device (function identification number), AP (absolute position), and port, etc., and controls and manages the reception and transmission of commands, data format and the like. The commands can be increased by improving (updating) and increasing the busbar controller M. In the busbar M, all the device functions are forced to have information particular to itself (inherent information) recorded according to a prescribed format. This device function information is called "device status". The device status records the product name, device identification, license, model number, destination, LM busbar number, and the like, such as handling data, and the current consumption and maximum current consumption, etc., as electrical data (hardware information). The device status is managed and used by the busbar controller M and the application program interface (API); for example, it allows the name of the product and the connection capacity of a peripheral device to be identified, and allows the current for all ports to be controlled, based on the maximum current consumption, and the like. Figure 9 presents an approximate illustration of the proposed scope of the current standard. The application software performed on the host leads to the communication of data with the device functions on the peripheral devices through the software called API, or directly giving instructions to the busbar controller M. The commands formed by the busbar controller M in accordance with the instructions are supplied through the host MIÉ, cable, MIÉ peripheral device and MIÉ controller to the control software, which forms the core device functions of the peripheral device. This control software sends a response corresponding to the command in question to the application software performed on the host, through the MIÉ controller, the peripheral device MIÉ, the cable, the host MIÉ, and the busbar controller M. It is possible to provide a plurality of device functions in a peripheral device, and in this case, it is possible for each device function to share the use of a MIÉ. Here, MIEs and connection cables, etc., represent physical levels and the busbar controller M and the MIÉ controller represent logic levels. 'Next, the data transmission on the busbar M will be described.

? In the busbar M, the data transmission is carried out through a synchronized serial system. The connection cables comprise a total of four lines: a pair of power line (Vcc, GND), and a pair of data lines (SDCKA, SDCKB: two-way). If necessary, a protective cable is added to protect the connecting cable in order to avoid noise. The transmission and reception of data uses a dual-media system of two-way communications, which is set at an appropriate data transfer rate, for example, 2 Mbps. The principles of data transmission will now be described with reference to Figure 10. The data is transmitted through a serial data clock (SDCK) A and a serial data clock (SDCK) B, which propagate a data line. When data is transmitted, the serial data clocks A and B comprise a clock component and alternately form a negative edge (falling edge), as shown in Figure 10. In other words, as shown in the section on data pattern shown in Figure 11, the data bits are inserted between each pulse of the transmit clock pulse sequence, and the serial data clocks A and B are offset relative to each other for an appropriate amount on the axis of time (a time offset by which the pulse edge of a signal is placed in the data section of the other signal). On the receiving side, the data section of a signal is closed according to the negative edge time of the waveform of the other signal, and this data section is read to produce data (reproduction data). The data is transferred starting from the most important bit (MSB), for example. A circuit for performing data transmission in this way can be constructed relatively and simply. In addition, the data closing time can also be based on the positive edge (edge of increase) of the signal. According to this system, it is possible to reduce the transmission frequency in a data transmission path, compared with a busbar link system l2ODS. For example, in order to transmit at a data transfer rate of 10 Mbit s using a busbar I2 or DS link system, it is necessary to operate the data transfer medium at 10 MHz. However, using the system of the present, since 10 Mbits of data are transmitted by dividing them between two data lines that carry 5 Mbits each, theoretically, it is possible to obtain a data transfer rate of 10 Mbit / s using a data transfer clock of 5. MHz in the data lines. Furthermore, since the pulse width is enlarged by the insertion of data between the clock pulses, in the corresponding sections, the transmission frequency drops by an equivalent amount. Since a lower transmission speed is satisfactory, the circuit design is simplified. Figure 11 and Figure 12 show examples of signal transmission formats. A transmission format comprises: a start pattern, a data pattern and an end pattern, and if necessary, CRC bits (Cyclic Redundancy Check) are added. Figure 11 shows a standard transmission format. Data transmission is conducted in frame units (smallest unit). The composition of a frame in the standard format begins with a start pattern (START), which indicates the start of data transmission, and then comprises a data pattern with a length of 256 bits (DATA), and a pattern of end (FIN). The "D" symbols shown in the data pattern represent sections that carry the bit information "0" and "1" of the data. Figure 12 shows an example of a format that incorporates the CRC option, where an error correction function is added to the standard data format. A cyclic redundancy check (CRC), for example, can be used as an error correction method. In data transmission using a CRC option, a CRC code pattern is added after the data that is the CRC object, as illustrated in the data pattern, of Figure 12. The portions outside the data pattern in the transmission format described above form the information patterns that carry specific information. The information patterns are defined by the number of signal pulses (transmission clocks) for which either the SDCKA or SDCKB lines propagate the other signal line while in an "L" level state. The information patterns may include, for example, synchronization patterns, data line occupation permission patterns, restart patterns, and the like. Synchronization patterns include: start patterns as illustrated in Figure 13 (a), end patterns as illustrated in Figure 13 (b), and start patterns with the CRC option as illustrated in Figure 14. A start pattern is a synchronization pattern transmitted before the aforementioned data pattern. If the MIÉ on the receiver side detects four negative edges of the SDCKB data line, while the SDCKA data line is at the "L" level, the subsequent pattern is read as a data pattern and regulated, use a memory . The end pattern indicates the end of the data pattern. If the MIÉ on the receiver side detects two negative edges of the SDCKA data line, while the SDCKB data line is at the "L" level, then this confirms that the data pattern has ended and indicates the appropriate term of the process . The start pattern with the CRC option represents the START pattern when a CRC option is added. If the MIÉ on the receiver side detects six negative edges of the SDCKB line while the SDCKA data line is at the "L" level, then it is identified as data transmission comprising a CRC option. The error inspection is conducted with respect to the data section, using the 16 bits before the FIN pattern as CRC data. Figure 15 shows an example of the data line occupation permission pattern, whereby the host allows the receiver side to occupy one of the data lines. In an occupation permission pattern in relation to the occupation of SDCKB, of the data line, the SDCKB line has 8 negative edges, while SDCKA is at the "L" level. When the MIÉ on the receiver side detects the occupation permit pattern SDCKB, then it is possible to occupy SDCKB, while SDCKA is in "L", starting from the subsequent negative edge of SDCKA. The occupancy of SDCKB is canceled by the next positive edge of SDCKA. For example, it is possible to send output data from a light gun used in a shooting game device to the game device by occupying the data line SDCKB. The data is transferred using only the SDCKB data line, and the SDCKA data line indicates the occupation time (period). Figure 16 shows a restart pattern. The restart pattern comprises 14 negative edges of the SDCKB data line, while the SDCKA data line is at the "L" level. When the MIÉ on the receiver side detects the restart pattern, it identifies this as a request to restart the host. The device then initializes the WATCH and delete the AP. No data other than this is initialized. Next, the transmission protocol in the data communications between the host and the device is described with reference to Figure 17. First, in principle, the host has the right of priority to transmit commands. Communications are conducted in a way by which a corresponding device function responds to a command from the host. Therefore, all transmission protocols are initiated with the transmission of a command from the host. Figure 18 (a) presents an illustration of this. The data is transmitted from the host to the device function when the need arises. Therefore, in the bar M collector and the LM busbar, the intermittent data communication between the host host and a plurality of device functions is carried out. If the data to be transmitted exceeds a prescribed length of the transmission frame, then the data is divided into a plurality of sections as shown in Figure 18 (b), and each of the divided data sections is transmitted to through a plurality of transmission frames (see Figure 70 described below). • The host application program gives access to the busbar controller in order to obtain data from the device function of a peripheral device • particular. The controller creates an AP, forming an address, and a command, and the MIÉ sends frame data carrying the AP and the command to the busbar M. In a normal state, the device functions connected to the busbar are at rest waiting for a command from the host. The MIÉ in the peripheral device receives the frame data, and transfers the command to the control program of the device function through the MIÉ controller. If the control program detects its own AP, it sends a response to the relevant command through the MIÉ controller. The MIÉ creates frame data containing the return command and the host AP, and outputs to the busbar. The host receives this frame data, thus obtaining a response to the transmitted command. The device function returns to a rest command function. In this way, the host can obtain required information from a device function. Next, a summary of the processing implemented in the device functions will be described with reference to Figure 19. When the power line is connected to the peripheral device and the power is supplied, the device function executes an initialization process to set the initial hardware values, and the like. Then, an AP fixation process is implemented to set the AP value of the device function. In the AP fixation process, the connected device functions are identified and the APs are distributed to the device functions, etc. By giving the device function an AP, it is possible to conduct communications between the host and the device function using the AP, thus performing a normal operating state. • In a normal operating state, when a device function receives a restart command from the host, the AP is restarted (software restart). • When a collector band reset command is restarted, all device functions connected to the collector band on the corresponding port are initialized, and the APs are restarted (hardware reset). The host can also order an operation to be prohibited or suspended, transmitting a command to each device function. Now it will be described with reference to Figure 20, the process of fixing AP in the device functions. (1) After completing the initialization, the host transmits a Device Request in sequence starting from port A, to confirm if any of the device functions are connected to the ports. The Device Request is a command that requires any device function that has not been distributed an AP to send its Device Status, which gives the information inherent to the device. It is transmitted in sequence starting from port A and ending at port D. (2) After completion of the initialization, a device function U disconnects the busbar LM from the busbar M and waits for a request from the host device. If it receives a Device Request from the host, it sends a Device Status to the host in response. At this stage, there is only one device function on a port receiving a device request at any time. There is no response from device functions that have not been distributed to an AP. (3) When the host receives a Device Status from a device function, it determines the connection relationship and device attributes based on this data, and distributes an AP to the device function and transmits an assignment of the device. AP carrying the distributed AP value to the device function. The APs are consecutively distributed within a fixed scale for each port, and the host detects the relationship between the AP and the device function. If the device function attributes are not those expected by the application software (external scale of use), then the operation of that device function can be terminated by sending an Annihilate Device command. If the device function is a device function U, then the device functions L connected to it are also terminated, thus allowing the entire port to be disabled. (4) The device function reads in the host's AP assignment, stores its distributed AP, and then transmits a Device Response to the host as a response from the device function. Then, the host gives access to the device function using the ID and AP device. (5) Since the host detects the number of device function LM busbars currently set in the device state, and there is an LM busbar, the host will transmit the LM busbar connection so that one of the LM busbars connects to a device function. If there is no LM busbar connection, then processing is implemented in (10) below. (6) When a device function U receives a busbar connection LM, it connects an LM busbar to the busbar M. It then sends a Device Response to the host. (7) When the host receives a Device Response, it transmits a Device Request. In this case, since the U device function has already been distributed to an AP, it does not respond. (8) When a device function L receives a Device Request from the host, it sends a Device Status to the host in response. (9) Processing from (3) to (8) is repeated until all the LM bus bars are connected (the APs are distributed to all functions and devices). (10) The host sends a Function Start in order to start the operation of each device function. (11) When the device function receives Function Start, it transfers from the AP setting operation to normal operation. After transferring, the device function sends a Device Response to the host. (12) After receiving the Device Response, the host sends a Function Start to the next AP. (13) Each device function is activated in frequency by repeating the processing in (11) and (12), until the device function at the end of AP transmits a device response, so that the AP fixation process is completed . (14) The device functions having transferred to normal operation, the host proceeds with fixing AP for the next port. In this way, an AP is set for each function of the device connected to a particular port.

The involved processing will now be described when a cable is connected or disconnected while the host is operating (active line on / off). (1) The host transmits a device request to each port at prescribed intervals. Ports that are not in use can be excluded from the access operation. (2) If a device status is transmitted from a port which has not been previously connected, the host recognizes that a device function has been connected. After recognizing this, it outputs a reset pattern to that port, and clears the APs of all device functions. Then an AP fixation process is performed to renew the APs and redesign the connection relationships. (3) If the host transmits a command to a device function and there is no response of the device function, the host recognizes that device function has been disconnected. If a device function is disconnected, the host clears the APs and redesigns the connection relationships. Now we will describe the data transmission and reception processing during normal operation (1) Right of priority of transmission of command. A command is always transmitted initially by the host, and the device functions respond to this command. If a device function initially transmits a command to the host, it is not recognized. The host does not retransmit command unless there is a request from the device function side. (2) Data format. Transmission and reception data are constituted by commands and parameters (AP data, data size, data) When a signal is actually transmitted along a data line, the MIÉ adds a start pattern and an end pattern to it, before the command and at the end of the parameters, respectively. In this way, an individual frame is constructed and transmitted in the order: "start pattern" + "command pattern" + "AP data" + "data size" + "data" + "end pattern". -The frame is analyzed by the MIÉ on the reception side, thus confirming the -pattern of the start and the end pattern. The details of the commands and parameters are described later. (3) Host The MIÉ used by the host is governed by the busbar controller M. The reading of the function data of the device is not performed automatically for the MIÉ, but rather it is implemented by the respective software through the busbar controller M. The respective software here must mean the software of a higher level compared to the busbar controller M, for example, software bookstore or game software. In an individual access operation, it is possible to communicate with a device function having the specific AP. In order to read data from a plurality of device functions in 1 INT, the corresponding number of device functions is accessed. 1 INT (interrupt) is a unit of time of television screen writing, mainly about 1/60 seconds. Port connection verification transmits a device request to unconnected ports, and if a response exists, that port is set to "connected". When it is not transmitted, a port is always set in the input (reception) mode. The type of command that will be used differs according to the device's function of time and circumstances, so that it is set according to the device's specification. (4) Device functions MIEs for peripheral devices are controlled through a MIÉ controller through the CPU, or the like, which executes the device function programs. The device functions maintain a receiving state until a command is transmitted by the host. The device functions then generate their own data necessary for communications. In addition, asynchronously to host access, the functions of the device create data that will be output as the function of that particular device (e.g., operation input device such as a control paddle or game lever). If there is a request from the host, the data is transmitted within a prescribed period. The host transmits the same command to all device functions connected to the same port. The device functions analyze the received command and parameters, and send a command only if it matches its own AP. If it does not match your own AP, you should not respond to the host. The type of command used differs according to the device function, and the time and circumstances, so that the details thereof are determined according to the device function specification. (5) Prohibited operations. Direct access of a device function to another device function connected to the same port is prohibited. The communication between device functions must be conducted through the host. further, commands that can only be issued by the host should not be used. Now we will describe the exceptional processing. Exceptional processing is special processing prepared for devices where the transmission and reception of data can not be controlled by command. An example of such a device is a light gun used in a shooting game. (1) If the host recognizes that the function of the device has a light gun identification device, then it switches the collector bar M from the normal mode to the occupancy mode SDCKB, the switching mode is not possible from the function side of device. Prior to switching, the host transmits a mode change, and then confirms that a light gun is switched on, switches the busbar mode M to the occupation pattern SDCKB. After entering occupancy mode SDCKB, all devices in that port assume the occupancy mode SDCKB, and device functions other than those operating in occupancy mode SDCKB do not receive commands. For example, if a light gun with a memory card and a vibration unit is connected to port A, the device function operating in the occupancy mode SDCKB is only the light gun. During the occupation mode, only the light gun is controlled by the host, and the other device functions, mainly the memory card and the vibration unit, do not operate (they can not be controlled by the host). (2) Upon returning from the SDCKB occupation mode, the host performs the cancellation procedure. When the SDCKB occupation mode is terminated, the system immediately returns to normal mode. (3) In the case of a light gun, the time to write on the screen at 1 INT omitting the vertical white period, in other words, the period to draw on the • TV screen, forms the occupation mode SDCKB. When the period of drawing on the screen is terminated and the target period is initiated, the system is switched directly to normal mode, and data transmission and data reception is conducted for device functions on other ports. (4) In order to obtain a light gun function, a section containing a photoreceptor element is taken, as a device function, and taken in sections containing trigger and direction keys, analog keys, and the like, such as an additional device function. In this way, it is possible to eliminate conventional problems, such as by disabling the arrow keys, when the light gun is used. In addition, since the light gun forms a single device function unit, it can be connected to other expansion devices. Through this, it is possible to provide game applications having new functions. Now we will describe examples of commands. The commands can be broadly divided into control commands and error commands. The control commands include the basic commands of: Device Request, State Request, All States Request, AP Assignment, Connect LM Bus Bar, Function Start, Host Data Transmission, Data Request, All Data Requests, Change of Mode, Sleep Device, Device Request, Annihilate Device, Device Status, Device Response, Device Data Transmission, and the like. In addition, there are expansion commands which do not belong to these basic commands. The expansion commands differ according to the device function and busbar controller M. The Device Request is a host command requesting a device function that does not have a distributed AP to send a device status. The Status Request is a command from the host requesting a device function specified by an AP and sending a device status (this data is inherent device information (Fixed Device Status)). All States Request is a command from the host requesting all device states (mainly, both the Fixed Device Status and the Free Device Status) of a device function specified by an AP. The device function sends the Fixed Device Status followed by the Free Device Status through the device data transmission. AP Assignment is a command by which the host distributes an AP to a device function. It can only be executed during the AP fixation process. If the device function is in normal operation, it does not process the command but sends a Command Rejection. Connect Busbar LM is a command from the host asking for a device function to connect an LM busbar to the busbar M. After receiving the Connect Busbar LM command, the device functions connect the LM busbar that belongs to it, a bus for each function. If a device function is in normal operation, it does not process the command, but sends a reject • of command. Function Start is a host command that causes a device function specified by your AP to start normal operation. If the device function receives this command and starts normal operation, it sends a Device Response. If no initialization is presented. If the function of the device is in normal operation, it does not process the command but sends a Command Rejection. Host Data Transmission is a command by which the host transmits data to a device function. The data contents differ depending on the device function. The details of this data are determined by the device function specification. If the data size is 0, then the device function does not receive and sends a Command Rejection. During AP fixation also, the device function does not receive and sends a Command Rejection. Data Request is a command from the host asking for a function of the * device to transmit specific data. A plurality of request data number may be specified in the data region. If the data size is OOh, then the device function does not process the command and sends a Command Rejection. During AP fixation also, the device function does not process the command and sends a command rejection. All Data Request is a command from the host requesting a device function to transmit all of its data. During the AP fixation process, the device function does not receive the command and sends a Command Rejection. Change Mode is a command through which the host switches the mode of the M port bus. When switching to the SDCKB application mode after the Mode Change command has been issued, the Device Response is confirmed and the The specified port is switched to the occupation mode SDCKB. If the function of the device does not correspond to the operations in the occupancy mode SDCKB, then it does not process the mode change and sends a Command Rejection. During the AP fixation process also, the device function does not process the Mode Change, but sends a Command Rejection. Sleep Device is a command through which the host temporarily suspends a specified device. When a device function has been suspended, it sends a Device Response and then can only receive the Function Start. During the AP fix process, the device function does not process Sleep Device, but sends a Command Reject. Restart Device is a command through which the host applies a software restart to a specific function to reinitialise it. The software restart is not a re-fix (initialization) that uses hardware functions such as restart terminals IC, but for example, the initialization of internal RAMs or registers in programs (software). Since the software restart allows the selection of portions that will be reset in the program, it is possible to retain portions, such as the fix status of the IC terminal, for which the initialization is not desired. The AP values that have already been distributed are not initialized. After initialization, the device function sends a Device Response and starts normal operation. During AP fixation, the Device Function does not process the Restart Device, but rather sends a Reject of Command. Annihilate device is a command by which the host prohibits the operation of a device function. The device function can only process this command before Assign AP in the AP fix sequence. The device function waits at a standby current consumption, and can not receive any commands. In order to activate the device function, the hardware must be rebooted or the power turned off.

• The hardware restart is conducted by restarting (initializing) using hardware functions such as restart IC terminals. It is also possible to drive a . equal initialization processing in the program. This processing is equal to the energy for the restart in the power supply that performs IC initialization at the same time. In contrast to software initialization, no selection of the portion that will be initialized is possible. If the device function is in normal operation, it will not process this command, but will send a Command Rejection. To suspend a device function temporarily during normal operation, the Sleep Device command is used. - Device Status is a command through which a device function sends a Fixed Device Status to the host. This Status of Fixed Device is described below. Device Response has a wide scale of use as a device function response transmitted by a device function. The AP in the data contents indicates the AP itself of the device function, thus specifying the source of the Device Response. Transmit Device Data is a command by which a device function transmits data according to a request from the host. The data contents differ depending on the device function. If the data size is OOh (h indicates a hexadecimal notification), the host will not process the command, but will send a Command Rejection. Depending on the circumstances, a command such as a retransmission, Device Status or similar can be issued. Now the error commands will be described. The error commands include basic commands, such as Command Rejection, Unknown Command, Transmit again, LM Collection Band Error, Device Error and the like. In addition to this, there are also expansion commands, which are intrinsic to the device function and to the M-band controller. The intrinsic commands herein do not mean normal commands maintained by the controller but commands prepared for specific device functions. ^ Command Rejection is a command by which the host or device function refuses to receive data corresponding to an input command. This command is also transmitted if a command that is not compatible with the host or the function operation is received. This command prohibits inappropriate access. Unknown command is a command that is transmitted from a device function to the host when the device function receives a command from the host that is not recognized. Transmit again is a command sent by the host or a device function asking that the same data be transmitted once again, when an error of some kind has been presented in this received data.

Collecting Bar Error LM is a device command to the host presenting the notification that an error has occurred in the LM bus. This command is sent to the host in cases when, for example, the LM bus connection is received from the host, but there is no LM bus to connect. Device Error is a command of a device function notifying the host that an error of some type has occurred in a device function and that the device function is in the process of reinitialization. The Device Status information mentioned above will now be described. Device Status stores data directly so that it can not be written or deleted. For example, it is not allowed to calculate a certain value to give a value of -state or text. The Device State comprises: Fixed Device Status and Free Device Status. The Fixed Device Status refers to a permanent device status, which is an essential description of the device, for example, a total format of 108 bytes.

Unless all items are described, the operation and connection of the device can not be guaranteed. -? I Free Device Status refers to a device state that can be freely used depending on the individual device function. For example, the capacity must be 148 bytes or less. The Fixed Device Status comprises the following items: (1) Device Identification This describes the identification and attributes the device function. By pre-registering and assigning an identification to each device function, the host is able to identify which type of device function is connected by reading its identification. Therefore, those used by the busbar M are registered by product in advance for those that have a busbar license M. (2) Maximum data size This describes the maximum data output size by the device function. (3) Number of LM Busbars This describes the number of LM busbars carried by the device function. (4) Product name - The product name is described in English or romaji using ASCII code. -. 'This may be different from the real business name. The name of the product is also subject to previous registration. (5) Destination code This describes the region where the product is sold. For example, North America, Europe, Japan, etc. This code makes it possible to determine the compatibility between peripheral devices and game applications for particular target regions. (6) License -This shows the product license in English or romaji using ASCII code. (7) Current consumption at rest This describes the current consumed during the temporary suspension, in units of 0.1 mA. (8) Maximum current consumption This describes the maximum current consumed in units of 0.1 mA. On the other hand, the Free Device State refers to information areas, which can be freely set by product planners, developers, designers, programmers or similar. The host can obtain this information from a device function through the request command of all the devices. When this region of information is used in application software and the like, it is necessary to ensure the compatibility of data streams, etc., from before. The host's MIÉ must be specifically named as a peripheral controller. Figure 21 shows an example of a block circuit diagram for a peripheral controller (MIÉ) provided in the host. . In this diagram, a clock divider 51 creates a clock to supply each processing block of the controller from a system clock, and by varying the frequency ratio of the clock supplied, it is possible to alter the transmission (transfer) speed and Similar. The entry register 52 is a 32-bit register in which the instructions sent from the application, etc. towards the peripheral devices are written through the main bus. The contents written for this record are transferred to a port controller 57 and frame controller 58. The write buffer 53 is a RAM of 256 bytes in which data is written for transfer. The interrupt controller 54 is a controller for controlling interruptions due to reception transmission or errors of different types.

Status register 55 is a 32-bit register indicating the status of the main controller. The read buffer 56 is a 256-byte RAM for maintaining received data. The port controller 57 is a controller for controlling ports involved in the transmission and reception of data. Controlling a three-state buffer 68 of a transmission port selected by a command, the outputs SDCKA and SDCKB of a first and second selector 64 and 65 are directed to the selected port. A receiving port is selected by controlling a third and fourth selector 66 and 67. The frame controller 58 is a controller for controlling the frame composition in terms of output patterns, data length, and the like. The frame encoder 59 is controlled by the frame controller 58 and outputs patterns of information. The alternate shift register 60 is controlled by the frame controller, and is a register for converting parallel data (P / S) in the write buffer to serial data, and in turn outputting data and a clock to SDCKA SDCKB . A CRC calculation section is provided within the alternate offset register, and CRC processing is applied to the data according to the commands of the frame controller. ^ The first selector 64 is controlled through the frame controller 58, and outputs SDCKA by selecting the outputs of the frame encoder 59 or the output of the alternating shift register 60. The second selector 65 is controlled through a frame controller 58 , and output to SDCKB by selecting the output of the alternating offset register 60 or the output of the frame encoder 59. The third selector 66 selects a reception port in accordance with the commands of the port controller 57, and supplies received SDCKA through from a buffer memory amplifier 69 to a frame decoder 61 and an alternate shift register 62. The fourth selector 67 selects a reception port in accordance with the commands of the port controller 57, and supplies received SDCKB through an amplifier buffer 69 to a frame decoder 61 and alternating shift register 62. The frame decoder 61 analyzes the composition of the frames received, reflects this in the State Record 55 and controls the alternate shift register 62.: The alternate shift register 62 is controlled by the frame decoder 61, and the (S / P) register for converting data In series received to parallel data, the alternate shift register 62 also comprises a CRC calculation circuit for performing the received error inspection. The closing signal controller HV is activated by the frame controller 58. For example, when the frame controller 58 has transmitted an occupancy permission pattern SDCKB in which the frame decoder is deactivated and the closing signal controller HV is activated. When the closing signal controller HV receives an SDCKB after an occupancy permission pattern SDCKB has been transmitted, a closing signal is supplied to an HV counter (omitted from the drawing). The HV counter comprises a horizontal position counter and a vertical position counter, whose output values correspond to a position on the screen. For example, in a shooting game, when the trigger of a gun directed at a television screen is pulled, SDCKB is taken out by the gun. This SDCKB is used to identify the target position (shot) of the gun on the screen through the HV counter. Figure 22 is a circuit diagram illustrating the operational principles of the frame encoder 59. In this diagram, 591 is a vasculator, 592 is a counter 593 is a comparator and 594 is a logic gate. Figure 23 is a time control diagram for describing frame operation 59. When a written pulse is supplied to frame encoder 59, this circuit assumes an active state. The SDCKA at the Q output in the vasculator 591 is set at the "L" level through the elevation edge of the write pulse. SDCKA forms layers to counter 592, which initiates a CLK clock account supplied thereto. Counter 592 advances a CNT OUT account value through "0", "1", "2", ... "7", "8". This count value is supplied to the comparison input A of the comparator 593. An output pattern setting value n is supplied to the comparison reference input B of the comparator 593. For example, if a "start pattern" is generated. "then the frame encoder 59 decodes this command and supplies" 9"as a fixed value n. If the two inputs match, the comparator 593 outputs CMP OUT of the output terminal EQ, which is supplied to pre-establish the terminal / PR of the vasculator 591. In this way, the SDCKA at the Q output of the vasculator 591 is fixed at level "H". SDCKB is obtained by synthesizing SDCKA and a CLKB signal having half the frequency of the clock signal CLK in gate OR 594. In this way, the output pattern setting values corresponding to a start pattern, pattern of restart and end pattern, etc. And when a write pulse is entered the SDCKA is set at the "L" level, and for SDCKB a pattern signal having a prescribed number of falling edges can be obtained. Figure 24 is a circuit diagram illustrating the operational principles of the alternating shift register 60. In this diagram, 601 is a shift register for converting data parallel to serial data.; 602 is a double input selector; 603 is a shift register for converting data parallel to serial data; and 604 is a double input selector. Figure 25 is a timing control diagram describing the operation of the alternating shift register 60. A plurality of bits with even number D6, D4, D2, DO for data transmission are respectively provided to a plurality of input terminals D of the shift register 601, and the data is shifted through a shift clock SHIFT CLKA having the time control illustrated in the diagram, and is supplied from the output terminal Q to the input terminal A of the selector 602 as serial data. A CLKA clock as shown in the diagram is input to the terminal B of the selector 602. The selector 602 selects the serial data of the output terminal Q according to the level "H" of the SHIFT CLKA scroll clock, and selects the CLKA watch according to the "L" level of CHIFT CLKA. Therefore, a signal SDCKA, where the data D6, D4, D2, DO are superimposed on the clock CLKA at pre-written intervals, is obtained at the output terminal Y of the selector 602. Similarly, a plurality of bits of odd number D7, D5, D3, D1 for transmission are respectively supplied to a plurality of input terminals D of the shift register 603, and the data is shifted through a shift clock SHIFT CLKB having the time control illustrated in FIG. diagram and supplied from the output terminal to the input terminal A of the selector 604 as serial data. A CLKB clock as shown in the diagram is input to the input terminal B of the selector 604. The selector 604 selects the serial data of the output terminal Q according to the level "H" of the SHIFT CLKB scroll clock , and select the CLKB clock according to the "L" level of SHIFT CLKA. Therefore, an SDCKB signal, where the data D7, D5, D3, D1 are superimposed on the CLKB clock at prescribed intervals, is obtained at the Y output terminal of the selector 604. The sections "DO" - "D7" shown in the SDCKA and SDCKB signals have an "H" level or an "L" level depending on their data value. Figure 26 is a circuit diagram showing a compositional example of a frame decoder 61. In this diagram, 611 is a counter, 612 is a composite vasculator consisting of a plurality of vasculators, 613 is a counter, and 614 is a vasculator. compound consisting of a plurality of vasculators. Figure 27 is a time control diagram describing the operation of the frame decoder 61. Of the elements in the diagram, the counter 611 and the vasculator 612 operate in the detection of a start pattern. When SDCKA is at level "H", the counter operation is disabled. When SDCKA takes the "L" level, the counter operation is enabled, and the falling edges of SDCKB are counted. Counting the number of falling edges of SDCKB while SDCKA is at level "L", an account output is supplied to the vasculator. The output of the counter is supplied to the vasculator 611 at the elevation edge of SDCKA. As shown in Figure 27, if the number of fall edges of SDCKB is four during the period in which SDCKA is at the "L" level (Start Pattern, see Figure 13), vasculator 612 outputs the starting pattern vasculator. To detect the end pattern, the number of falling edges of SDCKA while SDCKB is at level "L" is counted through counter 613 and vasculator 614.

Through this elevation edge the SDCKB, the count output 613 is incorporated into the counter 613. As shown in Figure 27, when the falling edges of SDCKA are counted while SDCKB is at the "L" level, is vasculator 612 outputs the detection of the end pattern. When the number of falling edges of SDCKA during the period in which SDCKB is at level "L" is not specified, the vasculator 614 outputs a frame error detection. In the normal operation mode the data pattern and the end pattern with the falling edges of SDCKA follow the start pattern with four falling edges of SDCKB (Figure 11). Further, although not illustrated in FIG. 27, after starting reception, when the counter 611 detects six edges of SDCKB decay while SDCKA is at the "L" level, the vasculator 612 outputs the detection of a pattern of start with CRC (Figure 14). In the operation mode using CRC, the data pattern, the CRC data and the end pattern follow the CRC start pattern with six falling edges of SDCKB (Fig. 12). Further, if the counter 611 detects the falling edges of SDCKB eight times while SDCKA is at the "L" level, then the vasculator 612 outputs the occupancy permission detection SDCKB (Figure 15). When the pattern is detected, the operation mode is moved to the occupancy permit operation mode SDCKB. In the operating permit mode of operation SDCKB, the light gun can be used. The SDCKB operation mode is reset by the SDCKB occupation permission mode reset pattern (SDCKA occupation edge). If the counter 611 detects the falling edges of the SDCKB eleven times while the SDCKA is at the "L" level, the vasculator 612 outputs the detection of the restart pattern (Figure 16). The detection allows the restart operation. If the number of falling edges of SDCKB is not specified, the vasculator 612 outputs the frame error detection. The pattern detection outputs of vasculators 612 and 614 are maintained in state register 55. FIG. 28 shows a compositional example of alternate shift register 62. In this diagram, serial data SDCKB is supplied to the terminal of input data D of a shift register 621, and SDCKA is supplied to its shift clock input. The shift register 621 reads in the data sections of SDCKB successively at the falling edges of SDCKA, as illustrated in Figure 29. The data converted in series to parallel are arranged in the parallel output terminals D7, D5, D3 , D1 of the shift register 621 by four clock edges of SDCKA: Similarly, SDCKA of serial data shown in Figure 29 is supplied to the data input terminal D of the shift register 622 shown in Figure 28, and SDCKB It is supplied to your scroll clock input.

- The shift register 622 reads in the SDCKA data sections successively at the falling edges of SDCKB. The data converted serially to parallel are arranged at the parallel output terminals D6, D4, D2, DO of the shift register 622 by four clock edges of SDCKB. Figure 30 is an approximate general block diagram of a device -peripheral to be connected to a game device, generally referred to as a game controller, an input operation controller or an operation input device, etc. A game controller will be described below. It is possible to add (dock) more peripheral devices (L device functions) providing two expansion enclosures in the game controller. The game controller contains a single-chip microcontroller. It also comprises 11 switches to generate the digital output, and analog keys to generate a four-axis output. The output of these switches, etc., is processed through the microcontroller and the output to a host via MIÉ of an M bus. Figure 31 is a block diagram giving an approximate illustration of the composition of a MIÉ in the device function side, where the functions of a peripheral device are taken as the device functions. In this diagram, the game controller is connected to a host (omitted from the drawing) through a busbar M. The game controller comprises a device function U connected to the host through the busbar M, and two device functions L connected to the device function U through LM busbars. Figure 32 is a block circuit diagram showing a bus switch section (selector) of Figure 31. Two busbars M are presented branching off from the device function U, and these are referred to as busbar LM 1 and busbar LM 2, respectively. The interruption operation for connecting and disconnecting the LM busbars and the busbar M is done through a MIÉ selector in the device function U. FIG. 33 is an approximate block diagram of a hardware section of a function of device U. The transmission processing section, the receptacle control section, the CPU section and the I / O section are constituted by a single-chip microcontroller. The transmission processing block forms an interface with the host. The CPU section controls the signal processing in the peripheral device, such as a game controller, or the like. Section I / O is an external input interface for digital buttons, analog keys or similar. The receptacle control section is used to control expansion receptacles. In this example, hardware expansion receptacles (two slots) are prepared for the two functions of device L. Figure 34 is an approximate block diagram of a device L function. A transmission processing section, a CPU section , and a support function are constituted by an individual chip microcomputer. The transmission processing section forms an interface with the device function U (MIÉ for the device function L). The CPU section performs the processing in relation to the processing of device L. The support function block performs the function of the device function L, for example, a circuit for performing the trigger function of a light gun, function of memory or vibration function, etc. Next, referring to Figures 33 and 34, the operation of the MIÉ on the device operation side will be described. In the initial state where the APs are not distributed, a three-state buffer is controlled by the receptacle controller shown in Figure 33, and SDCKA OUT and SDCKB OUT transmitted to the expansion receptacle 1 and expansion receptacle 2 are disabled . Here, the receptacle controller performs the functions of a busbar controller LM 1 and a busbar controller LM 2. With SDCKA OUT in a disabled state, when no device function L is connected to the expansion receptacle, SDCKA OUT assumes the level "L" due to the tensile strength connected to the output terminal of the three-state buffer. The receptacle controller can identify that no device function L is connected to the device function U by detecting the "L" level of this output terminal. On the other hand, a power supply is connected through a pull resistor to the input terminal SDCKA OUT of the hardware of the device function L, as illustrated in Figure 34. Therefore, if the hardware of the device function L is connected to the expansion receptacle, the SDCKA OUT terminal (three-state buffer in the disconnected state) will be raised to the "H" level by the relatively high resistance of the tensile strength shown in Figure 33 and the low resistance of said tensile strength. By detecting the "H" level of this output, the receptacle controller can identify that the hardware containing a device function L has been connected to the hardware comprising a function of device U. An AP is distributed to the device function U to through an allocation command AP of the host, and when a command is received to connect the busbar LM, the SDCKA OUT and SDCKB OUT in the expansion enclosure 1 assume a enabled state. In this way, the host commands are transmitted to the device function U and the device function L linked to the expansion enclosure 1. If the host distributes an AP to the device function L in the expansion enclosure 1 and transmits an command to connect busbar LM to device function U, device function U will set SDCKA OUT and SDCKB OUT in expansion receptacle 2 to a enabled state. After the process of distributing AP to the device function L in the expansion enclosure 2 is complete, the host commands are transmitted to the device function U and all the functions of the device L, in the same manner. The function of the device U and the functions of the device L are compared with the value AP contained in a command, determine if they have been selected and respond appropriately. Figures 35-39 are flow diagrams illustrating the control operations implemented by the MIÉ during transmission. A processing script is given from the host application through an API to the bus driver software. The bus controller translates these processing commands into instructions controlled by WEDNESDAY, and fixes them in the instruction record 52 of the MIÉ. The frame controller 58 determines whether the commands (instruction) set in the instruction register, instruct the signal output of the standard transmission format pattern (S12), the output of a format signal with the CRC option (S14), the output of an occupation pattern SDCKB (S16) or the output of a restart pattern (S18). If a standard transmission format pattern is to be outputted (S12; Si) then the frame controller 58 selects the output of the frame encoder 59 through the voters 64 and 65 and causes a start pattern to be output from the encoder of frame 59 (S21), according to the sequence shown in Figure 36. Next, it selects the output of the alternate offset register 60 through the voters 64 and 65, causes the transmission data to be written from the buffer of write 53 to the alternating shift register 60 (S22), and causes a data pattern to be ejected from the alternating shift register 60 (S23). The frame controller 58 confirms that the transmitted data comprises 256 bytes, for example (S24). If it does not satisfy the 256 bytes (S24, No), then the read processes of the write buffer (S22) and the output data (S23) are repeated. If the 256 bytes have been transmitted (S24; Si), then the output of the frame encoder 59 is selected by the voters 64 and 65, and the frame encoder 59 transmits an end pattern. In this way, the data is transmitted in a standard pattern. If the code is set in the instruction register 52, it gives output instructions of a signal of the CRC option format (S14; Si), then the frame controller 58 selects the output of the frame encoder 59 through the voters 64 and 65 and causes a start pattern with CRC to be output by the frame encoder 59 (S31), according to the sequence shown in FIG. 37. Then, the output of the alternate shift register 60 is selected by the voters 64 and 65, and the transmission data are read from the write buffer 53 in the alternating shift register 60 (S32). In addition, the frame controller 58 causes the CRC calculation section in the alternate shift register to perform CRC calculation on the read data (S33). Then it causes a data pattern to be taken out of the alternate offset register 60 (S34). The frame controller 58 confirms that the transmitted data comprises 256 bytes, for example (S35). If it does not satisfy the 256 bytes (S35; No), then the read processes of the write buffer (S32), the CRC calculation (S33) and the data output (S34) are repeated. If the 256 bytes have been sent (S35; Yes), then the frame driver 58 causes the alternate shift register 60 to transmit the CRC data after the data (S36). Then it selects the output of the frame encoder 59 through the switches 64 and 65, and causes the frame encoder 59 to transmit an end pattern (S37). In this way, the data is transmitted in a pattern that contains CRC. If the frame controller 58 identifies an output driver for an occupancy permission pattern SDCKB (S16; Si), then it selects the output of the frame encoder 59 through the switches 64 and 65 and causes the frame encoder 59 output to an occupancy permission pattern SDCKB (S41), according to the sequence shown in Figure 38. The buffer 68 is controlled through the port controller 57 and prohibits the output of SDCKB (S42). Then, frame encoder 59 outputs an occupancy permission pattern SDCKB, where SDCKA is set at level "L" (S43). Then, the HV 63 closing controller is enabled. The closing controller HV 63 checks the SDCKB line (S44). If there is a response from the device side (S44; Yes), then the HV 63 closing controller generates a closing output of the HV controller (S45). After generating a closing output (S45), or if there is no device-side response (S44; No), then this identifies whether the command to set the occupancy mode SDCKB is still present in the register 52 (S46). If still present (S46; No), then steps S44-S46 are repeated, and the closing outputs are successively generated according to the device side responses. If the occupation mode setting command SDCKB has been canceled (S46; Si), then SDCKA is inverted to the "H" level, and the system resumes a state where SDCKA and SDCKB can be used for transmission (S47). In this way, the occupation mode SDCKB is implemented. If the frame controller 58 identifies that the code set in the register command is a restart pattern output command (S18), then it makes the frame encoder 59 output to a restart pattern (S51), as shown by the sequence in Figure 39. In this way, signals of various formats can be transmitted. Now, the operation of the MIÉ during reception will be described. As shown in the sequence of Figure 40, the frame decoder -61 decodes received SDCKA and SDCKB, and identifies whether the received signals comprise a start pattern (S62), a start pattern with CRC (S64), or a frame error that does not correspond to any of these patterns (S66). If a start pattern is detected (S62; Si), then it is identified if this is an undefined start pattern (S71), as shown by the sequence in Figure 41. If this is an undefined start pattern ( S71; Yes), then a detection flag of frame error in the status register, and frame error detection processing prescribed by the driver software, or the like, is implemented. If this is a previously defined start pattern (S71; No), then a start pattern detection flag is set in the status register. In this way, the alternating shift register 62 is activated, and the data is extracted successively from the received SDCKA and SDCKB signals, the extracted serial data being demodulated to parallel data (S73). This demodulation / data transfer is repeated until the frame decoder 61 detects an end pattern (S71-S75). When an end pattern is detected (S75; Si), an end pattern detection flag is set in state register 55, and the reception is completed. On the other hand, if a start pattern containing CRC is detected, it is identified if in an undefined start pattern (S81). If this is an undefined start pattern (S81; Yes), then a frame error detection flag is set in the status register, and a frame detection processing prescribed by the driver software, or the like ( S82). If it is a previously defined start pattern (S81; No), then a detection flag is set for the start pattern with CRC in the status register. Through - this, the alternating shift register 62 is activated, the data is extracted successively from the received SDCKA and SDCKB signals, and the extracted serial data is demodulated to parallel data (S83). The CRC calculation is then conducted for the demodulated data (S84) and the demodulated data is written to the read buffer 56 (S85). This demodulation and data transfer is received until the frame decoder 61 detects an end pattern (S81-S86). When an end pattern is detected (S86; Si), the CRC calculation for the received data is compared with the CRC data appended after the data section to determine if there is a CRC error (S87). If a CRC error (S87; Si) is detected, then a CRC error detection flag is set in status register 55, and error detection processing CRC, such as a request for retransmission of data (Transmit Again) or the like, becomes possible. If no CRC error is detected, the process of detecting data through a signal pattern containing CRC is completed (S87; No). Figure 43 is a flowchart illustrating the acquisition and use of inherent information (Fixed Device Status) in relation to a peripheral device (device function) through embedded programs in applications (software) such as game programs. The supplied application program of a data storage medium such as a CD-ROM is stored in the memory and made through the CPU. The application program causes a device request command to be transmitted to the device function (S102), and then waits for a response from the device function. If no fixed device status of the device function has been received even after a prescribed time, it is determined that no device option is connected to the bus bar (S104; No), and a "no connection" processing is implemented. "(S106). If the Fixed Device Status is received from the device function (S104; Yes), then the license description information (S108), the destination region information (S110), and the identification of the device are compared with the information maintained by the game program application, etc., supplied from the media. data storage such as a CD-ROM (S112). If this comparison produces a coincident point (S112; Si), then processing is implemented to distribute an AP to a device function (S114). However, if the comparison does not produce a coincident point, then the processing is implemented to inform the user that the connected device functions (or connected peripheral devices) do not correspond to the application (S116). Then, processing is performed to disconnect these host device functions (S106), and the routine ends. • These functions are used as PL countermeasures (product obligation) for peripheral devices. In a shooting game, for example, an imitation pistol is used, but there is a risk that a device modeled exactly on a gun can be mistaken for a real gun. In certain countries, this type of use may not cause any problems, but in other countries it may cause it. In such cases, in the relevant countries only a "gun" whose external appearance clearly indicates that it is a gun imitation can be used. Therefore, in applications that customers and circumstances must take into account, in particular countries or regions, it is desirable if the type or model of peripheral device that can be used with that application can be restricted, through the State of Fixed Device previously described. In this way, in accordance with the connection standard for a game device and related peripheral devices according to the present invention, it is possible to connect a game device and a plurality of peripheral devices through a small number of bus lines. Further, if a user connects a peripheral gaming device to a gaming device via a cable or cord, then since a gaming device automatically identifies the connected device and initializes and starts the peripheral device connected in a manner that responds to the application, it is possible to eliminate special procedures and fixing operations involving the user, thus providing a suitable connection standard between a gaming device and peripheral devices. Furthermore, in the above-described embodiment, since the peripheral devices do not have the right to enter other devices connected to the busbar, but rather data communications are conducted in a format by which the peripheral devices respond for access by the gaming device, so that the regulation of access time between the gaming device and a plurality of peripheral devices becomes obsolete. Since the access of a peripheral device to another peripheral device is prohibited, it is also unnecessary to regulate the access time control between the peripheral devices. Therefore, only a relatively simple structure for hardware I / O software is required. In addition, a plurality of peripheral devices and various types of peripheral devices can be connected. For example, it is possible to connect a gaming device controller, game pad, keyboard, CD-ROM drive, DVD drive, voice input / output device, memory pack, FDD device, modem, ISDN terminal device, or similar. Furthermore, since data communications are conducted in accordance with a command format between the game device and peripheral devices, it is possible in a game application to obtain the data required at that time and situation in correspondence with the development of the game. of a game controller (peripheral device) or similar. In addition, since small volumes of data are transmitted intermittently, the noise induced by the connection cables is reduced. Since data transmission is controlled by a busbar controller, commands can be added or new peripheral devices can be easily developed by updating the controller. Since data can be transmitted between a gaming device and peripheral devices, it is possible to transfer multimedia data, such as sound output, sound input, idle screens, animated screens, etc., through a pair of cables . Since a main unit of gaming device or application can use the inherent information of a peripheral device, it can distinguish between peripheral devices that can be used with an application and peripheral devices that can not be used with that application, of a plurality of devices connected peripherals and desirably, should be able to suspend peripheral operations that are not compatible.

(Second implementation mode) Summary Next, we describe a second peripheral interface standard for an M bus. Of all the processing implemented in the bus bar M, this standard determines the interface specifications between the host MIÉ and the bus controller. collector M, the interface specifications between the MIÉ function and controller, the communications protocol specifications, and the data format. In the first place, the physical topology and the logical topology of the second interface will be described, following a procedure similar to the previous explanation of the first interface standard. (1) Physical connection topology Figure 44 presents an approximate illustration of the physical connection topology according to this second implementation mode. The physical connection mode comprises a host configuration, base configuration (peripheral device), expansion device (peripheral device). The base devices represent the hardware (peripheral device) connected directly to the host. The expansion devices represent the hardware (peripheral devices) connected to the host through a base device. In any system, there is an individual host (for example, a gaming machine). The host is capable of having a maximum of four ports to connect to peripheral devices. A base device is connected to a bridge. A maximum of four external expansion devices can be connected to any of the base devices. The host and base devices are connected through designated cables.

However, the following types of connections are not allowed: a) the direct connection of the host to the expansion device; b) the connection of the base device to the base device; c) the connection of the base device to the expansion device; d) the connection of the expansion device to the expansion device. These statements are not intended to limit the present invention to the embodiments. (2) Logical connection topology Figure 45 is a figurative diagram illustrating the logical connection topology according to the second mode of implementation. As this diagram shows, the logical connection between each function (formed by the hardware of the base device and the expansion device) and the host form a so-called star connection with the host in the center. The host controls signal transmission and reception.

Layer structure and communication flow Figure 46 is a figurative diagram for describing the layer structure between a host and peripheral devices. As the diagram shows, the host and the peripheral devices form a layered structure for data communications between them. In Figure 46, the function layer uses each function in a peripheral device, and conducts the transmission and reception of data according to the data format. A peripheral device can have up to three functions. The control layer I / O controls the transmission and reception of data in frame units and also controls the MIE (Machine l / F busbar M) which is described below. The bus interface layer conducts the physical connection and signal transmission and reception between the host and the base devices (or expansion devices). The data acquisition (data transmission) and the control between the application between the host and the physical functions of the peripheral devices are implemented through a function library, bar library, host MIÉ, connection lines, MIÉ of base device (or expansion), MIÉ controller, and functions.

Peripheral type Peripheral (peripheral) devices are classified and distinguished as follows. First, peripheral devices are classified into two types of devices: base devices and expansion devices. The base devices and the expansion devices are then further divided into game controllers and other peripherals. Examples of the type of peripheral device game controller include normal components of game devices, such as game controllers, game levers, flyers, and the like, associated with game devices. Examples of "other peripherals" include: keyboard, mouse (mouse), gun (imitation gun), and the like. An expansion device is a peripheral of a controller expansion system, examples of which include: a sound input, a flashback memory, a gun (imitation gun) and the like. The controller system has a fixed standard data format, so it can be used with any application software. Since the other base devices and expansion devices have different formats depending on the device, a function library is prepared for each respective function.

-Description of terminology Next, the technology used in the description of the second mode of implementation would be explained. For convenience, this partially covers the description in the first mode of implementation. First, the data that is expanded over a series of time is called "serial data." A signal line (flow), which conducts the exchange of data in a serial fashion, is called a "bus bar" in series. A bus in series connecting a game device with peripheral devices according to the standard in relation to the present invention is called a "bus bar M". A group of parameters indicating the function of a peripheral device and distributed to each respective peripheral device is called a "device identification". A device identification contains 16 bytes, including the attributes of the peripheral device, and the functions (data format and functional elements) that it comprises. Device identification can be obtained through a device status command, as described below. A terminal of the busbar M, wherein a peripheral device of the game device can be connected is called a "port". In a port terminal, there are four normal needles, comprising power supply terminals (VCC, GND) and data lines (SDCKA, SDCKB) or five needles, comprising an additional protection line. In "busbar M" according to the standard of the second implementation mode, a maximum of four ports are supported (port A, port B, port C, port D). The game device is known as the "host", and the functions performed by the peripheral devices connected to it are called "function". A function does not refer to the same product, but rather to an element that constitutes a product, and therefore, a product can comprise a plurality of functions. A peripheral device forms a collection of functions, and access from the host is conducted in peripheral device units, access to functions is specified by the type of function. A plurality of functions can be used in an individual peripheral device, but with the "busbar M" according to the second implementation mode, for example, a maximum of three functions can be used.

As shown in Figure 47, peripheral devices are physically divided into two types: "base devices" and "expansion devices". A base device is a peripheral device which is connected to the host and has the function of controlling expansion devices. A base device automatically identifies and connects an expansion device linked to it. An expansion device is a peripheral device connected to a base device, which does not operate if it does not have a base device. A busbar M linking a base device to an expansion device is called an "LM busbar". A busbar LM is equal to the busbar M in logical terms (signal), but is physically different. Of the peripheral devices, the base devices mainly comprise game controller systems and the expansion devices comprise expansion devices of the game controller systems. For example, only one base device can be connected to a host port, but the base device can handle up to five expansion devices (up to five LM busbars). In the case of a base device and a plurality of expansion devices in an individual port, an identification number is assigned to each base device and expansion device according to the point where it is connected, so that it can be accessed directly. This assigned number is called an "AP absolute position". In the "busbar M", the AP is an individual fixed byte that has the following structure: (Maximum of 4 ports (2 bits)) x (Maximum number of APs assigned to 1 port = 6 (6 bits)) = (1 byte (8 bits)). The distributed AP is determined according to the connection mode and whether the device is a base device or expansion device, as described below. This AP is used to access the base device or expansion device. The exchange of data between the host and functions is not conducted using a conventional side communication system, but rather using certain specific instructions, so that data appropriate to the situation and time can be transmitted and received. These instructions are called "commands", and the object data of the command is called a "parameter". A "parameter" is constituted by the AP of the target device, the AP of the source device, the size of data and data. In the bus bar M, a maximum of 254 basic commands can be prepared, and a maximum of 1020 bytes of data can be transmitted or received in an individual access operation. Data transmission conducted through a port is done in "frame" units. Figure 48 presents an example of the composition of a frame. A frame is constituted by a start pattern, a command code, a parameter (destination AP, source AP, data size, data and the like), parity bits and an end pattern. A frame is transmitted in an individual access operation. An access is made to a device within a range (INT). The start pattern, the parity bits and the end pattern are added by the MIÉ (described later). Figure 49 is a figurative diagram illustrating a response and "suspension" processing in an M bus. The response is transmitted when a host sends a command to a base device or expansion device, called a "response". After transmitting a command, the host waits for a response for a certain period, and if there is no response after the wait, this state is called "suspension". A base device (or expansion), which has been suspended, is considered by the host to be disconnected. In addition, if a base device (or expansion) performs a suspension when it is in reception, a software start is increased. The period until a suspension (response time) can be 1.0 ms, for example. In Figure 49, in case (1), the response of the base (or expansion) device is within the response time and is, therefore, normal. In case (2), there is no response, so a suspension occurs. In case (3), there is no response within the response period, so a suspension occurs. -In the case (4), the interval during data transmission exceeds the response time, so that the suspension occurs. The port to which a peripheral device that has been suspended is connected, implements a hardware reset. The place to connect an expansion device in order to expand the functions of the controller is called an "expansion receptacle". An expansion device is connected to an expansion receptacle. The "busbar M" can have a maximum of four expansion receptacles. This is due to the correspondence between the expansion receptacles and the LM busbars that is implemented according to the logic of two identification lines, which will be described later. The number - of LM busbars and the number of expansion receptacles does not have to be the same. A circuit, which converts the data to serial data for the busbar M so that they can be transmitted and received through the busbar M, is called a "MIÉ (bus l / F machine)". All normal M busbar devices have this MIÉ. The host has a host MID, the base devices have a base device MID, and the expansion devices have a MID expansion device. A MIÉ only converts data, so that the process of extracting data from a frame is carried out by the busbar controller M (described later) in the host, and by the software (firmware) called a MIÉ controller in the device.

The operation of the host to access a peripheral device is conducted through the "busbar controller M" and the "function library" of the software controlled by the peripheral devices (base devices and expansion devices). The busbar controller M controls and handles frames, while the control operations of each peripheral device (function) by commands and operating parameters (data format) are made by a function library. There is only one type of busbar controller M for all peripheral devices, while the function libraries are provided corresponding to each respective function. Up to three function libraries indicated by the device identification can be used for any peripheral device. 'In the "busbar M" all base devices and expansion devices register particular information by themselves according to a prescribed format. The information regarding a base device or expansion device is called "Device Status". The Device Status records management data, such as product name, device identification, license, model number, production lot, destination region, etc., and electrical data, such as current consumption at rest, consumption of maximum current and similar. Device Status is handled and used through a device library and application software. For example, it is possible to reject illegal product copies through product name and license information, and control the current of the entire port according to the information on maximum current consumption.

Data transfer pattern The physical data transmission in the busbar M will now be described. The same format is used for this data transmission as the first mode of implementation. In other words, the data is transmitted through a synchronized serial format. There is a total of four lines: Vcc to supply energy; a line to ground GND; an SDCKA data line (two paths) to transmit an SDCKA signal; and SDCKB data (two paths) to transmit a SDCKB load. Data communication in two ways uses a double medium system, and the transfer rate is, for example, 2 Mbps at most. If necessary, a signal protection cable can be added.

Transmission Principles Figure 50 shows data patterns for SDCKA and SDCKB. The signals transmitted by the serial data clock A (SDCKA) and the serial data clock B (SDCKB) are formed such that their falling edges are always present alternately when the data is transmitted. On the receiving side, one signal is closed at the falling edge (the rising edge) of the other signal and the closed signal level is demodulated to give the digital data. The data is transferred starting from MSB, and in the start position, SDCKA provides the clock information and SDCKB provides the data information. Information patterns according to SDCKA and SDCKB Figure 51 shows an example of a synchronization pattern. The synchronization pattern includes a start pattern (START) and an end pattern (END). The start pattern is a synchronization pattern transmitted before the data pattern. When the receiving side detects the falling edge (or elevation edge) of the SDCKB four times (four negative pulses) in the period of the fall of SDCKA to its subsequent elevation edge, it is concluded that the next pattern is a data pattern. When the receiving side detects the falling edge (or elevation) of SDCKA twice (two negative pulses) in the period from the SDCKB drop to its subsequent elevation edge, it is confirmed that the data pattern is over, and it is concluded that the operation has been completed normally.

Occupancy permit pattern SDCKB (light gun) Figure 52 shows an example of an occupancy permit pattern SDCKB. If the receiving side detects the falling edge of SDCKB eight times (8 negative pulses) in the period from the SDCKA fall to its subsequent elevation, the SDCKB can be occupied by the next SDCKA fall until it rises. The occupation of SDCKB must be released through an elevation edge of SDCKA. This pattern is used, for example, with a light gun in a shooting game.

Restart pattern Figure 53 shows an example of a restart pattern. If the receiving side detects the falling edge of SDCKB 14 times (14 negative pulses) in the period from the SDCKA fall to its subsequent elevation edge, it is concluded that there is a request to restart the edge of the side that transmits and increases a restart Transmission format Figure 54 shows an example of a transmission format. Data transmission is conducted in frame units (minimum unit). The content of a frame starts with a pattern indicating the beginning of data transmission, and also includes a data pattern with a maximum length of 1024 bytes, parity, and an end pattern. The parity comprises 8 bits in a horizontal direction and is automatically added by the hardware during transmission and deletion during reception.

Protocol The communication protocol between the host and the peripheral devices will now be described. The commands are indicated by the "command name", and the details are described later. Figure 55 is a figurative diagram that presents a summary of the communications protocol. First, the priority right to transmit commands in a processing sequence lies with the host. Therefore, initially, the peripheral devices (base or expansion devices) assume a state of command rest. All communications between the peripheral devices and the host are conducted in frame units, as described above. The host executes an application program and generates commands to the peripheral devices. These commands are transmitted to the peripheral devices through the busbar M as frame data. An instruction is given to a peripheral device through the command and parameters in a frame. When a peripheral device corresponding to the destination AP in the frame receives frame data, it responds accordingly. Mainly, the peripheral device generates a corresponding command and creates frame data, which it transmits to the host through the busbar M. Then, the peripheral device assumes a state of rest waiting for the next transmission of data. The host receives the frame data from the peripheral device and extracts the command (response). This command is then passed to the application. The application implements the subsequent action using the information transmitted by this command. The data communications between the host and the peripheral device are conducted by repeating this procedure. Figure 56 (a) presents an illustration of this type of intermittent data communication between a host and a plurality of peripheral devices through an M bus and LM bus bars. In addition, Figure 56 (b) illustrates an example where it is not possible to send all the data that will be transmitted in an individual transmission frame, and therefore, the data length is divided and transmitted intermittently in a plurality of transmission frames (see Figure 70 below). The aforementioned data communications process has the following characteristic aspects. The host can give access to a base device and expansion device directly using the same protocol, without the need for data conversion, or the like, during the operation. The AP data required for access is determined in accordance with the host port, the base device and the expansion enclosure, where the function is connected. When accessing a base device, the connection status of the expansion devices in this base device can be confirmed. Peripheral devices can still be connected or disconnected and the host is in an operational state. In order to obtain information regarding a peripheral device, the host requests a Device Status. If the Device Status is not requested, the peripheral device will not initiate the operation, but rather will remain in a state at rest. There are two types of peripheral device restart operation, namely, a software reset (restart command) and a hardware reset (restart pattern), which are described below. A software restart only restarts particular peripheral devices, connected to a port. A hardware restart resets all peripheral devices. Data transfer is conducted in frame units containing a maximum of 1024 bytes. Up to three functions can be used by an individual peripheral device, and the functions are accessed by specifying the respective function types. A maximum of one access operation to a function is possible within one interval (1 INT), and a data frame can be communicated by one access. An individual port is not accessed in a continuous manner. The manner in which these aspects are achieved are described below.

Frame data A maximum of one access operation is possible to a function during an internal I NT period, and the amount of data that can be transferred by an access operation is 1 frame of data transmission of 1 frame of reception of data. Figure 54 described above, shows examples of frame data, wherein a frame comprises a start pattern, a data pattern, parity bits, and an end pattern. The start pattern, the parity bits and the end pattern are designated by the data transmission pattern, and are automatically processed by the MIÉ. The data pattern in the frame is made up of units of 4 bytes, and contains a minimum of four bytes and a maximum of 1024 bytes. At a minimum of 4 bytes, it comprises only one command code, destination AP, source AP, and data size (= 00h). The command code indicates the command code that will be issued to the target device. The destination AP indicates the AP of the device to which the frame is transmitted. In other words, the host specifies the AP of a base device or expansion device, and a base device or expansion device specifies the AP of a host port. The Source AP indicates the AP of the transmission device itself. The data size indicates the size of the transmission data in units of 4 bytes. The data is the data for transmission (data format, etc.) and is stored in units of 4 bytes.

Command codes The command codes comprise 1 byte and store the codes for commands.

(Table 1) Composition of Command Code Here, COM0 - COM, are command codes. Command codes are specified on a scale of 01 h to FEh. The various types of command code are described below. The data described with reference to this table is stored in a suitable location in an internal memory or register, etc., which is not shown in the drawings.

AP, absolute position Now AP will be described. There are three types of AP: the AP of the same basic or expansion device; an AP indicating a destination for data (destination AP); and an AP indicating a data source (source AP). The AP of a base or expansion device is the AP of the same device, and is compared to the destination AP in a frame transmitted by the host and used to identify whether the host data is or is not directed to this device. The source AP of a device is the data written to the third byte of a frame, when a base or expansion device sends data back to the host (Figure 48). This indicates to the host on which device the transmitted data has been sent. In the device source AP, the last five significant bits indicate the pre-connection status of the LM bus. The host accesses a base device, and examines the source AP in the response command (frame of the base device) to see which LM busbars of the base device has the expansion device connected to them. The AP value is determined in accordance with the port, base device, and expansion device connection configuration (fixed receptacle number system), as illustrated in Figure 57, which is described below.

AP bit composition Table 2 shows a composition of AP bits maintained in an internal register. The AP comprises 1 byte (8 bits). The seventh and sixth bits of the AP are the port fixing bits PO, and PQ, which indicate the port of entry / exit of the port where the base device is connected. The fifth bit of the AP is a base device / expansion device fixing bit, which indicates whether the device is a base device or expansion device. The AP bits from four to zero are busbar fixing bits LM LM4 - LM0, which indicate the number of a busbar LM. (Picture 2) Composition of AP Examples of the use of port fix bits PO0 and PO., Are shown in Table 3. Any port of port A - port D is specified through the two port fix bits PO0 and PO ,.

(Table 3) Port Fixing Bits As shown in Table 4, the fixation bit of the base device / expansion device is "1" when the AP is set for a base device and is "0" when an expansion device is fixed, and is "0" "when a port is fixed.

(Table 4) Base Device Fixing Bits / Expansion Device The fixing bits of the LM busbar LM4 - LMj are shown in Table 5. If the AP specifies a base device or port, LM4 - LM0 are all set to "0". - If an expansion device is connected to an LM busbar, or an expansion device is accessed, then the LMn setting bit for the corresponding busbar is set to "1". Furthermore, if no expansion device is connected, then the LMn setting bit of the corresponding busbar LM is set to "0". When an expansion device is accessed, only the set bit of the LM busbar number of the expansion device that is accessed is set to "1".

(Table 5) Fixing Bits without LM Busbar The source AP where there is a response from a base device comprises the AP of the base device automatically combined with the OR gate with the expansion device connection state setting bits for the respective LM collection bars. For example, if the host gives access to a base device from port A (OOh), then the destination AP will be "00100000" (20h), and the source AP will be "00000000" (OOh). Here, h indicates a hexadecimal notation. If the expansion devices are connected to the base device in the LM busbars Nos. 1 and 3, then the response of the base device in port A will be: destination AP = "00000000" (OOh), source AP = "00100101" (25h). The source AP adds (through the OR operation) the connection status of the expansion devices (LM0 and LM2 = "1") to the base device's AP ("00100000"). Then, when the host gives access to an expansion device accessed to the LM busbar No. 1 of port B, the destination AP is "01000001" (41 h), the source AP is "01000000" (40 h). The response of the expansion device connected to the busbar LM NO. 1 is destination AP = "01000000" (40 h), source AP = "01000001" (41 h). Figure 57 presents a table of APs (hexadecimal notation) for base devices and expansion devices when they are accessed by the host. The Source AP when a base device responds is the sum (all OR sums) of the AP of the same base device, plus the AP values of the expansion devices connected to them. Therefore, the source AP of a base device will contain the information in the connection of the expansion devices. The host can tell from the source AP of the base device whether an expansion device or expansion devices are connected.

Initial Fixing Procedure for base device APs - Next, a procedure for the initial fixation of APs will be described. The person playing a game can connect base devices to any host port, and can also connect expansion devices to any LM bus in the base device. Therefore, before starting the game, the host must discover if a base device or expansion device is connected to any of the host ports, and must identify the AP of these devices. A method for initial AP fixation of the base device will now be described with reference to the flow diagram in Figure 58. Figure 58 shows an example of a case where the base device is connected to the host's A port and the Expansion devices are connected to the LM busbars No. 1 and 2 of the base device. The diagram illustrates the operation of the host and the base device CPU. First, the host, the base device and the expansion device are mutually connected through coication lines, and when the power supply for the devices is turned on, the initialization programs are booted from a ROM to the CPU in each device . The base device MIÉ is illustrated in Figure 64 below, and the expansion device MIÉ is illustrated in Figure 66. According to these programs, the base device (CPU) initializes the interface and port register, which are described later (S22, S24). Therefore, the base device generates an AP by itself. In this case, since the AP is related to the same device, only 5 bits of the AP are set to "1", giving an AP of "- 100000". Here, the "-" symbol indicates an undefined value (S26). Next, the base device investigates whether an LM busbar No. 5 was provided. Unlike the other LM busbars, busbar LM No. 5 is a bus connection or logic connection. This is because the uses are found out where the functions of the same base device are expanded, by installing an expansion device within the base device, or by using a base device or expansion device in combination. For example, if a game controller comprising a vibration function is created, then the game controller can form the base device and a vibration section can be connected to it through the LM busbar No. 5, all the device thus forming a game controller containing a vibration section. The presence or absence of this busbar No. 5 is already fixed in the CPU of the base device (this information is written in a ROM, etc.), and particularly does not require configuration, or the like. In the example, it is assumed that there is no LM busbar No. 5 (S28). - Next, the CPU of the base device fixes the LM busbars for the external receptacles. As shown in Figure 64, the base device generates a combination of voltage values that correspond to the relevant LM busbar number in particular terminals, for example, terminals ID0, ID., Of each LM busbar receptacle. , starting from station I / O. Table 6 shows examples of the output logic to the terminals ID0, ID1 of each busbar LM as fixed through the base device (S30).

(Picture 6) : The base device outputs "0", "0", respectively to terminals ID0, ID, busbar receptacle LM No. 1, and outputs "1", "0" respectively to terminals ID0 , \ D ^ of busbar receptacle LM No. 2. Logical output voltages are supplied to the expansion devices through the LM busbars and l / O ports. An expansion device examines the logical output values of the bus device, to identify which LM bus (expansion enclosure) is connected to (S32). The base device reads at a logical level from a specially reserved terminal, for example, terminal ID2, of the bus receptacle LM. The terminal ID2 is connected to ground through a pull-down resistor, and when an expansion device is connected to this receptacle, a voltage Vcc of the expansion device side is applied. As a result, when an expansion device is connected to this receptacle, the logic level of the terminal ID2 becomes "1". Also, if no expansion device is connected, then the logic level of ID2 becomes "0". By examining the logical level of ID2 with respect to the output of ip e (D towards the LM busbar, the base device can identify whether or not a device is connected to the LM bus of the number indicated by the logic output to the terminals aforementioned ID0 and ID, etc. Repeating this process, the terminal ID2 serves to confirm the connection of expansion devices, and when ID2 is "0", this indicates that no expansion device is connected, and when ID2 is "1" , this indicates that an expansion device is connected In this example, ID2 of the busbar LM No 1 and ID¿ of the busbar LM No. 2, are "1" (S34). Under certain conditions, the logic outputs to the receptacle terminals, ID0, ID, serve as a reset signal from the base device to an expansion device. For example, if the base device reverses the ID0, ID outputs to the expansion device, this will form an "interrupt operation" signal to the expansion device, and the expansion device will stop its operation. For example, if ID0, ID, were "00" and then were inverted to ID0, ID., = "11", the expansion device could interrupt its processing. In addition, if the base device inverts the ID0, ID outputs, and then also inverts them to their original values, this forms a reset signal for the expansion device and the expansion device will restart. For example, if ID0, ID1 were "00", and then ID0, ID, = "11" (interrupt signal) goes out to interrupt the expansion device, the base device could subsequently be rebooted. After the base device has been restarted, the expansion device is reset by switching to ID0, ID, = "00" (reset signal) (return to original values). After the restart, the devices assume the same status as the following one, a software restart, which is described later. Then, when the base device is transmitting, it generates a source AP. The source AP has the form of "~ 1xxxxx" depending on the AP of the base device and the state of terminal ID2. The "x" symbol in bits 0 - 4 will be "0" or "1", depending on the connection status of the LM busbars. In this example, the devices are connected to busbars LM No. 1 and 2 only, so that the source AP is "-100011" (S36). The base device expects to receive a Device Request, which is a type of command sent by the host. Unless the base device receives a device request, it remains in an idle state and repeats the processing of step 34 (S38; No). In this example, the base device is connected to port A of the host.

The destination AP for this host base device is "00100000", which indicates that the base device is in port A. The "1" in the fifth bit indicates a base device, and "00" in the sixth and seventh indicate a port A. The host, on the other hand, sends a command (Device Request) to each port at a time and waits for a response from a base device, so that it can identify whether the base devices or expansion devices (peripheral devices) are connected to ports A to D (H22). When the base device in port A receives a command (Device Request) from the host (S38; Si), it reads the source AP in the received frame, and gathers the number of ports that is connected from the sixth to seventh bit. . In this example, this is port A, so the bits are "00" (S40). In step S26, the base device completes its own AP (8 bits) using the least significant six bits previously created and the two most significant bits indicating the port (S42). Specifically, it combines the "00" (sixth and seventh bits), gathered for port A, and the AP previously created by the base device (= "--100000") (zero to fifth bit) thus completing the AP itself. base device as "00100000" (20 h in the hexadecimal notification). Then, the base device completes the source AP for the transmission frame. The bits of the port are aggregated at the most significant positions to the source AP previously completed only up to the six least significant bits in step S36. In this example, the port bits "00" are added to the source AP = "- 100011" to give a source AP "00100011" (S44). Observing the code in this source AP, it can be seen that the base device is connected to port A, and that the expansion devices are connected to busbars LM No. 1 and 2 of this base device. The base device creates a transmission frame in order to respond to the device response (S46). The base device prepares a Device Status • as a response command for the Device Request command. The destination AP is "00000000" indicating port A, and the source AP is "00100011" as described above. The base device sends a transmission frame containing State of Device, thus returning a command to the host (S48). Then, as long as the base device is not disconnected, its AP will be "00100000". The base device constantly checks the status of the terminal ID2 of the LM busbar receptacles. If the connection state of the expansion devices to the LM bus bars changes, then the bits in the source AP change, thus maintaining a source AP corresponding to the connection state of the expansion devices. • The host receives transmission frames from the base device and identifies that there is a base device connected to port A and that the expansion devices are connected to busbars LM No. 1 and 2 of this base device (H24). The host can tell if there are expansion devices connected to the base device simply by giving access to the base device. As described below, through the device status command, the host can also identify the details of the base device (peripheral device type, etc.), connected to the port. In the aforementioned AP fixing process, the receptacles by which the expansion devices are connected to the base device have fixed numbers, and it is verified to see and an expansion device is or not connected to each of the receptacles ( Fixed receptacle number (bar number LM) system). In other words, (a) after initializing the same base device, the base device first fixes ID0, ID, which corresponds to busbar LM No. (receptacle), and then (b) examines the logical level of ID2 in each receptacle to identify the presence or absence of an expansion device connection in each busbar LM. Next, (C) determines which number of LM bus bar expansion devices are connected to form the ID2 connection information and therefore, creates the six least significant bits of the source AP for the transmission frame based on this information. (d) the base device obtains information indicating the port of the host that is -connected to form the source AP in the frame received from the host and, adds the two most significant bits of this source AP of the base device thus completing the base AP source. On the other hand, it is also possible for the base device to perform a previous ID2 check to identify the LM busbars in use, and then to distribute the LM busbar numbers to the used LM busbars (receptacle number distribution system) (bus number LM)). Specifically, (a) after initialization of the same base device, the base device examines the logical ID2 to identify whether an expansion device is connected to a particular LM busbar, (b) then distributes ID0, IQ to the busbars LM collectors identified by terminal ID2 for having an expansion device connection. The numbers are distributed in ascending order, so that there is no overlap in the number distribution. Table 7 shows an example of busbar numbers LM and ID0, ID ,, the busbar LM whose connection state remains unchanged will retain its number from the previous state.

(Picture 7) Then, (c) the base device creates at least 6 significant bits of its source AP used when transmitting, based on the information in ID2 and ID0, ID. ,, (d) It then obtains information identifying the port of the host that is connected from the source AP in the frame received from the host, and adds the two most significant bits of the base device source AP, thus completing its source AP. Once the base device has established its source AP, if it then receives a command from the host that requires the AP to be updated, in the fixed receptacle number system, ID0, ID., Were provided corresponding to each receptacle, so that the processing implemented by the base device to update the AP starts in step (b) above. In the receptacle number distribution system, the receptacle numbers change, and therefore the processing in the base device for updating the AP starts from step (a) above. The initial setting procedure for the APs of expansion device A will now be described with a procedure for the initial setting of APs for expansion devices, referring to the flow diagram in Figure 59. In this diagram, the operations of the host, Base device and expansion device are displayed in parallel. In addition, the same step numbers are applied to sections corresponding to Figure 58, and these sections are not described here. In the example described herein, a base device is connected to the B port of the host, and an expansion device is connected to the LM busbar No. 2 of the base device. First, the host, the base device and the expansion device are mutually connected, and the energy is supplied to each device (K22). The base device MIÉ and the expansion device MIÉ will be described later through Figures 64 and Figure 66, respectively. The expansion device is connected to the base device and when a so-called "restart power" is implemented, its internal register and collector base port LM are initialized (K24, K25). -The expansion device (CPU) examines the LM busbar in accordance • with a control program. As described above, the logical levels corresponding to the number of LM busbars are output by the base device (CPU) to particular terminals, for example, terminals ID0, ID1, of each busbar connector LM. The expansion device reads the logic at terminals ID0, ID1 and the busbar LM to which it is connected (K28). In this example, the expansion device is connected to the receptacle 2, so that the logical output of the receptacle terminals ID0, ID, is set to "01". The expansion device identifies the LM busbar number by referring to the logical output of terminals ID0, ID, in Table 6.

-In this example, ID0, ID, = "01" so that the busbar number LM is identified as "2" (K30). The expansion device then creates its own AP. The expansion device recognizes that it is an expansion device. This is achieved by previously writing the necessary information in a ROM, or writing it directly in the expansion device control program. Bit 5 (device setting bit / expansion device bit) of the AP in the register shown in Table 2 is set to "0", and bits 0 - 4 (bus number number LM setting bits) are set to "0". set to "1" in correspondence with the busbar number LM where the expansion device is connected. In this example, the busbar LM is No. 2, so bit 1 is set to "1". Therefore, the AP of the same expansion device is "-000010" (K32). Then, the expansion device creates an expansion device source AP. Unlike the base device, the expansion device does not conduct a connection check for the source AP, and, therefore, the "source AP = expansion device AP". In this example, the source AP = expansion device AP = "-000010" (K34). The expansion device then waits for a host input frame containing a device request command, which specifies its own AP ("-000010") (K36). Unless a device request command is received, it continues to wait at rest (K36; No). As described above, since the connection status of the LM busbars has already been reported to the host by the base device (S48), the host knows which LM busbars have an expansion device connected to them (H26) . Therefore, the device request commands can only be transmitted to the expansion device so that the expansion device can be used in applications that allow the use of expansion device. In this • example, the source AP in the transmission frame sent by the host is "01000000" indicating port B, and the destination AP is "01000010" indicating an expansion device and the bus bar No. 2 ( H28). The expansion device receives the frame that contains the command Device Request (K36; Yes). Next, read the source AP of this frame data ("01000000") to gather the relevant port number of the host. Here, this port is port B, so the port number is "01". The expansion device adds the bits indicating port B to the most significant positions of the expansion device AP previously completed only for the least significant 6 bits, thus completing its own expansion device AP. In this example, bits "01" for port B are added to the AP expansion device AP "-000010", thus producing an expansion device AP of "01000010". 5 Next, the expansion device source AP is completed. The port bits are aggregated at the most significant positions to the source AP previously completed only to the six least significant bits. Here, the port bits "01" are added to the source AP "-000010" to give a source AP of "01000010" (K42) This expansion device source AP is equal to the device AP of expansion, of way this processing is omitted (K42). * The expansion device then creates a transmission frame in order to respond to the host (K44). It prepares a device status response command in response to the device request command. The destination AP is "01000000" indicating port B of the host, and the source AP is "01000010". He expansion device sends the command to the host (K46). This command is a device status command. Then, the expansion device maintains "01000010" as its own AP and AP source, unless the power supply or cables are disconnected. : The host gets the details of the connected expansion device (information varied in relation to the peripheral device) receiving the status command device expansion device.

Data Size The composition of the data size section contained in a transmission or reception frame will be described. The data size section comprises a single 25 byte, as shown in Table 8.

(Table 8) Composition of Data Size Here, the data DS0 - DS, in bit 0 - bit 7 indicate the data size. The data size section indicates the data size in units of 4 bytes, from a minimum of 0 bytes to a maximum of 1020 bytes. This is shown in Table 9. Data Size Data The composition of the data section contained in a transmission or reception frame will now be described. The data section stores data that will be transferred to a size indicated by the data size (4-byte units). For example, in a controller system, it contains the type of function and the data format of the controller. The composition of the data section is shown in Table 0.

(Table 10) Data Composition Data transfer A summary of the data transmission between the host and a peripheral device (base device or expansion device) will now be described. In this data transmission process, the rules are advised so that they are suitable for gaming devices. First, data communications are essentially conducted in accordance with a format by which the host makes request and peripheral devices respond accordingly. The instructions and requests of the host to a peripheral device are all implemented by commands (frames). If a command (frame) is transmitted to a peripheral device, the peripheral device always sends a command of some kind to the host. If a transmission error occurs, an error band is invoked and error processing is implemented through the hardware functions. -After connecting to the host, a peripheral device is activated after receiving a Host Device Request command for the purpose of gathering the details of the peripheral device, the peripheral device always sends back a command of some kind in response to a host command. The peripheral device (or function provided by this peripheral device) may receive, for example, a command during an INT interval.

Figure 60 is a figurative diagram illustrating the transmission of data between a host and a peripheral device. As previously established, the host and the peripheral device (base device or expansion device) are interconnected, and when the power supply is turned on, their respective APs are set before the data transmission begins. This produces respective inherent device AP, Source AP, and destination AP, which are required for data transmission. -Executing an application, the host CPU requires access to the peripheral device. The transmission data and the transmission command output by the application are respectively written to a write buffer and the host MIÉ registration command. The transmission data and the transmission command are constructed in a frame, as previously illustrated in Figure 48, and this frame is transmitted to the peripheral device, which is in a state of command rest. After receiving this frame, the MIÉ on the peripheral device reads the command and the data, and supplies them to the peripheral device's CPU. The CPU of the peripheral device reads the command and drives the processing corresponding to the command to obtain a response command and, if necessary, the data to be sent back to the host. This data and command are built in a frame through the peripheral device MIÉ, and then they are sent to the host. Next, the peripheral device assumes a state of rest waiting for the next command. When the host MIÉ receives the response frame, it writes the communications status to the status register and writes the received data to a read buffer. The host CPU then reads the data from both registers and the application continues. By repeating these operations, data communications are conducted between the host and the peripheral device (device or expansion device). The specific details of a communication process between the host MIÉ and the peripheral device MIÉ will be described later. If the hardware produces an error flag, then error processing is implemented. The details of the host's internal interface are also described below.

Transfer Error Here, the transfer error that occurs during data transmission will be described. Errors that can be detected by the hardware include: parity errors, interruptions and data overflows. A parity error is an error detected when the data frame parity does not match. An interrupt is an error detected when an interruption period has elapsed while the SDCKA and SDCKB lines remain in a stable state. An overflow of data is an error detected when the data volume exceeds the capacity of the transmit / receive buffer. Other errors other than these (for example, data corruption) are detected by the software. If a hardware detectable error occurs when a frame is received, this is indicated by an error flag or similar.

Error processing on the host If a reception error occurs on the host, a retransmission command is issued through the command sent to the peripheral device (base device or expansion device). The retransmission command is sent up to three times. If the error continues to occur, an "n connection" or error deployment, or similar, is implemented. The number of transmissions and the processing method vary according to the application software and the library. A retransmission command sent by the peripheral device is known up to three times for each transmission by the host, and then a processing of "no connection" or display of error, or the like, is implemented. An "offline" processing sends a hardware reset (restart pattern) to the port where the error occurred. Then, if necessary, a Device Request is implemented.

Processing of error in the peripheral device If a transmission error occurs, the peripheral device (base device or expansion device) conducts a retransmission operation in response to the requests of the host, but does not perform the error processing, such as retransmission based on the decision of the peripheral device. If a reception error occurs, the peripheral device can send a retransmission command to the host. If an interruption occurs during reception, the peripheral device implements a software restart. The interrupts are detected only by the base devices, and the restart signals are sent to the expansion devices, from a base device using the identification line.

Prohibited operations "In this standard, certain prohibitions apply. Specifically, (1) if a plurality of peripheral devices (base devices and expansion devices) are connected to a host, direct access from one peripheral device to another is prohibited. In principle, access must be conducted through the host. (2) A peripheral device can not use commands that can only be issued by the host. (3) The same port must not be accessed in a continuous manner. However, these prohibitions are only given as examples in a standard according to one embodiment, and are not intended to reduce the scope of the present invention or restrict the application of the invention. Of course, it is possible to conduct data communications through a separate standard that allows these forbidden operations, and the like. Connection and disconnection of peripheral devices. Here, the judgment processing implemented in the host to connect and disconnect peripheral devices (base devices, expansion devices) will be described. In order to implement this judgment processing, the host transmits a Device Request command to the peripheral devices in each port. As previously established, when the power supply is turned on, after connecting a host and peripheral devices, the host, the base devices and the expansion devices, each execute procedures to establish their own respective AP.

Therefore, before this judgment processing, the APs of the peripheral peripheral devices are determined for each port. The interval to which a Petition for Device interval 1 and INT is desirable. If there has been a response from the peripheral device, then it is not necessary to transmit a subsequent Device Request command. Naturally, it is not necessary for the host to transmit a command of Device request to ports not used by the application software.

Verification of connection of the base device The connection verification of a base device will now be described. If the host transmits a device request command to a particular port, and the command device status is returned by the base device, then the host identifies that a base device described by the Device Status (explained below) is connected to this port. If there is no answer from the base device (interrupt), then it is judged that there is no base device connected to this port. An interrupt is generated when there is no response in 1.0 ms, for example, from the transmission of the command.

Verification of connection of the expansion device Accessing only the base devices connected to their respective ports, the host also receives from the base devices information about the connection status of the expansion devices, connected to those base devices (through the source APs) and therefore, it is not necessary to perform a connection check for all expansion devices in the same way as the base devices. In addition, if, when a base device is accessed, an expansion device connection setting bit that previously did not indicate any connection in the source AP contained in the response of the base device has now changed to "1", this indicates that an expansion device indicated by that setting bit has been reconnected. Since the host can identify the connection state of expansion devices, after accessing a base device, it also transmits a device request to the expansion devices, and waits for a device status response command. Here, if no device status response exists, an interrupt is generated, and no expansion device is judged to be connected.

Peripheral device operation with respect to connection verification. All peripheral devices (base devices and devices) • expansion) assume a stable state immediately after the connection and rather starting their device operation, obtain at least six significant bits only from their own AP. A peripheral device will not respond to any host command until it receives a device request. The peripheral device then receives a request command from the host device. It registers the port AP to which it is connected from the source AP in the received frame, completes its own AP and source AP, and then initiates the operation to send back a Device Request.

Verification of Base Device Disconnection The host transmits a command to a connected base device (the base device previously confirmed as being connected to a port), and if there is no response from the base device within a prescribed period (interruption) ), the host concludes that the base device has been disconnected. This disconnection is confirmed three times, and if it is still disconnected, a restart pattern is transmitted after the 1 interval (1 INT).

Verification of disconnection of the expansion device If the host does not receive any response to a command transmitted to an expansion device, which has previously been confirmed as being connected to a port (interruption), then concludes that this expansion device has been removed and has assumed a disconnected state. This disconnection is confirmed three times, and if it is still disconnected, a restart pattern is transmitted after 1 interval (1 INT). In addition, the host gives access to the base device and receives a response frame from the base device. Then, if the host identifies that an expansion device connection setting bit in the source AP in the received frame has changed to "0", it concludes that the expansion device indicated by that connection fixing bit LMn has been removed and has entered a disconnected state.

Peripheral device operation with respect to disconnection If a base device is removed from a host port, the host's power supply to the base device connected to that port is interrupted. Therefore, the information regarding the connection port stored in the base device is lost. Consequently even if a base device whose connector has been removed later is reconnected to the host port (hardware reset), the base device will not start operating in this state. Similarly, if an expansion device is separated from a base device receptacle, the power supply to the expansion device will be interrupted and, therefore, the information stored in relation to the connection port will be lost. Consequently, even if the separate expansion device is reconnected to the base device receptacle, it will not start operating.

Restart There are two types of reboots: a hard reset (restart pattern) and a soft reset (restart command). Restarts can only be implemented by the host. A hard reset is a reset through a reset pattern, and allows all peripheral devices (base devices and expansion devices) connected to -certain port are initialized. No response is sent by peripheral devices.

A soft reset is a reboot through a device restart command, and is capable of initializing a particular peripheral device. In this case, the peripheral device in question sends back a device response command, whereby the peripheral device implements the auto-initialization process. The peripheral restart device (base device or expansion device) initializes your stored data, such as variables and RAM contents, etc. to the state immediately after switching on, with the exception of some functions. Since the AP of the peripheral device is initialized, when it is going to be reused, the host must transmit a device request. *. ' 106 Device Identification As described above, in a connection check, a peripheral device (base device or expansion device) which receives a device request from the host transmits a device status back to the host. 5 Variable information regarding the device is stored in this region of device status data, which forms the fixed device information. One of these is device identification. The device identification records whether the device is a base device or expansion device, the type of function, and the function definition block text. All peripheral devices have at least one device identification 10 and one or more functions. In this way, the guest can identify the peripheral device details connected to it (type, function, signal format, etc.). The various types of commands are described later.

Composition of the device identification 15 The identification of the device comprises 16 bytes (128 bits), as shown in Table 11.

(Picture 11) Here, FT indicates the type of function provided by the peripheral. FD1 indicates a function definition block of a first function. FD2 indicates a function definition block of a second function. FD3 indicates a function definition block of a third function FD1, FD2 and FD3 have a meaning of different content depending on the function indicated by FT. Table 12 illustrates the contents of the aforementioned function types FT0 - FTj,. The function type FT indicates a function provided by a peripheral device. There are 32 types of functions in total, each comprising fixation commands and data format.

(Picture 12) Types of Function * .In an individual peripheral device, for example, it is possible to set the three types of functions, and the fixing bits corresponding to a provided function are set to "1". A priority order exists for the fixing bits: the most significant bit (FT31) has the highest priority, and the least significant bit (FT) has the lowest priority. Up to three function libraries are set according to this priority order. In Table 11, FD31, FD10 indicates the first function definition blocks. There are blocks that define the individual elements that constitute the first function. The contents of them vary depending on the function. The details are governed by the respective function specifications (omitted in the drawings). FD231 - FD2o indicate second function definition blocks. These are blocks that define the individual elements that make up the second function. Its contents vary depending on the function. The details are governed by the respective function specifications. Similarly, FD331 - FD30 indicate third function definition blocks. These are blocks that define the individual elements that constitute the third function. Its contents vary depending on the function. The details are governed by the respective function specifications.

Format of function data and definition blocks The data format and definition blocks for functions will now be described. This shows the data format used to exchange data with a peripheral device. First, peripheral (peripheral) devices are classified and distinguished as shown in Table 13. (Table 13) Types of Peripheral Device As shown in the chart, a game controller represents a typical base device. The function type of a game controller is "the controller", and it is used by connecting it to a host port. The game controller uses a normal data format of fixation so that it can be used with a plurality of applications. The functional elements in a controller system are given below: Digital address key A: Ra, La, Da, Ua Digital address key B: Rb, Lb, Db, Ub Digital buttons: A, B, C, D, X, Y, X, START Analog key: A1, A2, A3, A4 Analog lever: A5, A6 In addition, it is a condition of the controller-peripheral devices of the system that are provided with the following elements: Digital direction key A: Ra , La, Da, Ua Digital buttons: A, B, START Other types of base device These other types comprise peripheral devices of a different type of function than the game controller. Since the data content and format, and the reading / structure cycle, etc., vary depending on the peripheral device, each device has a data format and data library corresponding to its respective functions.

Expansion devices These are peripheral devices to expand the functions of the base devices. Since the data content and format, and the read / write cycle, etc., vary depending on the peripheral device, each device has a data format and data libraries corresponding to its respective functions.

Controller type functions The function type indicates the controller data format and the device identification definition block. A read data format is shown in Table 14. The read data format is a format used to read the controller data. The data format size is 8 bytes.

(Figure 14) Controller Reading Format In this box, the first data is digital button data (ON = "O", OFF = "1"). The second data is digital button data (ON = "O", OFF = "1"). The third data is analogue axis data 1 (value between OOh and FFh). The fourth data are data 2 of analogous axis (value between OOh and FFh). The fifth data is data 3 of analogous axis (value 80h ± 7F). The sixth data is data 4 of analogous axis (value 80 h ± 7F). The seventh data is data 5 of the analogous axis (value 80h ± 7F). The eighth data is data 6 of the analog axis (value 80h ± 7F).

Write data format There is no format for write data to the controller. The data size is 0 bytes. If the data is written, there is no response. Function definition blocks The FD definition blocks for the game controller indicate functions divided into elements used in the reading format shown in Table 14. Table 15 shows an example of function definition blocks for a game controller.

(Table 15) Controller Composition Function Definition Blocks FD In this table, RBn indicates a divided block of reading format. Table 16 shows an example of block division. (Table 16) Block Division of Driver Read Format Bit 7 6 5 4 3 1 or 1o. Data RB R Bn 2o. Data RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 3rd RB data, n 4th. RB data "5th. RB data "6o. Data RB, 3 7o. Data RB14 | 8th RB data "| This table corresponds to Table 14, and the fixing bits for used blocks are set to "1" and those for unused blocks are set to "0". Unused blocks are ignored by the function library.

Device identification and data format for standard controller Table 17 shows an example of device identification for a standard controller. This example refers to a device identification for a standard controller that only has controller functions.

(Picture 17) Identification of Standard Controller Device The device identification shown in this Table comprises, in sequence from the first data to the data sixteen: 00h-00h-00h-01h-3hh-1hh-00h-00h-OOh-OOh-OOh-OOh-OOh-OOh-OOh . Table 18 shows the data format (read format) in a standard controller (Table 18) Standard Controller Reading Format No writing format is expected in a standard controller.

Storage type function A storage type function is a type of function for storing data, and indicates function definition blocks. Information other than function definitions (total capacity, etc.) is linked through a Get Media Information command. The type of function is FT, = 1, and the definition block in function (storage) is as shown in Table 19. (Table 19) Composition of Storage Definition Blocks In this table, PT0- PT7 represents division numbers. The number of divisions can be set between 1 and 256. The division number = (PT + 1). BB0 - BB represents byte numbers of block 1. These can be set from 32 bytes to 8192 bytes. The byte number in a block = (BB + 1) x 32 (bits). RAQ - RA5 represent read access numbers of block 1. These set the number of times of access that must be done to make the data in a block. The access number can be set between 1 and 15. The volume of data for an access is a volume of a block equally divided between an access number. The access number = RA (times) and the volume in an access = volume of a block / RA (bytes). RA = 0 indicates that there is no read access. WA3 - WA represents write access numbers of block 1. These set the number of times an access must be made to write the data in a block. The access number can be set between 1 and 15. The volume of data for an access is a volume of a block equally divided between the access number. The access number = WA (times), and the volume in an access = volume of a block / WA (bytes). WA = 0 indicates that there is no write access. RM represents a removable medium. This sets if the media storage data is removable (FD or flash memory card, etc.). An example of RM fixations is shown in Table 20. (Table 20) RM values FD6 - FD0 in Table 19 represents reserved bits. A reserved bit is a fix bit, which is reserved for future use. Usually, all these bits are set to "O".

Type B / WLCD function A type B / WLCD function indicates a monochromatic dot matrix liquid crystal display function, and a function definition block. Information other than the function definition (resolution, etc.) is obtained through a Get Media Information command. 'Function type FT2 = "1". The definition block of type B / WLCD may be, for example, as shown in Table 21.

(Frame 21) Composition of Function Definition Blocks B / W LCD -In Table 21, PT7-P represent LCD numbers. These can be set between 1 and 256. The LCD number = (PT + 1). BB7-BB0 represents byte numbers for an individual block transfer. These can be set at 32 bytes and 8192 bytes. The number of bytes in a block = (Bb + 1) x 32 (bytes). WA3 - W Q represents a block of write access numbers. These set the number of times an access should be done in order to write a block of data. The access number can be set between 1 and 15. The volume of data for an access is the volume of a block equally divided between the access number. The access number = WA (times), and the volume in an access = volume of a block / WA (bytes). WA = O indicates that there is no write access.

H? indicates whether the LCD data strip is horizontal or vertical. This is shown in Table 22.

(Picture 22) Value H? In Table 21, B W indicates whether the liquid crystal display is normally black or normally white. This is shown in Table 23.

(Picture 23) Value of B? / V Other functions The details of the data format and function definition blocks for functions other than the controller type functions are determined by the individual specifications for each function (omitted in the drawings).

Example of real access to peripheral device The following describes an example of a real method for accessing a peripheral device.

Processing after connection (1) The host confirms the destination region, the product name, license, operating current, etc., given in the Device Status command returned by the base device, and checks to see if the peripheral device is incompatible with the destination region of the host, not supported by the application, or not operating by the hardware, etc. If the base device is not compatible, the host implements a hard reset of the base device, or leads to processing to prevent the base device in question from being accessed later. (2) The host confirms the type of function of the base device of the data given in the Device Status. The host searches for the most significant function type fix bits, and calls up to three of the libraries for the most significant function. Then, the data required for the function definition blocks is prepared. (3) If the host identifies the source AP value that an expansion device is connected to, it transmits a Device Request to that expansion device and repeats the processing from (1).

Access to functions After connecting, the host enters communications with the peripheral device, and gives access to peripheral device functions. This will now be described using an example where the peripheral device connected to port A is a standard controller (game). (1) The host requests data from the standard driver. A command to obtain condition is used. This command requires that the physical condition of the function be transmitted to the host. The host requests the conditions of buttons, keys and levers in relation to the game controller. Desirably, the interval between the command transmissions is interval 1 (INT), for example, and faster access than this is forbidden. An example of transmission data sent from the host to a peripheral device (controller) is shown in Table 24.

(Picture 24) 'Transmission Data from the Host to the Peripheral Device (2) The data is transmitted from the controller to the host according to the data format. A data transfer command is used. Table 25 shows an example of the data transmitted from a peripheral device (controller) to the host.

(Picture 25) The type of function directly stores the type transmitted by the host, and the read format is appended accordingly. The read format of the controller comprises 8 bytes.

Exceptional processing Exceptional processing refers to special processing prepared for devices that do not control data transmission and reception through commands. A typical example is a light gun.

Light Gun 1) If the host determines that the peripheral device has the device identification of a light gun or firing pistol used in a firing kit, it switches the busbar M from the normal mode to the occupancy mode SDCKB when the Light gun is used. Mode switching is not possible from the side of the peripheral device. If the host transmits an occupancy pattern SDCKB (see Figure 52) and the port is switched to the occupancy mode SDCKB then all peripheral devices on this port are switched to occupancy mode SDCKB and only the peripheral devices that operate in the mode SDCKB occupation can work. If a plurality of devices having the device identification of a light gun are connected to a port, then the host indicates this to the user through a caution message, or the like, and informs the user through a presentation in screen or a sound to reduce the number of such devices connected to a port. (2) In order to return the busbar M of the occupancy mode SDCKB the host conducts the cancellation processing. When the occupancy mode SDCKB is terminated, the busbar M immediately returns to normal mode. (3) In the case of a light gun, occupancy mode SDCKB represents the period taken for interval 1 (INT) to write on the screen, minus the vertical target period, in other words, the period during which the television screen is drawing. When the drawing time on the screen is finished, and a blank period starts, the busbar M immediately switches to normal mode, and the data can be transmitted and received by the other peripheral devices on this port. (4) In order to perform the function of a light gun, a section comprising a photoreceptor element is taken as a function (it is also possible to use an expansion device), and a section comprising the trigger, direction keys , analog keys, etc., is taken as a different function (it is also possible to use an expansion device). Through this, it is possible to overcome conventional problems, such as disabling the arrow keys when the light gun is used. (5) In the occupancy mode SDCKB, no interrupt processing is implemented.

Internal host interface The interface between the bus controller M and the host IME will now be described (see Figure 46 and Figure 63).

Summary of the Host Internal Inferior The peripheral controller shown in Figure 63 comprises a record setting consisting of a plurality of registers within an objective section 52a. Specifically, the peripheral controller comprises: a 32-bit DMA instruction table address register; a selection register of DMA trigger; a DMA training record; a start / state record of DMA; a system control record; a state record; a record of hard trigger cleaning; a RAM work area protection record; Y Similar. Next, the basic operation of the peripheral interface in the host will be described. The peripheral controller loads transmission data in the work RAM indicated by the DMA instruction table address register to the transmission data FIFO in synchronization with the V_BLANK signal (the start delay can be set in the system control register ). The working RAM can be formed by distributing a particular area of the main memory. The transmission data include: instruction + storage address reception data + output data. The instruction is a command for the peripheral controller, and when the instruction is completed, the output port and the length of the transmission data, etc., are set. In addition, if the instruction has not been completed, as fast as the transmission data FIFO is empty, the transmission data in the working RAM is uploaded to FIFO of transmission data (conducted in units of 32 bytes). An initiator address, where the received data is stored, is set in the receiving data storage address. Transfer data is the data actually transferred to a peripheral device governed by the application protocol (4-byte units). The reception data of the peripheral device is in units of 4 bits, and as soon as FIFO of reception data (32 bytes) is filled, it is successively transferred to the work RAM area indicated by the receiving data storage address. Here, even if FIFO is not full, as soon as the reception is completed, it is transferred in a compulsion-like manner as 32 bytes (valid data + invalid data). In addition, if the peripheral device causes an interruption (for example, 1 ms), due to a disconnection or disabling, etc., the 32 bits ffff_ffffh are written to the storage address of the initiator reception data corresponding to this instruction. When this sequence of operations is completed, the peripheral controller interrupts its operation, and reflects the status of the start / DMA register.

Registration map DMA instruction table address record The DMA instruction table address record is a readable and typable record, comprising 32 bits. The constituent elements are: a command (instruction) to the peripheral controller; a reception data storage address; and bits indicating an initiator address for the transmission data group (Ct31-Ct5).

DMA trigger selection register The DMA trigger selection register is a writeable and writeable register comprising 32 bits. The constituent element is a selection bit (Ts) that refers to the transmission trigger and reception start if it is a software start or a hardware start (blank V).

- Register to enable DMA The register to enable DMA is a writable and readable record comprising 32 bits. The constituent element is a selection bit that is enabled and disabled for transmission / reception (Tn). In the case of a software trigger, this bit is enabled and transmission or reception is initiated by setting the start bit DMA shown in the start register / DMA status in "1". In the case of a hardware trigger this bit is enabled and transmission and reception is initiated at the time of detecting the hard trigger (blank V). In addition, in the enabled state, it is possible to implement a compulsory termination written in "0".

Start register / DMA status The start register DMA is a writeable and writeable register comprising 32 bits. The constituent element is a bit (Ss) to implement a software start for transmission / reception. In addition, when it is read, it becomes a status register, indicating the transmission / reception status. Only when a software trigger is selected as the start trigger, it is valid for "1" to be entered, thus initiating the transmission.

System control register The system control register is a 32-bit read and writeable register. The constituent elements are: The interruption setting bits (To, 5-To0) of the data transmission to a peripheral device; a selection bit (Yes) to select if there is a start in each blank V in the case of a hardware trigger, or if the operation is suspended until the flag in the clean register is cleared; transfer speed setting bits (Dc3 - Dc0); start time setting bits (Dt¡- D) (set blank delay V) when there is a hardware start. The interruption setting time (= 20 ns x To15 - To0). For example, it can be set at 300 μs = 20 ns x 3a98h. If it is a repeat setting bit for automatic start. When this bit is "0", a start is implemented in each interval. When this is "1", the next start is not implemented until the flag in the clean record of hardware trigger is cleared. From, - D ?, indicates the transfer rate setting bits.

Status register The status register is a read-only register comprising 32 bits. The constituent elements are: a bit (Do) indicating that the peripheral controller is in operation (during transmission / reception); bits for verifying an internal block state counter (St5 - Sto); and bits to verify the input / output line of each port (L ^ -La0, Lb, - l). This registry is used for debugging hardware and not for the application.

Clean Log of Hardware Trigger - The clean log of hardware trigger is a write-only log that comprises 32 bits. The constituent element of this register is a cancellation bit (Te) for an individual hardware automatic start interrupt in the peripheral controller. The automatic interruption is cleared by typing "1" in this bit.

Work RAM area protection record The work RAM area protection record is a write-only record that comprises 32 bits. The constituent elements of this register are fixed bits: a 16-bit write security code; a scale initiator for the receiving data storage address (Ha); and termination address (Ta).

Transmission data address counter register The transmission data address counter register is a read-only register, comprising 32 bits. The constituent elements indicate a direction point for transmission data in the working RAM, which are read through the peripheral controller. Since this record is for debugging, it is not used by the application.

Receipt data address counter register The reception data address counter register is a read-only register comprising 32 bits. The constituent elements indicate a direction point for reception data in the working RAM, which are written by the peripheral controller. Since this record is for debugging, it is not used by the application.

Receipt database address registration The address database address register is a read-only register comprising 32 bits. The constituent elements indicate an initiator address for reception data in the work RAM, which are written by the peripheral controller. Since this record is for debugging, it is not used by the application.

Transmission data • Next, the transmission data will be described. A transmission data unit comprises: an instruction, reception data storage address and output data. Whenever this data is stored in the work RAM as: instruction + reception data storage address + output data + instruction + reception data storage address + output data ..., the peripheral controller executes this in sequence.

Instructions An instruction comprises 32 bits of data supplied to a peripheral controller by the application program in order to control the peripheral controller.

The constituent elements are: an end bit indicating the end of the instruction in progress; active port selection bits (Ps, Po0) for transmission and reception; pattern selection bits (Pn2 - P ?,); and output data length selection bits (n - Ln). When the peripheral controller detects that the Ef bit is "1", the processing for that instruction is completed (the final command in the transmission data must always be set in the Ef bit to "1"). In addition, if the peripheral controller detects that the Ef bit is "0", it executes the following instruction. When "START" is selected in the pattern selection bits, the output data is output. When another pattern is selected (allowed occupation pattern SDCKB, RESET or allowed occupancy pattern calculated SDCKB) only the information pattern output is valid on the port, and the specification of the output data length becomes invalid. When the occupation permission pattern SDCKB is selected, the Ef bit in this instruction must be set to "1". The execution of any of the subsequent instructions must be invalidated, with the exception of the occupation cancellation pattern SDCKB. In addition, during occupancy SDCKB, the peripheral controller outputs the negative edge input through the SDCKB line as closing signals of the HV counter. The output data length selection bit Ln can be set, for example, up to 1024 bytes, in units of 4 bytes.

• Receiving data storage address The receiving data storage address is a setting bit (Ra) for the address of the initiator for storing reception data.

Output data The output data is the data actually transmitted to the peripheral device. The data length of the output data must be equal to the length of output data length set by the aforementioned instruction (32 bit units).

Interruption record The interrupt record is not contained in this interface. Rather, six signals are connected from the interface to an interruption block. An interruption occurs, for example, when transmission or reception is completed (DMA termination), when a transmission or reception (DMA) operation is extended to V BLANK IN, when reception FIFO is full and it seeks to write additional data to reception FIFO, when there is a fixation or initiation outside the protection area of the DMA instruction table address and when there is a false illegal instruction operation, and the like.

HV counter register - The HV counter register in a light gun mode is not contained in this interface. Rather, an HV closing signal is connected from the interface to the drawing block. The application of the value of the HV counter in the drawing block during V BLANK.

Transmission / reception sequence The transmission and reception sequence will now be described. The transmission / reception sequence comprises a normal sequence and an occupancy procedure SDCKB, as described below.

Normal sequence An example of a normal sequence is shown in Figure 61. This diagram illustrates the flow of data transmission and reception between a host CPU and peripheral controller, shown in Figure 63 described in detail below, and peripheral devices A and B illustrated in Figure 64.

In Figure 61, the host CPU determines whether a peripheral device is connected to any of its ports and identifies the destination APs for the relevant peripheral devices through the aforementioned AP securing operation. Then, it gathers the details of each peripheral device transmitting a Device Request to the peripheral devices and receiving corresponding responses. Then, for example, the CPU sets transmission data in the working RAM for the DMA operation, in order to drive data communications with the peripheral device A in response to an application request, or the like, and various operations of fixation for instructions, etc., are implemented in the registers within the objective section 52a of the peripheral controller. These instructions are commands supplied to the peripheral controller, and set the end of an instruction, output port, output data length, and the like. Furthermore, if the end of an instruction is not indicated, the transmission data in the work RAM will continue to be loaded into transmission FIFO 53a, as soon as transmission FIFO 53a is emptied. The loading operation is conducted in units of 32 bytes, for example. "The peripheral controller loads the transmission data in the work RAM indicated by the instruction table address register DMA to transmission FIFO 53a in synchronization with the emergence of the V BLANK signal in the supplied video signal (end of period of white), for example, as previously established, a start delay can be set through the system control register.The peripheral controller creates transmission data in the frame format illustrated in Figure 48 based on the instructions and data output through the CPU, and sends this transmission data to the busbar M of the relevant port.The peripheral device A continuously checks the data signal in the busbar M. When it confirms that the destination AP of the transmission data matches its own address (AP), reads in these transmission data.The peripheral device A then implements corresponding processing to the command, and creates response data in a prescribed frame format, which it sends to the busbar M. After receiving the data from the peripheral device A, the peripheral controller first places the received data in this receiving FIFO 56b, and then it transfers them to the working RAM for the operation of the DMA. The data received from the peripheral devices are in units of 4 bytes, for example, and as soon as FIFO reception 56b is filled (32 bytes), the data is transferred to the work RAM indicated by the receiving data storage address. However, even if reception FIFO 56b is not filled, as soon as the reception ends, the data is compulsively transferred as 32 bytes (valid data + invalid data). Then, the data that remains in the working RAM, which will be transmitted to the peripheral device B, is read, placed in FIFO of transmission data 53a and formed in transmission data directed to the peripheral device B. These are then transmitted to the busbar M of the port to which the peripheral device B is connected. Similarly to the peripheral device A, the peripheral device B continuously checks the data signal in the busbar M. When it confirms that the destination AP in the transmission data matches its own address (AP), it reads in this transmission data. The peripheral device then implements the processing corresponding to the command, and creates response data in the prescribed frame format, which it sends to the busbar M. After receiving the data from the peripheral device B, the peripheral controller first places the received data in receiving FIFO 56b, and then transferring them to the working RAM for the DMA operation.

The CPU reads the status of the peripheral controller in synchrony with the drop of the V BLANK signal in the supplied video signal (start of the target period). Thus, you can identify the presence of data from a peripheral device. It then reads the stored reception data from the relevant area of the work RAM, and provides this data to the application. Data communications between the host and peripheral devices are conducted by repeating this procedure. When the sequence of operations ends, the peripheral controller interrupts the operation and indicates its status to the DMA start / status register. If the peripheral device causes an interruption (for example, 1 ms) due to a disconnection or interruption, etc., the peripheral controller writes a 32-bit ffffjfffh to the initiator address data storage address register corresponding to this command . If a parity error occurs, a 32-bit ffff_ff00h is written. The CPU implements the corresponding processing to this.

• SDCKB occupancy procedure (light gun) Next, the SDCKB occupation procedure will be described with reference to Figure 62. The occupation procedure SDCKB is used, for example, for data communications between the host and a firearm. light that forms a peripheral device in a shooting game. As previously established, the CPU determines if a peripheral device is connected to any of its ports and identifies the destination APs of the relevant peripheral devices through the aforementioned AP fixing operation. Then it gathers the details of the peripheral devices transmitting a Device Request to each peripheral device and receiving its corresponding answers. The CPU, for example, sets the transmission data in the work RAM through the DMA operation, in order to drive data communications with the light gun in response to a request from the trigger game application, and performs several fixing operations for instructions, etc., on the registers within the target section 52 of the peripheral controller. For example, if a gun game application requests SDCKB occupancy from the CPU, the CPU switches the port operation from the normal mode to the occupancy mode SDCKB. Through the aforementioned commands, the transmission data containing the selected port and the occupancy permit SDCKB are written in the work RAM. The data address in the work RAM is written to the address register of the DMA command table. The peripheral controller loads the transmission data in the work RAM indicated by the table address register DMA command to the transmission data FIFO 53a in synchronization with the emergence of the V BLANK signal in the supplied video signal, for example . The peripheral controller then reads the commands and data from the work RAM, creates an occupancy permission pattern SDCKB of the format illustrated in the Figure 52, and transmit this to the busbar M of the relevant port. The peripheral device A continuously checks the data signal in the busbar M. After receiving the occupancy permission pattern SDCKB, the peripheral device A is able to transmit its output to the busbar M at a desired time. If the peripheral device A (light gun) is operated by the user (the trigger is pulled), then the peripheral device A (light gun) transmits a trigger signal to the busbar M. When the peripheral device receives the data of trigger signal of the peripheral device A, this outputs a closing signal to the HV counter (omitted in the drawings). The HV counter counts the values corresponding to the position of the lighting point that is being scanned on the video screen. From the values of the closed HV counter, it is possible to identify the target point of the peripheral device A (light gun) on the screen, when the trigger is activated. If the peripheral device is a light gun, the CPU distributes the pattern on the video screen within a period of 1 interval of the video signal supplied as an occupancy period SDCKB. Then, when the drawing period is finished and the V BLANK signal drops (start of the target period) the CPU cancels the occupation mode SDCKB and switches the operation of the relevant port of the occupancy mode SDCKB to the normal mode. For this purpose, the CPU writes the transmission data containing the selected port and the occupation cancellation SDCKB to the working RAM through the aforementioned commands. The address of the data in the work RAM is written in the DMA command table address register. The peripheral controller immediately loads the transmission data in the work RAM indicated by the DMA command table address register to the transmission FIFO. The peripheral controller reads the commands and the working RAM data, creates an occupancy permission cancellation pattern SDCKB and transmits this to the bus bar M of the relevant port. The peripheral device A continuously checks the data signal in the busbar M. If an occupancy cancellation pattern SDCKB is received then the peripheral device A cancels its output enabled state. In this way, the occupancy mode SDCKB occupies the period during which the video screen is drawing in a range of 1 of the video signal. Therefore, even if a peripheral device that produces a random output, such as a light gun, is used, it is still possible to use other peripheral devices connected to the same busbar M.

Record setting method Examples of record setting will now be described in the case of a software start and a hardware start (automatic start of each trigger). In a software startup, prescribed registry values are set in the following cases.

Initialization 1. Setting of work RAM area protection record. 2. Setting of the system control record 3. Setting of the DMA trigger selection register Implementation procedure 4. Setting of data in the work RAM (DAM command table) 5. Setting of the DMA command table address record - 6 Setting the DMA enable register 7. Setting the DMA start / state register Completion verification 8. DMA start / DMA status confirmation 9. Interruption of reception data to the work RAM - At a hardware start (automatic start in each trigger), prescribed register values are set in the following cases. Initialization 1. Setting of work RAM area protection record 2. Setting of system control record. 3. Setting of trigger selection register DMA Implementation procedure 4. Setting of data in work RAM (DAM command table) 5. Setting of DMA command table address record 6. Setting of DMA enable register 7 DMA start / state registration setting Completion verification 8. DMA start / status confirmation 9. Interruption of reception data to work RAM Host block diagram MIÉ Figure 63 is a block diagram showing the proper composition of a peripheral controller (MIÉ) 1h in a host. In this diagram, the sections that correspond to Figure 21 are marked with the same symbol. -In Figure 63 an initiator section 50 performs the role of a master bus to access the work RAM, when the peripheral controller 1 h has assumed an operating state. Read the data that will be transmitted to a peripheral device in the work RAM and write the data received from a peripheral device in the work RAM. The clock divider 51 is a clock division circuit for selecting the bit rate (transfer rate) of the transmission data. The objective section 52a is a block that operates as a target on the address bus, and is formed by the host CPU through the aforementioned group of data records. 32 bits that can be read and written. Principally, instructions or similar are written in this section. The transmission data temporary register 53b is a register for storing 32 bits of FIFO transmission data of 3-byte transmission data 53a. Transmission data FIFO 53a is a FIFO register of 32 bytes (First in to First out) to temporarily store transmission data. The reception data FIFO 56b is a FIFO register of 32-byte reception data. The reception data buffer 56a is a register for storing 32 bits of reception data. As soon as the data reception is complete, the reception data is written in reception data FIFO 56b. The interrupt signal control section 54 generates an interruption signal of a clock pulse, which is sent to an interruption section under certain conditions. The frame controller 58 is a block that controls the transmission frame (start pattern, data pattern, end pattern, etc.) based on the instructions, and the like. The frame encoder 59 is a block to create a frame pattern. An alternate shift register (parallel / series) 60 is a circuit for converting parallel transmission data into two lines in series, alternately. In addition, the alternating shift register 60 performs a parity calculation for the transmission data and append parity data (e.g., a parity bit byte) at the end of the transmission data. The frame decoder 61 is a circuit for analyzing a frame of the reception signal. The alternate (serial / parallel) shift register 62 is a circuit for converting alternately received data of the two serial lines into parallel data. In addition, the alternate shift register 62 performs a parity calculation for the reception data. These calculation results are compared with the parity data received to determine if an error exists. If there is an error, a notification of this effect is sent to the CPU interrupt controller through the interrupt signal control section 54. In this way, the CPU is able to conduct error processing, such as by issuing a retransmission command or similar. The closing signal control HV 63 is a circuit for transferring a closing signal HV of the lines in series to an HV counter in a drawing processor section (video signal generation section) 1f. The port controller 57 controls the active port that refers to the transmission / reception process. In other words, the three-state buffer 68a-68h of the transmission port selected by the instruction is controlled so that the outputs of SDCKA and SDCKB of the selectors 64 and 65 are directed to the selected port. The selector 64 is controlled through the frame controller 58, and forms an SDCKA signal by selecting the output of the frame decoder 59 or the output of the alternating shift register 60 and outputs this signal to a bus bar line M through of the three-state buffer 68, selected. The selector 65 is controlled by the frame controller 58 and forms an SDCKB signal by selecting the output of the frame encoder 59 or the output of the alternating shift register 60, and outputs this signal to a bus line M, a through the selected three-state buffer 68. The selector 66 selects a reception port according to the commands of the port controller 57, and supplies reception signal SDCKA, which has passed through a buffer amplifier. 69, to the frame decoder 61 and alternating shift register 62. The selector 67 selects a reception port in accordance with the commands of the port controller 57, and SDCKA receive signal, which has passed through an amplifier buffer memory 69, to frame decoder 61 and alternating shift register 62.

INTERNAL INTERFACE OF THE PERIPHERAL DEVICE FIG. 64 is a block circuit diagram giving an approximate illustration of the circuit composition of a peripheral device which is a base device. In addition, Figure 65 is a block circuit diagram giving a more detailed illustration of the filter (MIÉ of base device) between the receptacle control section 203 and the communications processing section 204 shown in Figure 64. In these examples, in order to simplify the description (illustration), only two external expansion receptacles are presented, but in reality, four external expansion receptacles can be provided. The CPU block 201 performs the control functions of the base device, such as forming transmission data carrying the input operation information, and processing response data corresponding to the requests of the host 1. This also includes initialization operations , such as setting the APs of the device and the APs of the expansion device during startup, as previously described. Block I / O 202 converts the operation information of the input means to a data signal. If the base device 2 is a control palette of a game device, then a plurality of digital buttons and analog keys, etc., correspond to the input means. In addition, the I / O block 202 indicates a busbar number LM for expansion devices connected through the IDO and ID1 terminals of each expansion enclosure, according to the output of the CPU. The role of the IDO and ID1 terminals has been described above in the AP fixation processing for expansion devices, with reference to Figure 59. The receptacle control block 203 determines the presence or absence of an expansion device connection in each expansion receptacle. Then, the SDCKA and SDCKB data lines supplied to the device by the host are respectively connected to the bus data lines LM SDCKA and SDKCB through the three-state buffers in the expansion receptacles to which the expansion devices. Therefore, seeing the busbar M from the host 1, this is equivalent to a plurality of peripheral devices (base devices and expansion devices) that are connected to the busbar M in parallel. The communication processing block 204 performs the decoding of reception data and the coding of output data of the CPU, and the like. The CPU block 201 - the communication processing block 204, can be constituted through an individual integral chip.

The communications processing section 204 performs the functions of the demodulation frames received from the host, and the frame transmission data output (decoding) through the CPU section 201. The communications processing section 204 and the section 203 receptacle control together form the main components of the MIÉ (input / output interface). The signal SDCKA (downstream signal) leaving the host to the busbar M is supplied to the communications processing section 204 through a buffer amplifier 212a. Further, having passed through the buffer amplifier 212a, the signal SDCKA forms a signal SDCKADS-1 and a signal SDCKADS-2 through the buffers of three respective states 215a and 215b, which are supplied to the busbars LM 1 and 2. The signal SDCKB (downstream signal) that leaves the host to the busbar M is supplied to the communications processing section 204 through an amplifier of buffer 212b. further, being passed through the buffer amplifier 212b, the signal SDCKB forms a signal SDCKBDS-1 and a signal SDCKBDS-2 through the buffers of three respective states 216a and 216b, which are supplied to the busbars LM 1 and 2. On the other hand, an SDCKA signal for the host output (upstream) by the device communication processing section 204 exits through (the first terminal of) an OR gate 214a and a buffer of three. states 211 to SDCKA of busbar data line M, where they are received by the host's MIÉ. In addition, an SDCKB signal towards the host output through the communications processing section 204 exits through (the first terminal of) an OR gate 214b and a three state buffer 211b towards the bar data line SDCKB. collector M, where it is received by the host MIÉ. When the communications processing section 204 transmits an SDKCA signal, or an SDCKB signal, a permitted signal is supplied to the three-state buffer memory control terminal 211a through (the first terminal of) an OR gate 213a with in order to open the gate 211a (turn it on), and an enabled signal is supplied to the control terminal of the three state buffer 211 ba through (the first terminal of) an OR gate 213b in order to open the gate 211b. The respective input terminals of the three input gates OR 213a and 213b are connected to ground through a resistor. If there is no input signal at the input terminal, that input terminal remains at ground level. In addition, the respective input terminals of the three input OR gates 214a and 214b are connected to a power supply Vcc through a resistor. In this way, the input terminals to which there is no signal input, are maintained at the "H" level. An SDCKA signal output from the first expansion device to the busbar LM 1 is drawn to the bus data data line M SDCKA through the terminal SDCKAUS-1 of the expansion enclosure 1. The gate OR 214a (second bus terminal) input of) and the three-state buffer 211a. An SDCKB signal output through the first expansion device to the busbar LM 1 is pulled to the bus data data line M SDCKA through the terminal SDCKBUS-1 of the expansion enclosure 1, the OR gate (second terminal). input of) 214b and the three-state buffer 211b. When the first expansion device transmits an SDCKA signal or an SDKB signal, it supplies a signal capable of controlling the terminal of the three-state buffer 211a, via the busbar LM 1 SDCKAEN1 and the gate OR (second input terminal of ) 213a, in order to open gate 211a. In addition, it supplies a signal enabled to the control terminal of the three-state buffer 211b, via the bus signal line LM 1 SDKBEN1 and the gate OR 213b (second input terminal of), in order to open the gate 221b. Similarly, an SDCKA signal output through a second expansion device to the busbar is output to the SDCKA data line of the busbar M, via the SDCKAUS-2 terminal of the expansion enclosure 2, (the third bus terminal). input of) of gate OR 214a and the buffer of three states 211a. An SDCKB signal output through the second expansion device to the busbar LM is output to the bus data data line M SDCKB via the SDCKABUS-2 terminal of the expansion enclosure 2, the OR gate 214b (third terminal). input) and the three-state buffer 211b. When the second expansion device transmits an SDCKA signal or an SDCKB signal, this supplies a signal enabled to the control terminal of the three-state buffer 211a, through the bus signal line LM 2 SDCKAEN2 and the gate OR 213a (third input terminal), in order to open gate 211a. In addition, it supplies a signal enabled to the control terminal of the three-state buffer 211b, through the bus signal line LM 2 SDCKBEN2 and the gate OR 213b, (third input terminal), in order to open gate 211 b. A supply of operating power is supplied to the base device from the host via the power lines Vcc and GND of the busbar M. The power supply to the expansion devices is supplied through the base device by means of the Vcc and GND power lines in the LM busbars. As shown in Figure 65, the receptacle control section 203 is constituted by a busbar controller LM 203a. The busbar controller LM verifies the voltage of a particular terminal provided to verify the connections in the expansion receptacles. In this example, the needle voltage ID2 of the expansion receptacles is checked. On the side of the base device, the needle ID2 is connected to ground supply GND of the base device through the resistance R. As shown in Figure 66, when an expansion device is connected to an expansion receptacle , the power supply Vcc and GND is supplied to the expansion device 3 through the terminals Vcc and GND of the expansion receptacle. This power supply Vcc to the side of the expansion device is applied through the terminal ID2 of the expansion housing of the base device to the resistance R. The busbar controller LM 203a determines whether or not an expansion device is connected to a receptacle from the presence or absence (or magnitude) of the voltage produced in resistor R. The busbar controller LM 203a indicates the connection or not connection of an expansion device in each busbar LM to a control register 204a. The busbar controller LM 203a also opens the gate of the three-state buffers of the LM busbar of the expansion enclosure, where the expansion device is connected, and respectively connects the data busbar data SDCKA and SDCKB to the LM busbar data lines of SDCKADS and SDCKBDS. The busbar controller LM 203a is capable of activating the control of the busbars of the expansion connector independently of the operation of other sections, but it is also possible to do this depending on the judgment of the CPU. Mainly, the busbar controller LM 203a detects the connection of an expansion device and sets a detection output in the control register 204a. The CPU 201 identifies the connection of an expansion device to a busbar LM by checking the control register 204a. If the CPU 201 allows the connection of the expansion device, it sets an LMC flag instruction connection of the relevant LM busbar in the control register 204a. The busbar controller LM 203a opens (turns on) the buffers of three states 215, 216 of the bus bar LM corresponding to the LMC flag. Through these operations, as shown in Figure 47, when an expansion device is connected to a base device, the base device automatically recognizes the connection of the expansion device and connects the expansion device to the busbar M The communication processing block 204 comprises: a control register 204a; a parity register 204b; a frame controller 204c; an online monitor 204d; a frame encoder 204e; an alternate shift register P / S 204f; a temporary record 204g; a frame decoder 204h; an alternate shift register S / P 204i; a transmit / receive buffer 204j; and a data length register 204k. The control register 204a is a register for storing several flags, etc., to control the transmission and reception of data. These various flags are described below with reference to Table 26. The parity register 204b is a table buffer for calculating parity and calculations related to serial / parallel and parallel / serial conversion. The transmit and receive buffer 204j is a register for storing data used in the transmission and reception of data. The frame controller 204c controls the transmission and reception of frames by checking the various flags in the control register 204a. In addition, it also sets relevant flags in the control register 204a in response to the detection of a start pattern, an end pattern, an occupancy pattern SDCKB, a restart pattern, or the like. The frame encoder 204e generates frames by attaching sections from pattern to data. The alternate offset register P / S 204f performs a parallel / serial conversion to convert data parallel to serial data. Online monitor 204d checks the SDCKA and SDCKB signal lines. The data length register 204k is a register that indicates the data size of transmission data when they are transmitted.

The interface with the MIÉ seen from the CPU 201 section of the peripheral device comprises: 21 control flags (CFLAG), a data length register (LREG) 204k, and a transmit and receive buffer with a maximum of 1024 bytes (TRBF) 204j. The capacity of the transmission and reception buffer is optimized to adapt the device. Here, the interface between a MIÉ controller (CPU 201) and a base device MIÉ (receptacle control 203, transmission processor 204) according to the above composition will be described. The frame data transmitted from the host via the data lines SDCKA and SDCKB are received by the frame decoder 204h. The frame decoder 204h demodulates the frame data of the SDCKA and SDCKB signals and separates the pattern section and the data sections from the frame data. When the frame decoder 204h detects pattern sections, such as a start pattern, an end pattern, an occupancy pattern SDCKB, a restart pattern or the like, transfers the information detected in this pattern section to the frame controller 204c. As well as the control of the reception operation, the frame controller 204c also sets flags in the control register corresponding to the detection of the pattern. These flags include: the RXB reception flag; RFB full reception flag; the occupation mode flag SDCKB POS; and the HRES restart pattern reception flag. The separate data sections are transferred to the alternate shift register 204 The shift register 204i has a serial / parallel data conversion function, and converts the separated serial data signals to parallel data, which is sent to a register temporary 204g. The temporary register 204g performs a parity verification calculation for the received data. It also extracts the parity bit section from the received data and stores it in a parity register 204b.

The parity check result is compared with the parity bits in the parity register 204b, and if an error is detected, a parity error flag PERR is set in the control register 204a. The verified error data is then stored in the transmit and receive buffer 204j. If the reception data volume exceeds the capacity of the transmit and receive buffer 204j, then a BFOV buffer overflow flag is set in the control register 204a. The overflow data is not stored in the transmit and receive buffer 204j. When the reception is complete, an RFB reception completion flag is set in the control register 204a. The CPU 201 checks the contents of the control register 204a, and reads the reception data stored in the transmit and receive buffer 204j in response to the RFB reception completion flag. When the CPU 201 transmits data, the transmission data is stored in the transmission and reception buffer, and the transmission data volume is written to the data length register 204k. The CPU 201 sets the transmission flag TXB and the end pattern transmission flag ENP (if there is no subsequent transmission data) in the control register 204a. The transmission data in the transmit and receive buffer 204j are sent to the temporary register 204g, when a parity calculation is performed. The temporary register 204g stores the parity calculation result as a bit of parity bits, which is appended to the end of the transmission data. The transmission data is then supplied from the temporary register 204g to the alternate shift register 204f, where they are converted to serial data and then supplied to the frame encoder 204e. The frame encoder 204e creates a transmission frame by appending a start pattern and an end pattern respectively to the start and end of the transmission data and the parity data. The frame controller 204c opens the buffers of three respective states 211 a and 211 b through the gates OR 213 a and 213 b. The transmission frame encoded by the frame encoder 204e to the SDCKA signal and the SDCKB signal. The SDCKA signal and the SDCKB signal are respectively output to the bus data lines M SDCKA and SDCKB. The online monitor 204d continuously checks the SDCKA data line and the SDCKB data line. The results of this (whether or not there is a signal) are set in the control register 204a as an SDCKA online monitor flag and an online SDCKB monitor flag. The CPU 201 is able to investigate interruption for the data transmitted by the host by referring to these flags. As shown in Figure 62, the expansion device MIÉ is similarly composed to the base device MIÉ, but does not comprise a receptacle control section. The support function section in this diagram corresponds to the input means and the I / O section in the base device, and performs the characteristic functions of, for example, an LCD screen a sound output cartridge, a cartridge of sound input, a light gun cartridge, a vibration cartridge, a memory cartridge, and the like. The CPU section 301 and the communication processing section 304 correspond respectively to the CPU section 201 of the device and the communications processing section 204. Now, the composition of the control register 204a, the data length register will be described. 204k and the transmission and reception buffer (TRBF) provided in the MIÉ of a base device (or expansion device). Table 26 shows the composition of a control register 204a that contains several control flags (CFLAG). These control flags comprise 21 flags to control the transmission and reception of data. The types of flag used to make this record differ according to the type of peripheral device. Table 26 Composition of CFLAG Dir R ?? R? / V R? / V R? / V R ?? R / V R ?? R? / V R ?? R / V R / V Data HRE CTXB TFB TXB BFOV RFB END LMC1 LMC2 LMC3 LMC4 S P ¡ni 0 0 0 0 0 0 0 0 0 0 0 Dir R R R R R R R R R Data RXB EMP SDAM SDBM PERR POS LMM1 LMM2 LMM3 LMM4 Ini 0 0 _ _ 0 0 - - - - In this box, R? V indicate that the flag can be read and written. R indicates that the flag is read only. "Ini" represents the initial fixation. HRES represents a reset pattern receiving flag. The HRES restart pattern reception flag becomes "1" when a restart pattern is received, and accelerates the initialization of the MIÉ control. TXB is a transmission flag. If TXB is written during transmission or reception, the contents of the corresponding data are not guaranteed. CTXB is a continuous transmission flag. If a volume of data is transmitted in excess of the capacity of the transmit and receive buffer 204j, then after storing the continuation of the data in the transmit and receive buffer 204j, this data is transmitted with the transmission flag CTXB continues, instead of the TXB transmission flag. TFB is a transmission completion flag. BFOV is an overflow buffer of transmission and reception buffer memory. The BFOV overflow flag is cleared when reception or transmission starts. When the transmit and receive buffer 204j produces an overflow, the BFOV overflow flag is set to "1". RFV is a reception completion flag. ENDP is an end pattern transmission flag. When an end pattern is appended to the transmission data, ENDP is set to "1". RXB is a reception flag, which changes when the data is received. EMP is a vacuum flag. If the data transmitted to the transmission and reception buffer 204j during transmission disappears (is empty), then the EMP empty flag is set to "1". PERR is a parity error flag. When the parity in the frame received does not match, this PERR parity error flag is set to "1", and under normal conditions, it is cleared to "0". POS is an SDCKB occupation mode flag. The occupation mode flag SDCKB POS indicates whether the busbar M is in the normal mode or the occupancy mode SDCKB (POS = "0") or the occupancy mode SDCKB (POS = "1"). SDAM is an SDCKA online monitor flag (only provided on the base device). SDBM is an SDCKB online monitor flag (only provided on the base device). SDAM and SDBM indicate the status of the data lines SDCKA and SDCKB, respectively. LMC1 - 4 are connection flags for busbars LM 1-4 (provided only in the base device). Flags LMC1 - 4 indicate a connection (= "1") or disconnection (= "0") in busbars LM 1-4. LMM1 - 4 are the connection monitor flags of the LM 1-4 busbar (provided only in the base device) these LMM1 - 4 flags indicate the usage status of the LM 1-4 busbars. The MIÉ controller investigates a host data interruption by checking the SDAM and SDBM flags. The processing of the interruption is conducted only by the base devices and not by the expansion devices.

Data length record (LREG) Table 27 shows the composition of the data length record. The data record is an individual bit register to indicate the size of an individual frame during transmission.

(Picture 27) Composition of LREG Bit 7 6 5 4 3 2 1 0 Dir R ?? R ?? 7 R / W R / W R ?? / R ?? / R ?? / R / W Data Ln7 Ln6 Ln5 Ln4 Ln3 Ln2 Ln, Ln0 Ini - - - - - - - In this box, R ?? indicates that a bit can be read as well as written. In this initial state, all the bits are undefined. Ln represents the data length, where OOh < Ln < FFh. The relationship between the value of Ln and the length of data is illustrated in Table 28.

(Table 28) Data Length Bit 7 6 5 4 3 2 1 0 Data Length Ln7 Ln6 Ln5 Ln4 Ln3 Ln2 Ln, Ln0 4Bytes 0 0 0 0 0 0 0 0 8Byt.es 0 0 0 0 0 0 0 1 512Bytes 0 1 1 1 1 1 1 1 516Byt.es 1 0 0 0 0 0 0 0 1020Bytes 1 1 1 1 1 1 1 0 1024Bytes 1 1 1 1 1 1 1 1 During the transmission and reception of data and after the reception of data, the data length record (LREG) is undefined. The data length can be specified in units of four bits. Now, the data buffer will be described. The aforementioned transmission and reception buffer (TRBF) 204j is used as the data buffer. The transmit and receive buffer 204j is a buffer region, wherein a transmission data frame and receive data are stored. The capacity is from a minimum of 4 bits to a maximum of 1024 bits, in units of 4 bits. The capacity is optimized for each peripheral device. The buffer is shared for transmission and reception, and regions are divided for a command code, destination AP, source AP, data size and data. • Table 29 shows the composition of the transmission and reception buffer. In this box R ?? / indicates that a bit can be read and written. In the initial state, the contents of the buffer are undefined. The data is transmitted in sequence starting from the first, and the received data is written to the buffer in sequence starting from the first data storage region. The sections of 1st data - 40s data are regions where the data will be stored and specified. (Table 29) Composition of TRBF Bit 7 6 5 4 3 2 1 0 Dir R ?? / R ?? / R ?? R ?? / R ?? / R ?? R ?? / R ?? / 1st Data D17 D16 D15 D14 D13 D12 D1, D10 2nd Data D27 D26 D2S D24 D23 D22 D2, D20 3rd Data D37 D36 D3S D34 D33 D32 D3, D30 4th Data D47 D46 D 5 D44 D43 D42 D4, D40 5th Data D57 D56 D55 D54 D53 D56 D5, D50 6th Data D67 D66 D65 D64 D63 D62 D6, D60 7 ° Data D77 D76 D75 D74 D73 D72 D71 D70 8th Data D87 D86 D85 D84 D83 D82 D8, D80 In this box, the first data section (1st data) is a region for storing command codes. The second data section (2nd data) is a region for storing target AP values. The third data section (3rd data) is a region for storing source AP values. The fourth data section (4th data) is a region for storing the data size. When the value in the fourth data values D40-D47 is "OOh", this indicates that no data exists. The fifth data section (5th data) are regions for storing parameter data. The number of bits of data stored is the number of bits indicated by the data size. The contents of the data regions beyond the data size are undefined. -Procedure of data transfer between the MIÉ and the base device MIÉ. The reception of data and the transmission of data through the host MIÉ and the base device MIÉ having the above compositions will now be described.

Since a similar data transfer procedure is used in expansion devices, no description is given here of the data transmission procedure between the host IME and the expansion device IME. Procedure for receiving data First, a summary of a data reception in a base device will be described. The data reception is done automatically through the respective MIEs of the host and the base device. When the host transmits a data signal and the base device initiates the reception process, the TXB transmission flag, the TFB transmission completion flag and the RFB reception completion flag are all cleared to "0" through the MIÉ. When the RXB reception flag is "1" this indicates that the MIÉ is in the process of receiving data, and when RXB is "0", this indicates that the reception has finished. When the data reception is completed normally and the data is stored in the transmission and reception buffer (TRBF), while the parity error status is stored by the parity error flag PERR, the reception completion flag RFB is set to "1" (in the case of interrupt processing, a reception interrupt is generated at this point), and the reception process. If the reception flag RXB and the reception termination flag RFB are both "1", then this indicates that an error has occurred during reception. In addition, if the reception data exceeds the capacity of the transmit and receive buffer, then the BFOV transmission and reception buffer overflow flag is set to "1", and the reception data of the reception start up the capacity of the transmission and reception buffer are stored in the transmission and reception buffer. If there is a parity error in the frame data, then PERR is set to "1", and if the parity is normal, then PERR is cleared to "0". Figure 67 is a diagram illustrating the reception of data in the device MIÉ, in a case where the volume of data transmitted from the host to the device (peripheral device) does not exceed the capacity of the transmit and receive buffer 204j. First, on the host side, the transmission data that will be sent is created in the work RAM 1e, and the host MIÉ forms the frame data containing this data and begins to transmit them to the busbar M. The MIÉ The device receives this frame data and decodes it through a decoder 204h.

The data section (data pattern) and the parity data in the frame data are converted into series to parallels through an alternating displacement register 204¡, and the parity is verified (parity calculation) through the register temporary 204g. The verified data section is then stored in a transmit and receive buffer 204k, and the parity data is stored in a parity register 204b. When the frame decoder 204h detects a pattern in the frame data, the frame controller 204c cleans the transmission flag TXB, the transmission termination flag TFB, and the reception completion flag RFB in the control register 204a in "0" As previously stated, when the RXB reception flag is "1", it indicates that the MIÉ is in the process of receiving data and when RXB is "0", this indicates that the data reception has finished. The CPU section 201 reads the fact that the reception flag RXB is set to "1", and concludes that the data has been received. In addition, the CPU 201 section is also capable of verifying the use of the SDCKA and SDCKB data lines by checking the SDAM and SDBM flags. When the frame decoder 204h detects a final pattern in the frame data, the frame controller 204 concludes that the data reception has ended and sets the reception flag RXB to "0". The parity register section 204b compares the parity check results for the reception data with the parity data received, to determine if there is a parity error. The occurrence or absence of an error is written to the PERR parity error flag in the control register 204a. When the reception of frame data is normally completed, and the data is stored in the transmit and receive buffer 204j, while the parity error state is stored in the parity error flag PERR of the control register 204a, the RFB reception completion flag is set to "1" and the reception process ends. The receive termination flag RFB can be taken as an interrupt signal in the CPU section 201. Verifying the RFB reception completion flag periodically or alternately, receiving an interrupt signal when the reception completion flag is set to " 1", the CPU section 201 executes a program for processing the reception data. First, it confirms that the parity error flag PERR in the control register 204a is not indicating that an error exists. Then, it reads in the reception data of the transmit and receive buffer 204j to the main memory in the CPU section 201. The CPU section 201 then implements the processing corresponding to the commands and parameters transmitted by the host, and process to create response data, and the like. If both the RXB reception flag and the RFB reception completion flag are set to "1", then since these are essentially incompatible states, the CPU identifies that an error has occurred during reception, and implements the relevant processing. In addition, if the PERR parity error flag indicates that an error exists, the CPU section 201 performs processing to send a retransmission request command to the host, for example. Figure 68 is a diagram illustrating the reception of data in a base device MIÉ in a case where the transmission data volume from the host to the base device (peripheral device) exceeds the capacity of the transmission buffer and reception TRBF. When the reception data exceeds the capacity of the transmission and reception buffer 204j, in the overflow flag of the transmission and reception buffer BFOV is set to "1", and the reception data from the beginning of reception to the capacity of the transmission and reception buffer are stored in the transmission and reception buffer. Now the operations implemented in this case will be described.

First, similar to Figure 67, the transmission data that will be sent by the host are created in the work RAM 1e, and the host MIÉ forms the frame data containing this data and begins to transmit them to the bus M. The MIÉ in the base device receives this frame data and decodes it through a frame decoder 204h. The data section (data pattern) and the parity data in the frame data are converted from serial to parallel through the alternating shift register 204i, and a parity check (parity calculation) is performed by the register temporary 204g. The data section is then stored in the transmit and receive buffer 204j, and the parity data is stored in the parity register 204b. When the frame decoder 204h detects a start pattern in the frame data, the frame controller 204c cleans the transmission flag TXB, the transmission termination flag TFB and the reception completion flag RFB in the control register 204a in "0". As previously stated, when the reception flag RXB is "1", it indicates that the MIÉ is in the process of receiving data, and when RXB is "0", it indicates that the transmission has finished. The CPU section 201 reads the fact that the reception flag RXB is set to "1", and concludes that the data is being received. In addition, the CPU section 201 is able to verify the use of the SDCKA and SDCKB data lines by checking the SDAM and SDBM flags. If the reception data exceeds the capacity of the transmit and receive buffer 204j, then the transmit and receive buffer 204j sets the overflow flag of transmit and receive buffer BFOV in the control register to "1". For this purpose, an overflow is detected, for example, by generating a detection output when an address counter in the transmit and receive buffer 204j reaches the maximum address value in the memory. Even after the reception data volume has exceeded the transmission and reception buffer 204j, the reception data is still supplied to the transmission and reception buffer 204j through the temporary register, but the transmission buffer and Reception does not read in this data. In this way, only one parity calculation is implemented for all the data. The parity data section of the reception data is stored in the parity register. When the frame decoder 204h detects an end pattern in the frame data, the frame controller 204c identifies that the reception has ended and sets the reception flag RXB to "0". The parity register section 204b compares the parity check results for the reception data with the parity data received, to determine if there is a parity error. The occurrence or absence of the error is written to the parity error flag PERR in the control register 204a. When the data is set in the transmit and receive buffer 204j and the parity error state is set in the PERR parity error flag of the control register 204a, the RFB receive termination flag is set to "1" and the reception process ends. The reception termination flag RFB can be taken as an interrupt signal for the CPU section 201. The CPU section 201 identifies that a program must be implemented to process the reception data by periodically checking the RFB reception completion flag of the register control, or receiving an interrupt signal when the RFB receive termination flag is set to "1". In addition, the CPU section 201 confirms that the parity error flag PERR in the control register 204a does not indicate that an error exists. It also verifies that the BFOV transmission and reception buffer overflow flag is set to "1". After identifying that the data is halfway through the transmission, the CPU section 201 reads in the receive data from the transmit and receive buffer 204j to the main memory of the CPU section 201, and then implements the relevant processing. Data transmission method Now a method of transmitting data from a base device to the host will be described with reference to Figure 69. The method of transmitting data from the expansion device to the host is similar to the procedure for transmitting data from the base device to the host, so it will not be described here. When the base device receives a command from the host, it creates response data in order to respond to the command, and sends this response data to the host. As previously stated, if there is no response in a predetermined period (for example, 1.Oms) after the transmission of the command, the host concludes that there is no connection. Therefore, the base device must send back a command within this period. First, the CPU section 201 of the base device writes the transmission data (commands, parameters) to the transmit and receive buffer 204j. Then, it writes the data volume of the transmission data to the data length register 204k and sets the end pattern flag ENDP in the control register to 1. When the CPU section 201 sets the transmission flag TXB in the control register 204a to "1", the MIÉ starts a transmission operation in order to transmit the data of the size indicated by the data length register. If the transmission flag TXB is set to "1", then the reception flag RXB, the reception termination flag RFB, the transmission termination flag TFB and the overflow flag of transmission and reception buffer BFOV in the 204a control register are all set (cleaned) to "0". If the data volume group in the data length register 204k exceeds the capacity of the transmit and receive buffer 240j, the BFOV transmission and reception buffer overflow flag is connected to "1", and all the data in the transmission and reception buffer 204j are transmitted. The frame controller 204c allows the transmission of the data stored in the transmit and receive buffer 204j in response to the transmission flag TXB which is being set to "1". The temporary register 204g performs a parity calculation for the transmission data, and the data is then converted from parallel to serial through the alternating shift register 204f and transmitted to the frame encoder 204e. The parity data are appended to the end of the transmission data through the temporary register 204g. The frame encoder 204e transmits in sequence a start pattern, transmission data (commands, parameters), parity data and end pattern, under the control of frame controller 204c. The transmission frame constituted by these data items is sent to the busbar M through the signal SDCKA and the signal SDCKB mentioned above. When the final data item is taken out of the transmission and reception buffer 204j, the transmission flag TXB in the record control is set to "0", the EMP empty flag is set to "1", and the flag Continuous transmission is set to "0". The contents of the transmission and reception buffer 204j after the transmission has been completed are undefined. The frame controller 204c transmits an end pattern and if the data transmission is completed normally, the TFB transmission completion flag in the control register 204a is set to "1". The MIÉ of the base device then assumes a quiescent state waiting for an entry of the busbar M. The CPU section 201 confirms that the transmission is complete by checking the TFB transmission completion flag in the register control 204a periodically to see if it was fixed at "1". Further, if the transmission flag TXB indicating that the transmission is in progress and the transmission termination flag TFB both are "1", then the CPU section 201 identifies that an error has occurred. The host IME, on the other hand, receives the frame data transmitted by the base device. When the frame decoder 61 detects the start pattern in the data, a signal is sent through the interrupt control section 54 to the interrupt controller in the host CPU 1a, to notify the CPU that the data is being received. The reception data is converted from serial to parallel through the alternating shift register 62, whereby they are transmitted from the initiator section 50 through the reception data temporary register 56a and the reception data FIFO. 56b to work RAM 1e. In the storage location of receiving data in the work RAM 1e, the reception data storage address predetermined by the CPU 1a is taken as the previous bit position. When the frame decoder 61 detects an end pattern, reception purposes, and the interrupt signal control section 54 sends a signal indicating the completion of the reception process to the interrupt controller. In this way, the CPU is notified that the reception has finished, and is able to access and process the reception data in the work RAM 1e. -Now, referring to Figure 70, the data transmission will be described in a case where the transmission data of the base device exceeds the capacity of its transmit and receive buffer204j. In an expansion device, a procedure similar to that in a base device is implemented. If the transmission data exceeds the capacity of the transmit and receive buffer 204j, the CPU section 201 in the base device is able to transmit the data by dividing them into a number of blocks according to the buffer capacity of the device. transmission and reception 204j.

If the CPU section 201 in the base device receives a command from the host, it forms response data in order to respond to this, and sends this data to the host. If there is no response within a predetermined period (for example, 1.0 ms), after the transmission of the command, the guest concludes that there is no connection. Therefore, the base device must send back a command and parameters within this period. First, the CPU section 201 of the base device compares the volume of data to be transmitted with the capacity of the transmit and receive buffer 204j to identify whether the transmission data volume is large. The CPU section 201 then divides the transmission data into lengths equal to or less than the capacity of the transmit and receive buffer 204j (e.g., 1024 bits) and writes the data into the transmit and receive buffer 204j (blocking of data) After, the data volume of the transmission data stored in the transmit and receive buffer 204j are written to the data length register 204k, and the END pattern flag ENDP in the control register 204a is set to "0". " When the CPU section 201 sets the transmission flag TXB in the control register 204a to "1" (transmission mode), the MIÉ starts a transmission operation in order to transmit data of the size indicated by data length registration . When the transmission flag TXB is set to "1", the frame controller 204c sets (cleans) the reception flag RXB, the reception completion flag RFB, the transmission completion flag TFB, the vacuum flag EMP and the overflow flag of transmit and receive buffer BFOV in register control 204 to "0".

The frame controller 204c allows the transmission data stored in the transmit and receive buffer 204j to be transmitted in response to the transmission flag TXB which is set to "1". A parity calculation is made for the transmission data in the temporary register 204g, and the data is then converted from parallel to serial through the alternate shift register 204f and transmitted to a frame encoder 204e. The frame encoder 204e transmits the start pattern and transmission data (command and parameters) successively, according to the commands of the frame controller 204c. Since the ENDP flag is set to "0", the parity data and an end pattern are not appended to the end of this data block. A transmission frame comprising the aforementioned data is transmitted to the bus bar M via the signal SDCKA and the signal SDCKB. When the final data item is taken out of the transmission and reception buffer 204j, the vacuum flag EMP in the control register is set to "1" and the continuous transmission flag is set to "0". The CPU section 201 checks the vacuum flag EPM in the control register 204a periodically. If you confirm that the EMP empty flag has been changed to "1", divide the continuation of the transmission data to a size equal to or less than the capacity of the transmit and receive buffer and store them in the transmission buffer and reception 204j. The length of this data is set in the data length register 204k. Then, the CPU section 201 sets the DC transmission flag CTXB in the control register 204a to "1". When the CTXB continuous transmission flag is set to "1", the frame controller 204c sets (cleans) the EMP vacuum flag and the BFOV transmission and reception buffer overflow flag in the register control 204a at "0" " The frame controller 204c allows the transmission data stored in the transmit and receive buffer 204j to be transmitted in response to the transmission flag TXB which is set to "1". A parity calculation is made for the transmission data in the temporary register 204g, and the data is then converted from parallel to serial through the alternating shift register 204f and sent to the frame encoder 204e. The frame encoder 204e transmits the transmission data (commands, parameters) successively, under the control of the frame controller 204c. These data items, and the like, are transmitted to the busbar M via the signal SDCKA and the signal SDCKB. When the final data is taken out of the transmission and reception buffer 204j, the EMP empty flag in the control register is set to "1" and the CTXB continuous transmission flag is set to "0". The CPU section 201 identifies that the vacuum EMP banner has been switched to "1" by checking the control register at periodic intervals. The CPU section 201 divides the remaining (not transmitted) transmission data to a size equal to or less than the capacity of the transmit and receive buffer 204j and stores them in the transmit and receive buffer 204j. In the case of this example, the remaining data is smaller than the capacity of the transmit and receive buffer 204j, so that all the remaining data is stored in the transmit and receive buffer 204j. The length of this data is set in the data length register 204k. In addition, since the final data block is being transmitted, the end pattern transmission flag ENDP is set to "1", so that an end pattern is appended to the end of the data. Then, the CPU section 201 sets the DC transmission flag CTXB in the control register 204a, at "1". When the CTXB continuous transmission flag is set to "1" the frame controller 204c sets (cleans) the EMP empty flag and the BFOV transmission and reception buffer overflow flag in the register control 204, at "0" " The frame controller 204c allows the transmission data stored in the transmit and receive buffer 204j to be transmitted in response to the transmission flag TXB which is set to "1". A parity calculation is made for the transmission data in the temporary register 204g, and the data is then converted from parallel to serial through the alternating shift register 204f and sent to the frame encoder 204e. The temporary register 204g takes the results of the parity calculation for all transmission data as parity data (a bit of parity bits), which are sent to the end of the transmission data. The frame encoder 204e transmits the transmission data (commands, parameters), parity data, and an end pattern, successively, under the control of the frame controller 204c. These data items, and the like, are transmitted to the busbar M through the signal SDCKA and the signal SDCKB. When the final data item is taken out of the transmission and reception buffer 204j, the EMP empty flag in the control register is set to "1" and the CTXB continuous transmission flag is set to "0". Since the transmission has finished, the transmission flag TXB and the transmission termination flag TFB both are set to "0". The CPU section 201 identifies that the transmission of all the data has been completed from the state of the various flags, checking the control register 204a periodically. The host MIÉ, on the other hand, initiates a reception operation when it receives a start pattern, and stores the reception data (commands, parameters) successively in the work RAM 1e. The storage location in work RAM 1e is previously specified by the DMA registry. The original transmission data is retrieved by linking together each of the data blocks received in the work RAM 1e. When the host IME finally receives an end pattern, it ends the data reception.

As described above, when the transmission data is split and transmitted as blocks the initial block uses the transmission flag TXB, and the second block and the subsequent blocks use the continuous transmission flag CTXB to transmit the remaining data. If the period of sending a block of data to send the next block of data exceeds a prescribed time, for example 1.0 ms, then an interruption will be generated in the host, so that the device transmits the second block and the subsequent blocks within of this period. The size of the blocks can be set in block units. The block size is set in the data length register 204k for each block transmission. With the exception of the final block, the end pattern flag is set to "0" when the block is transmitted so that no end pattern is appended. When the final block is sent, the end pattern flag is set to "1", so that an end pattern is appended to the end of the transmission data. In this way, the base device can transmit data that exceeds the capacity of its own transmit and receive buffer. The same applies to expansion devices. Relationship between flag and communications status The relationships between the flags in the control register 204a of the base device and its communications status will now be described. (1) State of the base device flags (when the base device is communicating with the host) (a) When the base device is transmitting data to the host.

(Table 30) Transmission of Data to the Host Bit Start of In Transmission End of Transmission Error transmission transmission TXB 1 1 0 1 TFB 0 0 1 1 RXB 0 0 0 0 RFB 0 0 0 0 If the transmission flag TXB and the flag of termination TFB are set to "1", this represents a transmission error. (b) When the base device is receiving data from the host.

(Table 31) Host Data Reception Bit At reception End reception Receive data Error stored reception TTXXBB 00 0 0 0 TFB 0 0 0 0 RXB 1 1 0 1 RFB 0 0 1 1 When both the RXB reception flag and the completion flag RFB are set to "1", this represents a reception error. (2) Status of base device flags (when an expansion device is communicating with the host) (a) When an expansion device is transmitting data to the host.

(Picture 32) States of Individual Flags with Regard to the Transmission State of Another Peripheral Device Start Bit In Transmission End of TXB Transmission Transmission Error 0 0 0 0 TFB 0 0 0 0 RXB 0 0 0 0 RFB 0 0 0 0 If any of the expansion devices (transmission devices) transmit data to the host, it is possible for the expansion device to occupy an LM bus. This occupation is made possible by controlling the OR gates 213, 214 through the transmission device. In cases of this type, base devices and expansion devices other than the transmission device are excluded from the busbar, so that it is not necessary to verify the reception of data, thus reducing the load, consequently. (b) When the expansion device receives data from the host.

(Table 33) States of Individual Flags with Regard to the Transmission State of Another - Peripheral Device Bit In reception End of reception Receiving data Stored error Reception TXB 0 0 0 0 TFB 0 0 0 0 RXB 1 1 0 1 RFB 0 0 1 1 When the reception flag RXB and the reception termination flag RFB both are set to "1", this represents a reception error.

Error processing Error processing will now be described. As previously established, if TXB transmission flag and transmission completion flag TFB are set to "1", then there is a transmission error. If the reception flag RXB and the reception termination flag RFB both are set to "1", then there is a reception error. If an error occurs during transmission processing, the MIÉ may indicate that there is an error by setting both the TXB transmission flag and the TFB transmission termination flag to "1". The same applies if an error occurs during reception processing. If a parity error arises, then the PERR parity error flag is set to "1". If the data received exceeds the capacity of the transmit and receive buffer (overflow) during data reception, or if a data length exceeding the capacity of the buffer is specified during transmission, then the overflow flag of BFOV transmission and reception buffer is set to "1". Now we will describe examples of error processing in a base device in cases where errors of this type occur. (a) If an error occurs when transmitting to the host, no operation is implemented with respect to the error, but rather the transmission flag TXB and the transmission termination flag TFB. (b) If an error occurs when the host data is received, first, if the destination of the data corresponds to that of the base device, then the base device may send a relay command to the host. If the data destination indicates another device, then the base device cleans its own RXB reception flag and the RFB reception completion flag. (c) If the error during reception of host data is an interruption, then both the base device and the expansion devices are rebooted. In other words a) the identifications of the expansion devices are inverted to form interruption operation signals for the expansion devices, thus causing the expansion devices to interrupt the processing, b) the base device is restarted and then reversed its identification (returns it to the original identification). When the identification is reversed, the expansion devices are restarted. c) After reinitialization, the device assumes the same status as after a software restart.

Command Reference Now we will describe the various commands used in a frame. You can use 254 command codes of 01 h - FEh. OOh and FFh can not be used. These codes are inverted to be used to indicate "a communication error: unsafe data". The commands include control commands and error commands.

Control Commands The 01 h - DFh command code scale can be used for control commands. These commands are used to control the transmission and reception of data. The various function libraries in the host, base devices, and expansion devices must not provide different commands for the same command code. If more commands are added, it is desirable to look for compatibility with standards through the application prior to handling parts of the standards. The control commands are described below.

Device request (Figure 71) Right to issue: Host Command code: 01 h Data size: OOh Data region: None Expected response value: Device Status Description: A command for a peripheral device in the target AP that request a device status. Also used to verify the connection status in the ports.

All States Request (Figure 72) Right to Issue: Host Command Code: 02h Data Size: OOh Data Region: None Expected Response Value: All Device States Description: A request to the peripheral device in the AP of destination for all Device States (both Fixed Device Status and Free Device Status).

Device Restart (Figure 73) Issuance: Host Command code: 03h Data size: OOh Data region: none Expected response value: Device Response Description: Permits the initialization of the peripheral device specified by the destination AP. Operation procedure: (1) The device sends back a Device Response. (2) The same peripheral device is reset.

Aniquilatis Positivo (Figure 74) Broadcast: Host Command code: 04h Data size: OOh Region of data: none Expected response value: Device Response Description: Prohibits the operation of the peripheral device specified by the destination AP. The peripheral device then waits on the current consumption at rest and does not accept any command. To operate the peripheral device, it is necessary to either perform a hardware reset or reactivate it by cutting off the power supply. Operational procedure: (1) The peripheral device sends the Device Response. (2) The peripheral device interrupts the operation.

Device Status Emission right: Peripheral device Command code: 05h Data size: 1 Ch (28) Data region: Device identification: 16 bits; Destination region code: 1 bit; Product name: 31 bits; License: 60 bytes; current consumption at rest: 2 bytes; Maximum current consumption: 2 bytes. Description: Fixed Device Status data is sent in response to a request from the host device. The details of the data contents are described in the peripheral device information given below.

All Device States Issuance Right: Peripheral Device Command Code: 06h Data Size: 1 Ch + (n / 4) Data Region: Device Status Fixed: 112 bytes; device identification: 16 bytes; Destination region code: 1 byte; Product name: product name: 31 bytes; License: 60 bytes; Consumption current at rest: 2 bytes; Maximum current consumption: 2 bytes; Free Device Status: n bytes. Description: Both a Fixed Device Status and a State of Free Device are sent in response to All Host State Requests. The details of the data contents are described in the peripheral device information given below.

Device Response Right to Broadcast: Peripheral Device Command Code: 07h Data Size: OOh Data Region: None Description: Used as a response from the peripheral device.

Data Transfer (Figure 75) Right to issue: Peripheral device Command code: 08h Data size: n (01 h <n <FFh) Data region: Function type: 4 bytes; data: (n-1) x 4 bytes Expected response value: none - Description: Send data with respect to the type of function specified by the host. The data varies depending on the requested command.

Obtain Condition (Figure 76) Right of emission: Host Command code: 09h Data size: 01 h Data region: Function type: 4 bytes Expected response value: Data transfer Description: Physical status of requests of the specified function by the type of function of the peripheral device. The peripheral device sends the same type of function type transmitted by the host. Only one type of function can be designated at a time.

Obtain Information from the Medium (Figure 77) Right to broadcast: Host Command code: OAh Data size: 02h Data region: Function type: 4 bytes; PT (division): 4 bytes (of which 3 are simulated bytes) Expected response value: Data Transfer Description: Request media information in the function specified by the peripheral device function type and PT. The details depend on the specifications of the respective function types.

Read Block (Figure 78) Right to send: Host Command code: OBh Data size: 02h Data region: Function type: 4 bytes; Division (PT): 1 byte; Phase: 1 byte; Block number: 2 bytes. Expected Response Value: Data Transfer Description: Request data in locations specified by the peripheral device function type and the division of the storage medium, phase and block number (for example, data storage location in FDD) , HDD, memory, CD-ROM, etc.). The details depend on the specifications of the respective function types.

Write Block (Figure 79) Right of emission: Host Command code: OCh Data size: 02h + n Region of data: Type of function: 4 bytes; division: 1 byte; Phase: 1 byte; Block number: 2 bytes; Write data: n x 4 bytes. Expected response value: Device Response Description: Write data in a location specified by the peripheral device function type, and the division, phase and block number. The details depend on the specifications of the respective function types.

Get Ultimate Error (Figure 80) Right to broadcast: Host Command code: ODh Data size: 02h Data region: Function type: 4 bytes; division: 1 byte; Phase: 1 byte; Block number: 2 bytes. Expected response value: Device Response • Description: Investigate if the error occurred in the immediately preceding command. If there is no error, a device response is sent back, and if there is an error, an error command is sent. The division and the block number retain the same values as in the immediately preceding command, and the phase is increased by 1. The details depend on the specifications of the respective function types.

Error Command Now the error commands will be described. The EOh - FEh command code scale is used for error commands. An error command reports that an error has occurred in the reception and transmission of data or processing. It is prohibited for the respective function libraries in the host, the base devices and the expansion devices to provide different commands for the same command code. It is desirable for compatibility with the standards that will be sought through the previous application for handling parts of the standards. Now the error commands will be described.

Function Type Unknown Issuance right: Peripheral device Command code: FEh Data size: OOh Data region: none Description: Issued when the function specified by the type of function transmitted is not present in the peripheral device. Conceivable causes: (1) The function type specification is incorrect. (2) The description of the data is incorrect. (3) The device identification data is corrupt. (4) Corrupt data during communications. Action: (1) Correct function type specification. (2) Correct description of data. (3) Transmit the device request again and obtain the device identification. (4) Try to transmit again (up to a maximum of three times, so the same processing is set to interrupt).

Command Unknown Broadcast: Peripheral device Command code: FDh Data size: OOh Region of data: none Description: Issued when the transmitted command is not provided in the functions on the peripheral device side. Conceivable causes: (1) Incorrect command specification. (2) Correct data description. (3) Corrupt device identification data. (4) Corrupt data during communications. Action: (1) Correct command specification. (2) Correct description of data. (3) Transmit the device request again and obtain device identification. (4) Try to transmit again (up to three times, so the same interrupt processing is presented) Transmit New Issuance Right: Host; peripheral device Command code: FCh Data size: OOh Region of data: none Description: Requests that the same data be transmitted again, when an error of some kind occurs in the transmission data. Conceivable causes: (1) Parity error occurs. (2) Data overflow. (3) Corrupt data during communications. Action: Transmit again (up to three times, so the same interrupt processing is presented).

File error Issuance right: Peripheral device Command code: FBh Data size: 01 h Data region: Function error code Description: Issued when an error occurs in the File Function. A detailed error is transmitted through the function error code.

Conceivable causes: (Table 34) File Function Error Code Bit 1st Data FE31 FE8 FE29 FE28 FE27 FE26 FE25 FE24 2nd Data FE23 FE ,, FE21 FE20 FE19 FE18 FE17 FE16 3rd Data FE15 FE, 4 FE13 FE12 FE "FE10 FE9 FE8 4th Data FE7 FE6 FE5 FE4 FE3 FE2 FE, FE0 In this table, an article that has produced an error is set to "1", and an article that does not produce an error is set to "0". FE0, represents a division error (PT error); FE. ,, a phase error; FF ^, a block error; F? , a writing error; F? , a length error; FE5, a CRC error. Afterwards, these bits are reserved.

LCD error Issuance right: Peripheral device Command code: Fah Data size: 01 h Data region: Function error code Description: Issued when an error occurs in the LCD function. A detailed error is transmitted through the function error code. Conceivable causes: (Table 35) LCD Function Error Code Bit 7 6 5 4 3 2 1 0 1st Data FE31 FE30 FE29 FE28 FE27 FE26 FE25 FE24 20S Data FE23 FE ,, FE21 FE20 FE19 FE18 FE17 FE16 3rd - Data FE15 FE14 FE13 FE12 FE "FE10 FE9 FE8 4, os Data F 7 FE6 FE5 FE4 FE3 FE2 FE, FE0 In this box, an article that has produced an error is set to "1", and an article that does not produce an error is set to "0". FE0 represents a division error (PT error); FE,, a phase error; FE ^, a block error; FE, a writing error; F? , a length error; FE5, none. Afterwards, the bits are reserved.

Peripheral Device Information The inherent information (Device Status) relative to a base device or an expansion device will now be described. The data in the device state is stored so that it can not be overwritten or deleted. The Device State comprises: Fixed Device Status and Free Device Status.

The Fixed Device Status is a default Device State having a 112 bit format, which must always be defined. Unless all the items in it are defined, the operation and connection can not be guaranteed. The Free Device State is a Device State, which can be used freely by individual devices. It has a maximum capacity of 912 bits.

Fixed Device Status All the following items must be defined in the Fixed Device Status. (1) Device Identification Volume: 16 bits • Description: Indicates the attributes of the peripheral device and the data format (function). There is information regarding the identification of the device in the protocol section. (2) Region of destination Volume: 1 bit Description: Indicates the destination of the product (sales region). Table 36 shows the composition of the destination region setting bits. Table 37 shows the relationship between the destination region setting bits and the destination regions. (Picture 36) Formation of fixing bits for the target region Bit 7 6 5 4 3 2 1 0 Data DES7 DES "DES, DES ,, DES, DES, DES, DESn (Table 37) Bits of fixation for the destinations Reg? 8ߧáJft §áinos Bi > j ion For example, in the case of a common global destination DES = "11111111" = FFh, and the case of a common destination of Japan and Asia, DES = "00000110" = 06h. It is forbidden to DES to be set at OOh. (3) Product Name Volume: 31 bits Description: Give the product name in English or Roman Alphabet. You can use the size Em or in. The space codes (20h) are inserted in the available volume. This product name is previously registered. (4) License Volume: 60 bits Description: Description of ASCII code of the product license in English or Roman Alphabet. The available codes (20h) are inserted into the available bits. For example, "Produced by or Under the License of XXXXX, LTD.". (5) Current consumption at rest Volume: 2 bits Description: Current consumption of states during the temporary interruption in units of 0.1 mA, hexadecimal notification. For example, if the value is 10.5 mA, then the data is 00-69h. (6) Maximum current consumption Volume: 2 bits Description: Describes maximum current consumption of units in 0.1 mA, in hexadecimal notification. For example, if the value is 127.9 mA, the data is 04-FFh.

Free Device Status The Free Device Status is a region that can be freely written by the product planner, developed designer, programmer, or the like, and can be retrieved by the host through a request from all devices. When using application software, etc., it is necessary to match the data configuration, and the like. Other examples of base devices and expansion devices using the present invention will now be described with reference to the drawings. Figure 81 presents an approximate illustration of a compositional example of an additional base device (controller) in relation to the first implementation mode, which uses relative addresses. In the compositional example of a device function U illustrated in Figure 33, where a relative steering system is used, the absence or presence of an expansion device connection is judged by the SDCKA OUT terminal (connected to a resistor). , but in the example hereof, an ID2 terminal connected to the resistor R is provided in each expansion connector, similar to the example of Figure 64, and the presence or absence of an expansion receptacle connection is judged by identifying the voltage generated in this terminal. In Figure 81, the control circuit of a base device (game controller) 2 can be constituted through a so-called single chip microcomputer system 200. The computer system 200 comprises: a CPU 201 a to control each section; a ROM 201b for storing control programs and data libraries for the CPU 201a; a RAM 201c used to store CPU and data programs and implement data processing; and a I / O section 202a for converting compression operations in 11 digital switches 206 to code data; an A / D converter 202b for converting the variable level outputs of four analog switches 207 to a data signal; and a base device MIE 205 for conducting data communications between the base device and the host and supporting data communications between an expansion device and the host. In addition, the computer system 200 comprises: a reset signal generation circuit, comprising resistors, capacitors and diodes, to generate a restart signal when the power is turned on; a crystal oscillator to generate several clock signals for the system; and a voltage conversion circuit to generate a signal voltage of 3.3V for the MIÉ 205 of the base device and for the expansion devices from a power supply Vcc (+ 5V). The power supply Vcc (+ 5V) to the base device is supplied through the game device via an external connection cable. The external connection cable comprises the SDCKA signal line, the SDCKB signal line, the Vcc power supply line, and the GND ground line. The power supply Vcc (+ 5V) supplied from the game device through the external connection cable is fed to the expansion devices (omitted in the drawings) together with the aforementioned signal power supply (+ 3.3V) through the expansion connector. The CPU section 201a, ROM 201b and RAM 201c correspond to the CPU in Figure 33, the A / D converter 202b and the I / O section 202a correspond to / O in Figure 33, and the base device MIÉ 205 corresponds to the communication processing section, the receptacle control section and the gates in Figure 33. The power supply Vcc and the ground GND are supplied to the base device 2 from the host through an M bus. , data communications are conducted through the signal lines SDCKA and SDCKB. The base device and the expansion device are connected through: signal lines SDCKA-US-1, SDCKA-DS-1, SDCKA-EN-1, SDCKB-US-1, SDCKB-DS-1, SDCKB- EN-1, SDCKA-US-2, SDCKA-DS-2, SDCKA-EN-2, SDCKB-US-2. SDCKB-DS-2, SDCKB-EN-2, power supply Vcc (+ 5V, 3.3V) and ground lines GND (four lines). In this example, a base device having two expansion connectors has been described, but as previously stated, it is possible to provide four external expansion connectors. In this case, four terminals ID2, ID2-1 - ID2-4 are used to confirm whether or not a terminal device is connected. The operation of the base device 2 is equal to the function of the device U illustrated in Figure 33, and therefore its description is omitted. Figure 82 shows a further compositional example of a base device (controller) in relation to a second implementation mode using absolute addresses, and corresponds to the example of Figure 81, which uses relative addresses. In this diagram, the sections that correspond to Figure 65 or Figure 81 are similarly marked and are not described here. In a base device employing an absolute address system, the I / O block 202a indicates a busbar number LM to an expansion device connected through terminals IDO and ID1 of any of the expansion receptacles, in accordance with a CPU output. The role of terminals IDO, ID1 was described in the AP fixation method of the expansion device in relation to Figure 59. From I / O 202a, terminals ID0-1 and ID1-1 are provided in the first expansion receptacle and the terminals IDO-2 and ID1-2 are provided in the second expansion receptacle. Figure 83 and Figure 84 show examples of an expansion device provided with an LCD device (LCD cartridge) in a relative steering system and absolute steering system, respectively. In this diagram, the expansion device control circuit (LCD cartridge) 3 can be constituted through a so-called single chip microcomputer system 300. The computer system 300 comprises: a CPU 301 to control each section; a ROM 302 for storing control programs and data libraries for the CPU 301; a RAM 303 used to store CPU and data programs and implement data processing; a MIEM of expansion device 304 for conducting data communications between the expansion device and the host; a I / O section 305 that performs an input and output interface; and LCD 306 controller to control the 308 LCD screen and a 307 LCD controller to control the LCD element. The expansion device MIEM 304 is similarly constituted to the base device MIEM, but is not provided with a LM 203a busbar controller or gateways related thereto. The LCD cartridge stores text data, still image data, animated image data (including LD video, CD-V, DVD and TV information) and the like, transmitted in frame format of the host through the bus bar M, LM busbar and MIÉ 304 in a RAM 303. These data that will be displayed later are supplied by the CPU 301 to the LCD 306 controller and converted to images. further, the computer system 300 also comprises a reset signal generating circuit to generate a reset signal when the power supply is turned on, a crystal oscillator to generate a clock signal and, if necessary, a circuit is provided of voltage conversion (omitted from the drawings) to generate a voltage 3.3V for the MIÉ signal of device 205, or similar, of the power supply Vcc (+ 5V). The power supply Vcc (+ 5V, 3.3V) is supplied by the base device, but it is possible that the expansion device that generates the voltages needs to obtain its intended functions through an internal circuit. In the signal line ID2, power supply voltage Vcc is applied to the expansion device side. In the expansion device in the absolute address system, as previously established, the terminals IDO and ID1 to indicate the number of busbar LM are connected to section I / O 305. Figure 85 and Figure 86 show examples of memory cartridges (expansion devices) in a system of relative steering and absolute steering system, respectively. In these diagrams, the sections corresponding to Figure 83 and Figure 84 are marked with the same symbols, and the description of these sections is omitted. In this example, a fixed RAM 312, such as an EEPROM or memory with battery backup, etc., is provided. The data that will be retained is stored in the RAM 303 through the MIÉ 304. The CPU 301 writes the data stored in the fixed RAM 312 through the external output bus controller 311. In addition, according to the instructions of the host, the CPU 301 also reads the data written in RAM 312 to RAM 303, and then transfers it to the host via WED 03. For example, if the player interrupts the game by half, storing the game parameters transmitted by the host. the host until that middle point of the game, it is possible to start the next game from that midpoint. The fixed RAM 312 is connected to the bus controller 311 through a receptacle and can be exchanged for a plurality of fixed RAMs 312 in the form of a card. It is also possible to provide fixed RAM 312 in the computer system 300. Figure 87 and Figure 88 show examples of vibration cartridges (expansion devices) in a relative steering system and an absolute steering system, respectively. In these diagrams, the sections corresponding to Figure 83 and Figure 84 are similarly marked, and these sections will not be described here.

In these examples, a controller / control section 321 is provided to activate a vibration unit 322 through a motorcycle, solenoid, or the like, which causes an eccentric weight to rotate, thereby generating a vibration. An activation command signal or an activation interrupt command signal for the vibration unit is stored in the RAM 303 through the host via the MIÉ 304, and is supplied by the CPU 301 to the controller / control section 321 through section I / O 305. Figure 89 and Figure 90 show examples of light gun cartridges (expansion devices) in a relative steering system and an absolute steering system, respectively. In the diagrams, the sections corresponding to Figure 83 and Figure 84 are similarly marked, and these sections will not be described here. In these examples, the illumination point of the electron light beam scanning a certain portion (objective point of the light gun) of a video screen, is read through a photoreceptor element 332 by a lens of the gun cartridge of light. The signal level of the photoreceptor is amplified by an amplifier 331. When the trigger (eg, element 2d in Figure 97 (b) described below) of the game controller is operated, a trigger signal is generated and the output of the Amplifier 331 is supplied as a detection signal towards MIÉ 304. This signal is transferred to the host and used as a closing signal for the HV counter. Figure 91 and Figure 92 show examples of sound input cartridges (expansion devices) in a relative steering system and an absolute steering system, respectively. In the diagrams, the sections corresponding to Figure 83 and Figure 84 are similarly marked, and these sections will not be described here. In these examples, the output of a microphone 345 is amplified to an appropriate level by an amplifier 344 and then displayed by an A / D converter 343. The displayed sound data is stored alternately in first and second registers (FIFO) of a buffer 342. These data are read by a busbar controller 341 and transmitted to the transmission and reception buffer of the MIÉ 304. The sound data is formed in frames through the MIÉ 304 and transmitted to the host (device of game). This function makes it possible to use the host as a sound input, "karaoke", telephone, or communication device. Figure 93 and Figure 94 show examples of sound output cartridges (expansion devices) in a relative steering system and an absolute steering system, respectively. In the diagrams, the sections corresponding to Figure 83 and Figure 84 are similarly marked, and these sections will not be described here.In these examples, the sound data transmitted by the host is supplied from the MIÉ 304 to a bus controller 351 through a local bus bar. The bus controller 351 stores the sound data in a memory 352 based on a FIFO (First Input First Output) operation, and jointly and successively links transmitted sound data. The output of sound data by the memory 352 is converted to a sound signal through the D / A converter 352, its level is amplified by an amplifier 354, and output as sound of a speaker 355. This type of function allows the host functions as a sound response device (sound output), game sound effects device (particularly sound effects using a plurality of speakers), "karaoke" device, telephone receiver, or the like. The above modes for implementing the present invention describe two standard formats, but it is also possible to combine elements of the first implementation mode with the elements of the second implementation mode, as long as this does not produce technological incompatibilities. In addition, the present invention is not restricted to gaming device applications, but can also be used with small-scale computer systems, computer networks, computer devices, portable communication terminal devices, and the like. Figure 95 and Figure 96 illustrate other modes of implementation, wherein the bus bar M connecting the host to the peripheral devices has a wireless construction. In these diagrams, the sections corresponding to the first and second implementation modes are similarly marked, and these sections are not going to be described here. In Figure 95, radio modem devices 500 respectively are connected to the peripheral controller 1 h of a host (gaming device) 1 and the peripheral controller of a peripheral device (base device) 2. The radio modem devices 500 comprise : a data controller 501, a transmission section 502, a duplexer 503, a reception section 504, an antenna 505, and the like, and retransmit data transmission between the host and the peripheral device. In this case, the peripheral device 2 can be operated with battery. The data controller 501 performs a multiple value modulation of the signal SDCKA and the signal SDCKB that will be transmitted, for example, in order to transmit a QPSK modulation with a displacement of p / 4, the data is processed to create a signal component I and a signal component Q. These orthogonal data components are supplied to the transmission section 502. In addition, the data controller 501 creates an SDCKA signal and a SDCKB signal from the I and Q data components decoded by the reception section 504, and supplies these signals to the peripheral controller 501. The transmission section 502 comprises a multiple value modulator, for example, an orthogonal modulator for a QPSK modulation of displacement p / 4, and creates a carrier signal with a frequency f, to carry the frame data. The carrier signal is fed to antenna 505 through duplexer 503, and transmitted to a free space as an electromagnetic wave. In the peripheral device 2, on the other hand, the electromagnetic wave received in the antenna 505 forms a carrier signal, which is supplied to the reception section 504 by the duplexer 503. The reception section 504 comprises, for example, a detector synchronous wave, which separates the signal component I and the signal component Q from the carrier signal, and demodulates the data of multiple value. As previously established, the data controller 501 creates an SDCKA signal and an SDCKB signal from this multiple value data, which is supplied to the peripheral controller 501. Consequently, the cables and the like for the busbar M connecting the host and the peripheral device become obsolete. The wireless peripheral device 2 creates freedom in the usage specifications and separates the presentation design from the host. The aforementioned wireless modem device 500 also makes use of a portable telephone device (or PHS device). In this case, relatively inexpensive IC chips can be obtained, and not only for wireless use of the peripheral device as possible, but also a competition game or the internet can be used by connecting the host to a communication circuit. -The transmission system and the reception system can be duplexed according to the two signals SDCKA and SDKCB, or a composition using two transmission channels f ,, f2 can be used. In addition, by returning the SDCKA signal and the SDCKB signal to a serial data frame signal, the data can be administered to the other side via an individual communication channel f ,, the SDCKA signal and the SDCKB signal being decoded from the frame signal demodulated on the receiving side. Figure 96 shows an example where the wireless composition shown in Figure 95 is constituted through optical communications. In this diagram the sections that correspond to Figure 95 are similarly marked, and these sections will not be described here. In this example, an infrared modem device 600 is constituted by a data controller 601, modulator 602, light emitting section 603, light receiving section 604, demodulation section 605, and the like. The data controller 601 returns to the SDCKA signal and the SDCKB signal to a serial data frame signal. Modulator 602 modulates the activation current through a frame signal. The level modulation or frequency modulation can be selected, for example. The driving current is supplied to a light emitting element of the light emitting section 603, for example, an infrared emitting LED to activate the LED in an on and off state. The activated LED light is transmitted externally through an optical system. This transmitted light is input to the light receiving section 604 of the other infrared modem device 600. The input light is converted to an electrical signal through a photoreceptor element, for example, a phototransistor, and then demodulated to a signal digital data through the demodulation section 605. This data signal is returned to an SDCKA signal and an SDCKB signal through the data controller 601, which are transmitted to the peripheral controller. The peripheral controller in the host (game device) 1 or peripheral device 2 has already been described. In this way, the busbar M can be constituted by a radio system (wireless) instead of a wired system. Next, the connectors and the like in the host and the peripheral device will be described with reference to FIG. Figure 97 (a) is an illustrative diagram showing a busbar connector M, which connects a game device 1 forming the host to a base device (game controller) 2 forming a peripheral device. In this diagram, the sections corresponding to Figure 1 are similarly marked. • In the example in Figure 97, four connectors (receptacles) 110 are provided and on the side face of the game device. The connectors (plugs) 110 of the game controller 2 are connected to any of the connectors 1 i. The receptacles 1i and the plugs 110 each are of the following format comprising 5 terminals (needles). Buttons A, B, C and D (switches A, B, C, D) 2a and one key conforms to cross 2b (direction indicator switch up / down left / right) are provided on the upper face of the controller. set 2, and a trigger lever (trigger switch) 2d is provided on the support section of the game controller 2 (see Figure 97 (b)). These various buttons trigger the digital input switches 2Ó6. In addition, analogous buttons (analog keys) 2c are provided to drive analog switches 207 in order to drive an analog input. Analog keys are used, for example, to move cursors and pointers on the screen. Figure 97 (b) is an illustrative diagram for describing an LM busbar connector 131 connecting the base device (game controller) 2 to an expansion device 3 (omitted in the drawings). In this diagram, the sections that correspond to Figure 97 (a) are similarly marked, and these sections are not described here. On the back side of the game controller 2 facing the game device 1c, two busbar connectors LM (receptacle) 131. Figure 98 (a) shows a further example of a game controller. This game controller has functions that incorporate a game controller. In this diagram, the game controller 2 comprises the buttons A, B, C, D 2a, a cross-shaped key 2b, analogous keys 2c, a lever 2d (see Figure 97 (b) described above) and a radio button. start (start switch) 2e. In addition, a slot for inserting an expansion device is provided on the back side of the game controller (see Figure 97 (b)). A window 2f is provided in the center of the upper face of the game controller 2, towards its rear side. Figure 98 (b) shows an example of an LCD cartridge forming an expansion device 3. The LCD cartridge is composed so that, when the LCD cartridge 3 is inserted into the aforementioned slot and connected to the game controller 2 through of the expansion connector 131, the LCD panel 308 is placed directly below the window 2f. Consequently, when an LCD cartridge 3 is connected to the game controller 2, it is possible to see the video and similar images transmitted from the game device 1 in the game controller 2. Furthermore, this LCD 3 is also provided with a key with cross shape 2b, buttons A, B, C, D 2a, and the like, so that the LCD 2 cartridge as a unit can be used as a portable gaming device. Figure 99 - Figure 101 are diagrams showing the composition of a busbar connector M used in a busbar M. Figure 99 gives an approximate illustration of the receiver side of a busbar connector 1i provided in the case of a busbar connector. host 1, viewed from the front address (the address connector is inserted). The receptacle comprises an approximately D-shaped perimeter section, an approximately D-shaped hexagonal needle base 102., and an approximately D-shaped groove 103 formed between the perimeter section 101 and the needle base 102. The receptacle is an extruded mold made of insulating plastic and contact needles No. 1, No. 3, No. 5 they are formed on the main face (upper face) of the base needles 102, while the contact needles No. 2 and No. 4 are formed on the opposite face (lower face) thereof, which is parallel to the main face. Contact needle No. 2 is placed opposite the insulating region between contact needles No. 1 and No. 3, so it is not reliable to produce capacitor coupling with contact needles No. 3 or No. 5 Each contact pin is a flexible metal component and is respectively connected to five circuit board connection terminals on the back side of the needle base 102, which is omitted in the drawings. The contact pins No. 1 and No. 5 are respectively connected to the data lines SDCKA and SDCKB. The contact needle No. 3 between the contact needles No. 1 and No. 5 is connected to a protection cable, which prevents the coupling between the contact needles No. 1 and No. 5 connected respectively to the data lines . The contact pins No. 2 and No. 4 are power supply lines and are respectively connected to a power supply Vcc and to a ground line GND. As previously stated, the metal surfaces of contact needles No. 2 and No. 4 are positioned so that they are not directly opposite the metal surfaces of contact needles No. 1, No. 3 and No. 5, and therefore the power supply Vcc and the ground line GND have little effect on the data lines. Figure 100 shows the composition of the plug side of busbar connector 1i corresponding to this receptacle. Figure 100 (a) is a side view of the plug; Figure 100 (b) is a top view; and Figure 100 (c) is a front view. The plug is molded from plastic with good insulating properties, and 111 is a housing for containing the connecting sections between wires and terminals contact pin, 112 is an insertion section having a cross section approximately D-shaped corresponds to the shape of the slot 103 in the receptacle 113 is an inner wall approximately D-shaped insertion section, 114 is a groove with a shape corresponding to the outer shape of the needle base 102, and No 1 - No. 5 are contact pins provided on the inner wall 113. Each contact needle is a flexible metal component, and is provided corresponding to the respective needles in the receptacle. The two groups of contact pins No. 1 - No. 5 are connected together by inserting the plug section 112 into the slot 103 in the receptacle. Figure 101 is a side view illustrating a connector (plug) on the side of peripheral device (base device) of a wire bus bar 121 M. The plug molded plastic having good insulating properties comprises terminals No. 1 - No. 5 which are connected to the different cables in the wiring. The terminals are provided in a row on one side having a receptacle with an approximate rectangular or plate shape. This receptacle 121 is connected to the cables of a circuit board in the peripheral device through a connector (receptacle), or through direct welding. Figure 102 shows a compositional example of a receptacle 131 of a busbar connector LM, which connects a base device to an expansion device. Figure 102 (a) is a top view, and Figure 102 (b) is a front view.

In addition, Figure 103 shows a compositional example of a plug 141 in a busbar connector LM. Figure 103 (a) is a top view, and Figure 103 (b) is a front view. Generally speaking, the receptacle 131 comprises an insertion section 132, a receiving section 133 and a housing 134, which engages or adapts these two sections. Similarly, the plug 141 also comprises an insertion section 142, a receiving section 143 and a housing 144 which engages or accommodates these two sections. The receptacle insertion section 132 is inserted into the receiving section 143 of the receptacle 141, and the insertion section 142 of the receptacle 141 is inserted into the insertion section 133 of the receptacle 131.

The insertion section 132 of the receptacle 131 is a bar-shaped component projecting from the left side of the front face of the housing 134, and an insertion groove 132a having a thin rectangular shape extending in a lateral direction is formed on the front end of the receptacle. this bar-shaped component. The insertion slot is a slot provided for inserting the insertion section 132 into a slot 143a on the plug 141, so that it is placed on a plate-shaped needle base 143c in the groove 143a. The insertion groove 132a is formed towards the bottom of the end of the rod-shaped component in the vertical direction, in order to avoid incorrect insertion, and also in order to arrange the plurality of contact needles approximately in the center of the bar-shaped component 132. The metal contact needles No. 1 - No. 7 are provided in a row on the upper face of the inner wall 132b of the insertion groove 132a. These contact needles are located in an approximately central position in the vertical direction of the bar-shaped unit 132. Although not shown in the diagram, each of the contact needles No. 1 - No. 7 extends to a plurality of connection terminals respectively provided corresponding to the contact needles No. 1 - No. 7, on the rear side of the housing 134, and in this way are connected to the wiring of the circuit board or to a cable. The contact pins No. 1 - No. 7 are respectively connected to the power supply line Vcc (3.3V), the power supply line Vcc (5V), the control line SDCKA EN, the data line SDCKB DS, the SDCKA US data line, the identification line ID1, and the ground line GND. The receiving section 133 in the receptacle 131 is a bar-shaped component projecting from the right side of the front face of the housing 134, and the O-shaped groove 133a surrounding the base of the needle 133c is formed on the front end of this rod-shaped component 133. The shape of the inner wall 133b and of the slot 133a corresponds to the external shape of the insertion section 142 of the plug 141. The needle base 133c in the center of the slot is a plate-shaped component having a shape corresponding to the thin rectangular groove 142a, which extends in a lateral direction. The upper face of the needle base 133c is formed so that it is in an approximately central position in the vertical position of the end of the rod-shaped component 133, and the flexible metal contact needles No. 8-No. 14 are arranged on this upper face. Although not illustrated in the diagram, the respective contact pins No. 8 - No. 14 are respectively connected to a ground line GND, identification line ID2, data line SDCKB DS, data line SDCKB US, control line SDCKB EN and IDO ID line. The contact needle No. 14 is not used here and forms an available terminal. The plug 141 inserted in the receptacle 131 is similarly formed to the receptacle 131. However, as shown in Figure 103 (a), the contact pins No. 1 - No. 7 are provided within the receiving section 143, and the contact pins No. 8 - No. 14 are provided within the insertion section 142. Since the expansion connector having the aforementioned composition comprises insertion sections 132, 142 and receiving sections 133, 143 which are formed separately and have mutually different external shapes, the user is able to identify at a glance, the direction in which the receptacle 131 and the plug 141 must be connected. In addition, since the connection is only possible in one direction (configuration), the incorrect connection does not occur. In addition, there is merit in that the hands of the user do not touch the connecting needles directly. As described above, according to the present invention, data communications can be conducted between a gaming device (or host) and peripheral devices through two data lines and a relatively simple I / O circuit composition. In addition, when conducting data communications, since the addresses are automatically set for a plurality of devices connected to a network, the peripheral devices can be freely connected to the game device (or host), and the game device can identify the details of a connected peripheral device, which is advantageous in a consumer-oriented computer system, such as a game device.

Claims (33)

1. CLAIMS 1. A data transmission system for transmitting data by distributing an item of data in series between a first and a second data signal, wherein the first data signal contains each of the bits with odd number of the serial data, respectively distributed between pulses of a first clock formed through a pulse sequence having a uniform interval; the second data signal contains each of the even-numbered bits of the serial data, respectively distributed among pulses of a second clock formed through a pulse sequence having the same frequency as the first clock signal; the first data signal is transmitted so that the pulse edge of its clock signal component is located in the data section on the second data signal on the time axis; and the second data signal is transmitted so that the pulse edge of its clock signal component is located in the data section of the first data signal on a time axis.
2. 2. The data transmission system according to claim 1, wherein the data superimposed on the data signal of the first and second data signals are isolated by closing the level of the data signal at the pulse edge of the data signal. clock signal component of the other data signals.
3. 3. A data transmission system for transmitting a data frame defined according to a transmission format comprising, at least, a start pattern carrying start data information, a data pattern carrying serial data , and a final pattern that carries final data information, distributing said data frame between a first and a second data signal, wherein the start pattern is created by setting the first data signal to a constant value and setting the second signal of data as a first pulse sequence signal; the data pattern is created by forming the first data signal by distributing each of the odd number bits of the serial data respectively between pulses of a second pulse sequence signal having a constant interval, and forming the second data signal distributing each of the bits with even number of the series data respectively between pulses of a third pulse sequence signal, which is displaced by a prescribed amount of the position on the time axis of the second pulse sequence signal; and the final pattern is created by setting the second data signal to a constant value, and setting the first data signal as a fourth pulse sequence signal.
4. 4. A gaming device that requests the transmission of data required for a game by transmitting two data signals simultaneously through a signal transmission path to an individual peripheral device or plurality of peripheral devices, comprising: a pattern creation means start to create a start pattern represented by two data signals, wherein a first data signal is set to a constant value state for a first time period, and a second data signal is set to a signal state of a watch during a first period; means for creating a data pattern to create a data pattern represented by two data signals, wherein the data that will be transmitted to the peripheral device is divided into two data sequences, and a first data signal is created by inserting each bit of data. the first data sequence respectively between the pulses of a first clock signal, and a second data signal is created by inserting each bit of the second data sequence respectively between pulses of a second clock signal having the same sequence as, and a prescribed phase difference of the first clock signal; means for creating an end pattern to create an end pattern represented by two data signals, wherein the second data signal is set to a constant value state for a second period, and the first data signal is set to a state of clock signal during a second period; and means for creating a frame to create a frame represented by two data signals, containing the start pattern, the data pattern and the end pattern, and transmitting the frame as a transmission unit to the peripheral device. The gaming device according to claim 4, wherein the data is serial data, the first data sequence is a data sequence comprising the odd number bits of the serial data, and the second sequence of data. Data is a sequence comprising the bits with even number of serial data. The gaming device according to claim 4, wherein the prescribed phase difference is determined such that the pulse edge of the clock signal contained in a data signal of the two data signals representing the data pattern is located in the data section of the other data signal on the time axis, and the pulse edge of the clock signal contained in the other data signal is located in the section of a data signal on the axis of weather. 7. "The gaming device according to claim 4, wherein the data pattern comprises a command and a parameter, and said parameter comprises, at least, the address of the peripheral device connected to the signal transmission path that is to receive the frame. 8. The gaming device according to claim 4, wherein the signal transmission path comprises at least one of: data signal lines, radio communication channels and optical communication channels. 9. A peripheral device for a gaming device that sends information required for a game to a gaming device having an input / output port or a plurality of input / output ports transmitting two data signals simultaneously, comprising: creation means start pattern to create a start pattern represented by two data signals, wherein a first data signal is set to a constant value state during a first time period, and a second data signal is set to a state of a clock signal during a first period; means for creating a data pattern to create a data pattern represented by two data signals, wherein the data that will be transmitted to the peripheral device is divided into two data sequences, and a first data signal is created by inserting each bit of data. the first data sequence respectively between the pulses of a first clock signal, and a second data signal is created by inserting each bit of the second data sequence respectively between pulses of a second clock signal having the same sequence as, and a prescribed phase difference of the first clock signal; means for creating an end pattern to create an end pattern represented by two data signals, wherein the second data signal is set to a constant value state for a second period, and the first data signal is set to a state of clock signal during a second period; and means for creating a frame to create a frame represented by two data signals, containing the start pattern, the data pattern and the end pattern, and transmitting the frame as a transmission unit to the peripheral device. The peripheral device for a gaming device according to claim 9, wherein the data is serial data, the first data sequence is a data sequence comprising the odd number bits of the serial data, and the second data sequence is a sequence comprising the even-numbered bits of the serial data. The peripheral device for a gaming device according to claim 9, wherein the prescribed phase difference is determined such that the pulse edge of the clock signal contained in a data signal of the two data signals representing the data pattern is located in the data section of the other signal of -data on the time axis, and the pulse edge of the clock signal contained in the other data signal is located in the section of a data signal on the time axis. The peripheral device for a game device according to claim 9, wherein the data pattern comprises a command and a parameter, the parameter comprises, at least, the address of the input / output port of the game device which is to receive the frame. The peripheral device for a gaming device according to claim 9, wherein the signal transmission path comprises at least one of: data signal lines, radio communication channels and optical communication channels. The peripheral device for a gaming device according to claim 9, wherein the data pattern comprises a command and a parameter, the parameter comprises, at least, a source address indicating the direction over the transmission path of the peripheral device transmitting said frame, and this source address is created based on the peripheral device identification information representing the type of peripheral device already registered by the peripheral device, and information regarding the input / output port to which the peripheral device is connected as indicated by the game device. 15. A peripheral device for conducting data communications with a game device comprising an input / output port or a plurality of input / output ports through a data transmission path connecting to one of the input / output ports of the game device, comprising: first storage means for pre-storing the identification information for the peripheral device representing the type of peripheral device; second storage means for storing the input / output port information representing the input / output port to which said data transmission path is connected, as indicated by the game device; and source address creation means for creating a source address for the peripheral device, which is appended to the data that will be transmitted to the game device, based on the identification information of the peripheral device and the input port information / departure. 16. A peripheral device for conducting data communications with a gaming device through a data transmission path by connecting to either an individual input / output port or a plurality of input / output ports provided in the gaming device , comprising: an individual base connector that is connected to the data transmission path; an individual expansion connector or plurality of expansion connectors that are connected to the data transmission path through the base connector, in order to connect other peripheral devices to the data transmission path; and an input / output controller for conducting data communications with the game device through the base connector; the input / output controller comprises: first storage means for pre-storing the peripheral device identification information representing the fact that the device is a peripheral device that is to be directly connected to the game device; second storage means for storing the input / output port information representing the input / output port to which the data transmission path is connected, as indicated by the game device; connection identification means for creating the connection information representing the connection status of other peripheral devices identifying whether or not a peripheral device is connected to any of the expansion connectors; and source address creation means for creating a source address containing the peripheral device identification information, the input / output port identification and the connection information, which is to be appended to the transmission data. The peripheral device according to claim 16, wherein the identification means determines whether or not there is a connection in the expansion receptacles by identifying the voltage level of a particular terminal of the expansion connectors, which are connected to a compound level displacement circuit so that a bypass voltage is supplied through the additional peripheral device. 18. A peripheral expansion device that is connected to the peripheral device according to claim 16 through the expansion connector, comprising: first storage means for storing the connecting identification information representing the number of an expansion connector as it is indicated by the input / output controller through the expansion connector, after connecting to the expansion connector; second storage means for pre-storing peripheral expansion device information representing the fact that the device is a peripheral device to be connected to the expansion connector; third storage means for storing the input / output port information representing the input / output port to which the data transmission path is connected, as indicated by the gaming device through the data transmission path, and the base connector and the expansion connector; and source address creation means for creating a source address containing the peripheral device expansion information, the input / output port information and the connection information, which is to be appended to the transmission data. 19. A gaming device comprising an individual input / output port or a plurality of input / output ports for connecting through a main data transmission path a composite base peripheral device such that a peripheral expansion device individual or a plurality of these devices can be connected thereto via auxiliary data transmission paths, a game device comprising an input / output controller for conducting intermittent data communications with any of the peripheral devices through signaling signals. framework; wherein the data communications are conducted in accordance with a format by which a relevant peripheral device responds to instructions from the input / output controller; frame signals comprise: a start pattern representing the beginning of a data pattern, a data pattern that carries transmission data and an end pattern representing the end of a data pattern; the data pattern comprises a command and a parameter; the parameter comprises a destination address and a source address; and both the destination address as well as the source address are created including information regarding the main data transmission path used in communications, the base device classification / peripheral device expansion device involved in the communications, and the auxiliary data transmission path used in communications. 20. The gaming device according to claim 19, wherein the auxiliary data transmission paths are respectively connected in parallel to the main data transmission path. The gaming device according to claim 19, wherein the peripheral peripheral devices and the peripheral expansion devices each respectively carry inherent information containing information about the type of peripheral device and information inherent in the device, the gaming device Read this inherent information through the transmission of data. 22. The gaming device according to claim 21, wherein the compatibility between the peripheral device and a game application is determined by reference to the inherent information. 23. The gaming device according to claim 19, wherein the main data transmission path is constituted by two data lines, and two data signals formed by dividing the frame signal are used to transmit the two data signals, respectively . 24. A base peripheral device for a gaming device, to which a peripheral peripheral expansion device or a plurality of peripheral expansion devices can be connected via auxiliary data transmission paths respectively provided, and which is connected to a game device comprising a single input / output port or a plurality of input / output ports through a main data transmission path, comprising: an input / output controller for conducting intermittent data communications with the device of play through the frame signals; wherein the data communications are conducted in accordance with a format by which the input / output controller responds to instructions from the game device; Frame signals include: a start pattern representing the beginning of a data pattern, a data pattern carrying transmission data, and an end pattern representing the end of a data pattern; the data pattern comprises a command and a parameter; the parameter comprises a destination address and a source address; and both the destination address and the source address are created including information regarding the main data transmission path used in communications, the master / slave classification of the peripheral device involved in communications, and the auxiliary data transmission path used in communications. The base peripheral device for a gaming device according to claim 24, further comprising a connector for connecting to the main data transmission path, and a plurality of expansion connectors for connecting said data transmission path main to the auxiliary data transmission paths in parallel through the connector. 26. The base peripheral device for a game device according to claim 24, which further comprises storage means for storing the inherent information including the type of peripheral device and the information inherent to the device, wherein this inherent information is transmitted through the data communications in response to a request from the game device. 27. The base peripheral device for a gaming device according to claim 24, wherein the main data transmission path is constituted by two data lines, and the two data signals formed by dividing the frame signal are used. to transmit the two data lines, respectively. 28. A peripheral expansion device for a gaming device that is connected to a gaming device via an auxiliary data transmission path, a peripheral peripheral device to which peripheral expansion devices can be connected, and a path of main data transmission, comprising: an input / output controller for conducting intermittent data communications with the game device through the frame signals; wherein the data communications are conducted in accordance with a format by which the input / output controller responds to the instructions of the game device; Frame signals include: a start pattern representing the beginning of a data pattern, a data pattern carrying transmission data, and an end pattern representing the end of a data pattern; the data pattern comprises a command and a parameter; the parameter comprises a destination address and a source address; and both the destination address and the source address are created including information regarding the main data transmission path used in communications, the base device classification / peripheral device expansion device involved in communications, and the path of auxiliary data transmission used in communications. 29. The peripheral expansion device for a gaming device according to claim 28, wherein the main data transmission path is constituted by two data lines, the auxiliary data transmission path is constituted by two data lines in the upstream direction and the two data lines in the downstream direction, and the two data signals formed by dividing the frame signal are used to transmit said two data lines, respectively. 30. An information storage medium, wherein programs are stored to cause a computer system to operate as the game device according to claim 3. 31. An information storage medium, where programs are stored for causing a computer system to operate as the gaming device according to claim 30. 32. An information storage medium, wherein programs are stored to cause a computer system to operate as the game device in accordance with claim 30. 33. An information storage medium, wherein programs are stored to cause a computer system to operate as the game device according to claim 30.