MXPA98008706A - High power motor drive converter system and modulation control - Google Patents

Abstract

A high power motor drive converter (10) includes a three level neutral point (26) clamped (NPC) output power conversion stage (12) including switches (14);a split series connected DC capacitor bank (30) coupled in parallel with the NPC output power conversion stage;and a controller (15) for selecting switch positions for controlling the NPC output power conversion stage and controlling a neutral voltage balance of the DC capacitor bank by using space vector modulation and predictive charge calculations.

Description

HIGH POWER MOTOR TRANSMISSION CONVERTER SYSTEM AND MODULATION CONTROL BACKGROUND OF THE INVENTION The present invention relates in general to the modulation control for high power converters, and more particularly to the determination of gate timers for electronic power switches in three-phase power converters that are used in transmission systems. motor. Baker et al., US Pat. No. 4,270,163, propose a three-level power inverter circuit in a neutral-point bridge inverter (NPC), but do not provide a mechanism for neutral capacitor balance, or a viable modulation technique for vector-controlled transmission, both of which are necessary to use the power circuits in motor transmission systems. Different suggestions have been made to address the problems of how to use these proposed power circuits in motor transmission systems. For example, Kratz, U.S. Patent No. 4,855,893, discloses a method for providing neutral voltage balancing in which a twelve-pulse rectifier-source converter supplies the rigid grid support independent of each half of the co-current capacitor bank. direct, in which the switching safety of the power devices is improved with a protection design. This mode eliminates active control for the capacitor's voltage balance, and simplifies the controller's requirements, but unfortunately it can not achieve total demand distortion (TDD) of five percent in the grid connection, which requires the IEEE- standard. 519 established by the Institute of Electrical and Electronics Engineers (IEEE). The modulators. previous ones were defined as sinusoidal triangle hardware schemes, p with optimized off-line switching patterns. More modern point-based modulator approaches have been developed, which are based on spatial vector synthesis techniques, using algorithms that focus on gate shutdown converters (GTO), where large constraints of minimum gate regulation time constraints (greater than 100 microseconds) are a dominant consideration. First, active neutral voltage control was described, using sinusoidal triangle modulation schemes with zero sequence voltage insertion for voltage balance control. The zero sequence reference voltage was developed from the capacitor voltage imbalance, and the power flow direction (motorism or regeneration). The synthesis algorithms of the spatial vector modulator were also modified to take advantage of the redundant states of the vector, in order to control the balance of the neutral voltage. Many spatial vector methods have included subdividing the vector space to avoid the minimum pulse timing constraints of the gate shutdown switching elements, by simultaneously controlling the neutral voltage of the capacitor while minimizing the switching frequency. Neutral voltage balance control systems based on power flow, from the prior techniques, may have problems maintaining neutral control under high dynamic conditions.

SUMMARY OF THE INVENTION It is therefore seen that it is desirable to provide a fast response high power motor transmission converter system. It would be particularly useful to provide a system for operation in the power range of 1-20 MW, capable of supplying an alternating current (AC) transmission motor with an average voltage output of 2.3-6.6 KV at fundamental output frequencies up to 100-200 Hz range. In one embodiment of the present invention, a fast response high power motor transmission converter system includes: an output power conversion stage fastened in three level neutral point, connected to an alternating current transmission motor, a direct current capacitor bank connected in branch series, a controller to calculate the time switches of the switch by means of spatial vector modulation with an actively controlled neutral voltage balance, using the calculation method of predictable load, and either a converter bridge of a non-regenerative diode rectifier source, or a second stage of input power conversion held in a three-point neutral point, configured as a pulse amplitude modulation (PWM) source converter . In this mode, the three-level power converter minimizes the voltage steps applied to the drive motor (reducing winding voltages), and allows medium voltage outputs' using commercially available switching devices (IGBT (asylated gate bipolar transistor) , GTO, or IGCT (integrated gate-commutated thyristor)). The faster switching IGBTs or IGCTs allow more flexibility, and some algorithm simplification compared to GTO converters. The modulator control of the three-level inverter is used to determine the gate timings for the electronic power switches in the three-phase power converter. The converter, in general, produces sinusoidal currents by means of a pulse amplitude modulation (PWM) process, in order to achieve a smooth control over the load voltage. The modulation control of the converter must be able to operate as the activation stage in a vector-controlled or synchronous induction motor control, and in this way, be able to create an arbitrary output voltage vector at each sampling time of control, in response to transient torsion events. Modulation control is preferably software based to minimize any specialized hardware requirements. This modality will support a variety of options, including the addition of dynamic braking resistive elements actively controlled in the non-regenerative configuration. Other options include the addition of protection circuits in the internal elements of the switch and / or in the external elements of the switch. Another modification includes the addition of a tuned neutral-ground reference network to provide damping for wave fronts that propagate in the motor cables.

BRIEF DESCRIPTION OF THE DRAWINGS It is believed that the characteristics of the invention are novel, and are stated with particularity in the appended claims. The invention itself, however, insofar as both in organization and method of operation, together with other objects and advantages thereof, can best be understood by reference to the following description, taken in conjunction with the accompanying drawings, wherein the same numbers represent the same components, in which: Figure 1 is a circuit diagram of a non-regenerative converter with low grid current distortion, and active control of neutral charge balance. Figure 2 is a circuit diagram of a regenerative converter mode. Figure 3 is a circuit diagram of a three-stage phase branch fastened in neutral point. Figure 4 is a circuit diagram of protection circuits applied to internal elements of the phase-locked switch in neutral point of Figure 3. Figure 5 is a circuit diagram of protection circuits applied to external elements of the circuit breaker of the circuit breaker. phase branch clamped in neutral point of Figure 3. Figure 6 is a circuit diagram of a dynamic braking circuit. Figure 7 is a circuit diagram of a ground reference network.

Figure 8 is a vector diagram of three-level pulse amplitude modulation (PWM3) space. Figure 9 is a diagram of sector d / triangle indexes and local vertices. Figure 10 is a set of graphs illustrating the internal triangle modulation of three-level pulse amplitude modulation. Figure 11 is a set of graphs illustrating the external triangle modulation of three-level impulse amplitude modulation. Figure 12 is a diagram of the transient response of the spatial vector of amplitude modulation d impulse of three levels.

DETAILED DESCRIPTION OF A PREFERRED MODE OF THE INVENTION Figure 1 is a circuit diagram of a non-regenerative converter 10 with low grid current distortion, and active control of neutral charge balance, and Figure 2 is a circuit diagram of a regenerative 1 converter. Both embodiments include a stage 3 of output power conversion of three levels. The output power stage includes electrical switches 14 which are shown as IGBTs (abbreviations in English for Bipolar Transistors of Assem- bled Gate). Other useful switches include GTOs (for Gate Shutoff Thyristors) and IGCTs (for Switched Gate Integrated Thyristors). The switches are switched on with anti-parallel diodes 16 to freewheeling, to accommodate the inductive load currents of the motor. U controller 15, which is shown in Figure 1, is used to control each of the switches. The controller comprises a computer, and in a preferred embodiment, includes a digital signal processor. Figure 3 is a circuit diagram of a branch 18 single-phase phase of three levels held in neutral point of Figure 1 and Figure 2. The three-phase inverter has four pairs of switch and diode, connecting the direct current busbar (with a positive rail labeled P-Bus 20, a negative rail labeled N-Bus 24, and a middle point of the bus bar labeled Midpoint 26) and of clamping diodes 22 (labeled D5, D6). The switch-diode pairs are labeled from top to bottom Sl / Dl, S2 / D2, S3 / D3, S4 / D4. As shown in Table 1, there are three command states for the switches per phase.

Table 1 NPC states Depending on the state indicated by the interrupt per phase, and the instantaneous polarity of the load current in that phase, the path of the charging current can be through switches, free-wheeling diodes, or clamping diodes. For example, if the indicated state is STATE 2, and the charging current is positive, the trajectory of the charging current is through the diode d holding D5 and the switch S2. If the indicated state is e STATE 2, and the load current is negative, the trajectory of the load current is through switch S3, and clamping diode D6. Table 1 shows that the charge terminal can be either P-bus, N-bus, or at the midpoint of the direct current busbar, which causes the inverter terminology of three levels or clamped in neutral point. In a two-level inverter, the load terminal po phase is either P-bus or N-bus. This extra load point level, that is, the midpoint of direct current, in the three-level inverter explains its lower harmonic load current amplitudes than a two-level inverter that produces pulses at the same frequency. The second advantage of the three-level inverter is that with four switches connecting the direct current busbar, each with a direct current voltage working at maximum, equal to one half of the DC link voltage, two can be obtained. Sometimes the d output voltage for a given rated voltage of breaker, compared to a two-level inverter. This is achieved without the need to regulate the switches directly in series, and thus avoiding the complications of voltage on, shutdown. The midpoint of the bank 30 of the capacitor 28 (at the midpoint 26 of direct current), and the clamping diodes 22 d connected between the midpoint of the capacitor bank and the switches S1 / S2 and S3 / S4 respectively, prevent the Maximum direct current working voltage, through any switch, exceeds one half of the direct current busbar voltage (Vdc / 2), with the condition that the voltage of the midpoint of the direct current filter capacitor keep in Vdc / 2. Regulators are built into the modulator to maintain the mid-point voltage in Vdc / 2, to protect against the long-term irregular discharge of the two halves of the capacitor bank. The resistor network 19 (shown in Figures 1 and 2), through the bank of the direct current collector capacitor bank, serves as a fixed safety discharge resistor, and a balance network for the initial charge of the capacitor. Figure 4 is a diagram of optional protection circuits 32, applied to low ainductance and busbar design, such that 1 * ^ Figure 5 is a circuit diagram illustrating optional protection circuits. applied to the external switches of the NPC phase branch of Figure 4.

The shields of the illustrated outdoor switches also act to hold the formation of rings through the switch to halve the direct current busbar during shutdown of the device. The diode 42 of protection, the protection capacitor 44, and the protection resistor 46 of Figure 5 operate on the external switches in the same way that they operate the diode 34 for protection, the protection capacitor 36, and the protection strength 38 of Figure 4 in the internal switches. The low harmonic distortion of the grid current is important for the IEEE-519 standard, which requires an objective that can be measured to less than five percent of total demand distortion in the grid connection. To satisfy this standard, a non-regenerative or regenerative circuit can be used, based on the specific transmission application. The non-regenerative variant of this invention, illustrated in Figure 1, includes an eighteen-pulse diode rectifier 48 to convert the power of the grid 56 alternating current to the direct current busbar power required for the NPC voltage source inverter. Low distortion of grid current is important, to avoid excessive harmonic distortion in the utility grid. The series connection of eighteen pulses of three bridges 50 six-pulse diode rectifiers is most useful with a grid transformer 52 with three isolated sets of three-phase transformer secondaries 54, with phase separation of 20 degrees between the three sets . Although eighteen-pulse diode rectifiers are preferred, other diode rectifiers may alternatively be used. Another alternative embodiment (not shown), for example, capable of achieving the current distortion level requirement of the IEEE-519, is a twenty-four pulse configuration that includes four six-pulse rectifiers in series, powered from a power transformer. grid with secondary sets of 15 degrees of phase separation. This circuit has an advantage in the sense that the branching direct current busbar that is required for the NPC output converter stage can be achieved by feeding two rectifier bridges in series into the upper half of the capacitor bank , and the two remaining rectifier bridges within the lower half of the capacitor bank. This rigid independent power supply makes obvious the need for active control of the neutral voltage balance.

This option, however, increases the number of diode components, increases the complexity of the transformer, and increases wiring costs. Another alternative mode (not shown) is a twelve-pulse configuration that includes two six-pulse rectifier bridges. This mode includes fewer diode components and complexity, at the expense of additional distortion. The harmonic limits of IEEE 519-1992 are a function of the ratio of the line short circuit, Isc, to the rated current of the transmission, III. For proportions below twenty, Table 2 gives the current harmonic limits expressed in terms of Total Demand Distortion (TDD). This measure differs from the total harmonic distortion since the distortion content is measured relative to the nominal current of the transmission. The Total Demand Distortion of the global current must be less than five percent.

Ta e 2 Req ect m e m e th e I n e m e rs IEEE-519-1992 In addition, due to the special harmonic generation properties of eighteen-pulse rectifiers, the Total Demand Distortion limits can be increased for eighteen-pulse rectifiers for their characteristic harmonics by a factor of 1.73, with the proviso that the amplitudes of non-characteristic harmonics are twenty-five percent of the limits specified in the tables. The IEEE 519-1992 also restricts line voltage distortion. Total harmonic distortion (THD) with a maximum line impedance of five percent must not exceed five percent, with each individual harmonic not exceeding three percent of the total Harmonic Distortion. Figure 6 is a circuit diagram of an optional dynamic braking circuit (DB) 58 for a non-regenerative converter. A dynamic braking resistor 60 is provided to transiently dissipate the energy stored in the rotating inertia that regenerates within the direct current busbar, during engine deceleration. The dynamic braking switches 62 are controlled by gate in synchronism, based on the measured voltage of the direct current busbar (provided that the voltage of the direct current bus rises above the high line level). The controller must provide the appropriate hysteresis, in order to limit the maximum bus voltage, the dynamic braking switching frequency, and the switching losses of the device. S provides a freewheeling diode path 64, to accommodate the inductive current paths to the dynamic braking resistor. A diode clamping path 65 is supplied to the neutral direct current bus, to allow timing variations of the two dynamic braking switches. Figure 2 illustrates a complete regenerative mode that will typically be used in high performance motorcycle transmissions 74, or transmissions that must rapidly decelerate inertial loads. Power conversion stage 66 includes an NPC converter bridge similar to bridge 12 NPC converter. The embodiment of Figure 2 is capable of arbitrarily loading power factors while providing a unit power factor interconnection to the grid. The input rectifier bridge 66 'with three-phase branches 68 serves as a pulse amplitude modulation boost converter, which regulates the overall direct current bus voltage. The input converter 66 is interconnected with the utility grid 56 through an input stage filter assembly 70, which will filter the high frequency switching harmonics from the current of the three-phase converter. U input stage transformer can be an integral part of the inductive elements in the grid filter. The DSP controller will regulate the three phase input current flow. The power circuit must be supported by an active direct current neutral voltage balance control, and, in the present invention, active control is provided by a predictable load calculation method. If the direct current neutrals of the two converters are connected, then the charge balance of the combined branch capacitor bank can be maintained by either of the two converters. It will generally be preferred that the load size release the source converter control for the regulation of the grid current. Alternatively, source and load converters can maintain separate neutrals without any common connection. In this case, both modulation controls must independently maintain the neutral charge balance. Figure 7 is a circuit diagram of a ground reference network that is preferably coupled between the neutral direct current point 26, and a frame 73 to ground. The ground reference network impedance is selected to approximately match the characteristic impedance of the motor cable. The voltage across the ground reference network is monitored by the controller for ground fault detection. Preferably, a transmission controller based on a digital signal processor (DSP), uses neutral active control by means of manipulation of gate timing, in order to maintain a similar voltage balance in the branching series capacitor bank (between the upper and lower halves of the direct current link). It is desirable to also have strict control of neutral load currents, in order to minimize the required capacitance values. In one embodiment, the controller is a completely software-based system, executed on a computer with interconnection circuits for voltage and current feedback data acquisition and digital timers for switch activations based on the computer signal timing of the digital signal processor. The digital signal processor will include vector control of both the machine torque and the flow. The digital signal processor will also include a spatial vector modulation control for the NPC converter bridge. In addition, the digital signal processor will include active control of direct current busbar neutral voltage by means of the manipulation of gate timing, in order to maintain an equal voltage balance in the branching series capacitor bank.

An algorithm for controlling the modulator of the present invention is executed in the digital signal processor controller, by requiring only three additional hardware timers, one per phase, for activation. The control algorithm is an extension of the spatial vector synthesis approach developed for two-tier inverters. A rapid response to an arbitrary reference voltage vector is assured by means of an immediate irregular curvature transition between the local vertices, followed by the adjacent vector modulation. Neutral voltage control is achieved by selecting between alternative vectors based on measured voltage error and predicted load, using either measured or reference phase currents. The predicted charging method ensures a maximum neutral corrective effort regardless of the load power factor. Figure 8 is a diagram of the spatial vectors modulated in the three-level pulse amplitude (PWM3), which illustrates the complex voltage plane defined by the orthogonal voltage axes a, β, and indicating the direction of the phase voltages A, B, C. The phase axes o; and A are aligned with the peak of the voltage wave of phase A. The hexagonal outer limit indicates the voltages that can be reached, defined by the magnitude of the direct current bus (Vdc) voltage. The vertices of the individual triangular regions are denoted by a three-digit gate regulation state, one digit per phase, in the ABC order. Each digit can assume a value -, 0, or * that represents the three voltage levels available in a phase branch of the inverter. The reference voltage vector V * is denoted by rotating the frequency we in a counter-clockwise direction. For smooth voltage synthesis during steady-state conditions, the reference voltage vector will sweep through adjacent triangular regions at a sinusoidal frequency, and a substantially constant magnitude. The spatial vector synthesis will create the desired voltage by means of time modulation between the three corners of the corners of the triangular region containing the tip of the reference voltage vector. Figure 9 is a diagram of the sector / triangle indices and the local vertices, illustrating the control of the modulator by segmenting the complex voltage plane. Twelve vectors are defined, of 30 degrees in arc (dc = 0-11). Each 30-degree sector is further subdivided in magnitude between three triangular zones (ms = 0-2). An index ds is assigned to the reference voltage vector, in accordance with the reference angle to the a axis, and an index ms based on the reference amplitude. The combination of the ds and ms indices defines one of the 36 triangular zones within the voltage hex that can be reached. Once the correct triangular area has been located, a local vertex position is defined by Figure 9, as a vertex in common with one of the corners of the triangle, and in a position closer to the center of the diagram. There are 7 local vertices: one (+++ / 000 /) for all twelve internal triangular zones (ms = 0 and ds = 0-11) and six (+ 00 / 0--, ++ 0 / 00-, 0 + 0 / -0-, 0 ++ / - 00, 00 + / - 0, + 0 + / 0-0) for the 24 outer triangular zones (ms = 1 or 2). For example, if a reference voltage vector were in a triangular area XI-X4, the local vertex would be v6. Each modulation vector sequence always starts and ends at a local vertex. Redundant selections at voltage vertices allow for simultaneous voltage synthesis and load balancing, as explained below. Figure 10 is a set of graphs illustrating the internal triangle modulation PWM3. The sequence of the reference voltage vector starts at the local vertex 000. For each frame (or period) of regulation by gate, the switching pattern proceeds to the corners of the corners that define the triangular region, switching one phase at a time (000 to +00 to ++ 0 to +++), with a transition defined by phase, ending at the local vertex +++. The digital signal processor calculates residence times at each corner vertex, in order to achieve the desired reference voltage vector, on the average, during the gate regulation frame. The following calculation solves a set of simultaneous linear equations for calculating the residence times t03., Ti, and t2, with the zero vector residence time (t03) further subdivided in a similar manner between tO (residence time 000) and t3 (residence time +++): m =, mcosd = m-cos (d), rasend = m- sin (d) 2 - V d, c mc ms ti = kl - dtpwm, t2 = k.2 • dtpwm, t03 = k03 • dtpwm, where d is the angle from the reference voltage vector to the nearest axis, dtpwm is the regulation interval time per gate, V * is the reference voltage vector, Vdc is the measured voltage, d is an angle of the reference voltage vector with respect to one side of the triangular zone in which the reference voltage vector is present, k03 is the residence time per unit at the local vertex, kl is the residence time per unit at the first corner vertex, and k2 is the residence time per unit at the second corner vertex. The digital signal processor outputs the regulation times per gate and the regulation states per gate for each phase; for example, for this sequence tO for A, tO + tl for B, t0 + tl + t2 for C. The chronometers are activated in a synchronized manner every regulation period by gate. After each gate control frame, at the next sampling time, in a preferred embodiment, the following appropriate switching pattern is determined. If the reference voltage vector is in the same triangular area as in the previous gate regulation frame, a second gate regulation frame crosses the vertices in the opposite sequence (+++ to ++ 0 to +00 to 000 ) from the first regulatory framework per gate. The described switching pattern uses only the regulation states by gate 0 and + for each phase. This has the effect of discharging the capacitor bank of the upper half when it is monitored. The first and second regulation frames per gate form a pair of regulation frames per gate. To continue to maintain the load balance in the capacitor halves, if the reference voltage vector remains in the same triangular zone, the sequence of the first and second regulating frames per gate can alternate with a sequence of regulation state per gate less , as in the second pair of gate regulation frames illustrated by Figure 10 (000 to 00- to 0 - a followed by a 0-- to 00- to 000). Depending on the modulation algorithm, after the completion of (1) each regulation frame per gate, (2) each pair of regulation frames per gate, or (2) two pairs of regulation frames per gate, at the time of sampling before the start of the next regulation frame per gate, whether the reference voltage vector remains or not in the same triangular zone, alternate gate regulation sequences are possible: a positive sequence of 000 to +++, a negative sequence of 000 a, or, for option (1) where the test is performed after each regulation frame per gate, one of the opposite sequences described above (+++ to 000 or a 000). To actively control the neutral charge balance for internal delta modulation, the net charge injected into the neutral direct current busbar is calculated for the alternatives available as the sum of the product of the phase current (ik) and the time neutral residence (dt ^) for each phase q =? k =? .. 3 (ik * ^ tnk) • Select the alternative, based on the polarity of the predicted neutral load, to correct any measured neutral voltage error . If the neutral voltage error is small (that is, within a small dead band), the positive and negative gate control sequences will alternate. If the reference voltage vector changes the triangles, then the local vertex will be switched to be the local vertex of the new triangular zone, in which the reference voltage vector is located. Figure 11 is a set of graphs illustrating the outer triangle modulation PWM3, that is, when the magnitude of the reference voltage vector is greater than half the maximum. The modulation sequence begins at the local vertex (grstaüe = + 00), and proceeds to switch one phase at a time from +00 to + 0- to + -, returning to the local vertex (grstate = 0--). Once again the residence times in each vertex of the triangle (t03, ti, and t2) are calculated, by solving a set of simultaneous linear equations for pts = l -.

TX 71"1 TT 1 eos -.eos- - cos - 6 6 2 mcosd 7T 7T 1 7T? L xnsind cos -.sensen 0 le 1. 6 6 2 3 l £ 1 1 1 or for ms = 2: TT TT 1 1 cos t_tJo - 6 6 2 mcosd 71"TT ¿1 i7¡sind = 0 cos - sin - 0 k2 1 6 6 k03 1 1 1 If no neutral correction is required, the residence time of the local vertex is subdivided equally between tO (residence time +00) and t3 (residence time 0--). The regulation frame by gate of the second half inverts the regulation sequence by gate 0 - a + - a + 0 - a +00. Once again, the actual activation of the regulation by gate is controlled by means of phase chronometers activated synchronously. The neutral voltage control for the external triangle modulation is achieved by adjusting the relative residence times for the redundant states of regulation by the local vertex gate (time tO against t3), while its sum remains fixed. The relative charge injection for the two alternatives is calculated again as the sum of the product of the phase current (ik) and the neutral residence time (dtnk) for each phase. The two alternatives will have similar and opposite effect. It will be maximized either tO or t3, based on the polarity of the predicted neutral load, to correct any measured neutral voltage error. The residence times are assigned to maximize the corrective action, that is, assigning t = t03 - tminz to the selected alternative, and tminz to the other, where tminz is a minimum impulse amplitude time. The maximum corrective action corresponds to a detonation-detonation control strategy. A linear controller with proportional correction can also be implemented. Optionally, if the neutral voltage error is small (that is, within a small dead band), the times tO and t3 can be set equally, without applying a corrective effort. Figure 12 is a diagram of the spatial vector Transient PWM3, which illustrates the irregular curvature transition mode that facilitates a fast transient response for vector-controlled transmissions. Two successive reference voltage vectors Vk * and vk +? * Are shown. • The algorithm will force a synchronized transition from the previous local vertex (time tk) to the new local vertex (time tk + 1). Each state of regulation by gate of the local vertex is assigned a polarity weight index that varies between -3 to +3 (for example, gsta te = + 00 has a weight of +1). The irregular curvature transition selects the regulation state by gate of the new local vertex, to minimize the change in the polarity weight index. r making the transition to the new local vertex, a conventional external triangle modulation sequence is calculated for the gate control frame of the next half. In this way, no delay is introduced in the synthesis of the next reference voltage vector. The same algorithm applies also to transitions within internal triangles, and between inner and outer triangles. With this control system, overmodulation is possible (non-linear production of high output voltages). Overmodulation can be achieved by lowering the pulse and / or changing the angle of the reference voltage vector to the nearest axis, thereby reaching the magnitude of the reference voltage vector, while still respected the amplitude constraint. of minimum impulse. Although only certain preferred features of the invention have been illustrated and described herein, many modifications and changes will occur to those skilled in the art. Therefore, it will be understood that the appended claims are intended to cover all such modifications and changes as falling within the true spirit of the invention.

Claims (23)

1. CLAIMS 1. A high power motor transmission converter comprising: a three-level output power conversion stage, clamped in neutral point (NPC), including switches for supplying power to an AC drive motor; a direct current capacitor bank connected in branching series, coupled in parallel with the NPC output power conversion stage; a controller for selecting the positions of the switches, for controlling the NPC output power conversion stage, and controlling a neutral voltage balance of the direct current capacitor bank by using spatial vector modulation and predictable load calculations; an input power conversion stage, coupled in parallel with the capacitor bank. The converter of claim 1, wherein the input power conversion stage comprises a non-regenerative diode rectifier input power conversion stage, or an amplitude modulation input power conversion stage. Three-level NPC, regenerative. 3. The converter of claim 1, wherein the input power conversion stage comprises a non-regenerative eighteen-diode diode rectifier input power conversion step, and the converter further comprises a dynamic braking circuit coupled in parallel with the capacitor bank. The converter of claim 2, wherein the input power conversion stage comprises the three-level, regenerative NPC pulse amplitude modulation input power conversion step, and wherein the step neutral points NPC pulse amplitude modulation output power conversion, and the NPC pulse amplitude modulation input power conversion stage, are electrically coupled. 5. The converter of claim 2, characterized in that it also includes a plurality of protection circuits, each protection circuit coupled to a respective one of the switches. 6. The converter of claim 2, characterized in that it also includes a tuned ne- ter-ground reference network to provide damping for reflected wave fronts that propagate in the motor cables. The converter of claim 2, wherein the controller is adapted to use the modulation of the spatial vector, to control a magnitude and a rotation of a reference voltage vector in a complex voltage plane, defined by orthogonal axes and voltages of phase. The converter of claim 7, wherein the complex voltage plane is divided into twelve sectors of thirty degrees, based on a reference angle of the reference voltage vector, with each sector of thirty degrees being subdivided into three zones triangular on the basis of the reference angle, and the magnitude of the reference voltage vector, where a total of thirty-six triangular zones are present, with twelve triangular zones representing the reference voltage vectors having magnitudes less than or equal to one half of a maximum magnitude, and having a central local vertex and twenty-four triangular zones on an outer perimeter of the twelve triangular zones, the twenty-four triangular zones representing the reference voltage vectors having magnitudes greater than or equal to one half of a magnitude maximum, and that they have six outer local vertices. The converter of claim 8, wherein the controller is adapted to create a reference voltage vector switching pattern that begins and ends at a selected local apex of the central and outer local vertices corresponding to a respective position of the vector of reference voltage, the switching pattern proceeding during a period of regulation by gate of the selected local vertex to the corner vertices that define a triangular zone, wherein the reference voltage vector is present while selecting the relative residence times at each corner vertex, to achieve the desired reference voltage vector during the gate regulation period. The converter of claim 9, wherein the gate regulation period comprises a first gate regulation period, and wherein the controller is adapted to create a second gate control period, with the switching pattern proceeding to the corner vertices in a direction opposite to the first regulation period per gate. The converter of claim 9, wherein, if the magnitude of the reference voltage vector is less than one-half of the maximum magnitude, the following set of simultaneous linear equations is used to calculate residence times at the vertices of corner: (1) V * m = -, mcosd = m-cos (d), msend = m-sin (d), 2 - V, dc (2) 1 1 71"- - • cos 0 2 2 3 mcosd 1 TG kl msind - 0 • sin 0 k2 1 2 3 k03 1 1 1 (3) ti = kl • dtpwm, t2 = k2 - dtpwm, t03 = k03 • dtpwm, where d = the angle from the reference voltage vector to the nearest axis dtpwm = the time of the regulation period by gate V * = the reference voltage vector Vdc = the measured voltage d = an angle of the reference voltage vector with respect to one side of the triangular zone in which the reference voltage vector k03 = the residence time per unit in the local vertex kl = the residence time per unit in the first corner vertex k2 = the residence time per unit in a second corner vertex t03 = the residence time in the local vertex ti = the residence time in the first corner vertex t2 = the residence time in the second corner vertex. The converter of claim 11, wherein the controller is adapted to, after the termination of a gate regulation period, determine whether to start a positive or negative gate regulation sequence, by predicting a net load that it would be injected at a neutral point for each alternative sequence as a sum of a product of a phase current, and the neutral residence time for each phase, and select the regulation sequence per gate based on the polarities of the net charges predicted , to correct any differences between the reference voltage vector and a measured voltage. The converter of claim 11, wherein, if the magnitude of the reference voltage vector is greater than or equal to one half of the maximum magnitude, then if the triangular zone has a side adjacent to one side of one of the twelve triangular zones, equations (1-3) of claim 10 are applied, with equation (2) being replaced with the following equation: mc ms or, if the triangular zone does not have a side adjacent to one side of one of the twelve triangular zones, equations (1-3) of claim 10 are applied, with equation (2) being replaced with the following equation: 7T 7T 1 1 COS • C Jo 6 6 2 mcosd 7T 7T kl msind = 0 COS -. sen - 0 kl 1 6 6 k03 1 1 1 14. The converter of claim 13, wherein the controller is adapted to adjust the residence times of the redundant states of the regulation by gate of a local vertex, based on the polarity of the predicted neutral change while holding a sum of the residence times of redundant states of gate regulation. The converter of claim 9, wherein each of the local vertices has a respective status of regulation by gate with an assigned polarity weight index, and the controller is adapted to respond to transient conditions, by means of selecting a regulation state by gate of a new local vertex, to minimize the change in the polarity weight index between a local vertex present and the new local vertex. 16. A method for controlling a high power motor transmission converter, which includes a three-level output power conversion stage, clamped in neutral point (NPC), which includes switches for supplying power to a power transmission motor. alternating current; a branched series direct current capacitor bank coupled in parallel with the NPC output power conversion stage, the method comprising: selecting the positions of the switches to control the NPC output power conversion stage, and control a neutral voltage balance of the direct current capacitor bank by using spatial vector modulation, to control a magnitude and rotation of a reference voltage vector in a complex voltage plane defined by orthogonal axes and phase voltages . 17. The method of claim 16, characterized in that it also includes dividing the voltage plane into twelve thirty-degree sectors, based on a reference angle of the reference voltage vector, and subdividing each thirty-degree sector between three triangular zones based on the reference angle, and the magnitude of the reference voltage vector, where a total of thirty-six triangular zones are present, with twelve triangular zones representing the reference voltage vectors having magnitudes less than, or equal to one half of a maximum magnitude, and having a central local vertex and twenty-four triangular zones on an outer perimeter of the twelve triangular zones, the twenty-four triangular zones representing the reference voltage vectors having magnitudes greater than, or equal to, one half of a maximum magnitude, and having six exterior local vertices. 18. The method of claim 17, further comprising creating a reference voltage vector switching pattern that begins and ends at a selected local apex of the central and outer local vertices corresponding to a respective position of the voltage vector. reference, the switching pattern proceeding during a period of regulation by gate of the selected local vertex to the corner vertices that define a triangular zone, in which the reference voltage vector is present while selecting the relative residence times in each corner vertex, to achieve the desired reference voltage vector during the gate regulation period. The method of claim 18, wherein the gate regulation period comprises a first gate regulation period, and characterized in that it also includes creating a second gate regulation period, with the switching pattern proceeding to the vertexes of the gate. corner in a direction opposite to the first regulation period by gate. The method of claim 18, wherein, if the magnitude of the reference voltage vector is less than one-half of the maximum magnitude, the following set of simultaneous linear equations is used to calculate residence times at the vertices of corner: (1) v * í 172 = mcosd = m-cos (d), msend = m-sin (d] 2 - V, dc (2) mc ms (3) ti = kl - dtpwm, t2 = k2 - dtpwm, t03 = k03 • dtpwm, where d = the angle from the reference voltage vector to the nearest axis dtpwm = the time of the regulation period by gate V = the reference voltage vector dc = the measured voltage 6 = an angle of the reference voltage vector with respect to one side of the triangular zone in which the reference voltage vector k03 = the residence time is present per unit in the local vertex kl = the residence time per unit in the first corner vertex 'k2 = the residence time per unit in a second corner vertex, t03 = the residence time in the local vertex ti = the time of residence at the first corner vertex t2 = the residence time at the second corner vertex. The method of claim 20, characterized in that it also includes, after the termination of a gate regulation period, determining whether to start a positive or negative gate regulation sequence, by predicting a net load to be injected into the gate. a neutral point for each alternative sequence as a sum of a product of a phase current, and the neutral residence time for each phase, and select the regulation sequence per gate based on the polarities of the predicted net charges, to correct any differences between the reference voltage vector and a measured voltage. The method of claim 20, wherein, if the magnitude of the reference voltage vector is greater than, or equal to one half of the maximum magnitude, then if the triangular zone has a side adjacent to one side of one of the twelve triangular zones, equations (1-3) of claim 10 are applied, with equation (2) being replaced with the following equation: 7T 7T TG 1 cos -. costs - 6 6 2 3 2 mcosd 7T 7T 1 TG k \ msind cos -.sen- - sen- 0 k2 1. 6 6 2 MB 1 or, if the triangular zone does not have a side adjacent to one side of one of the twelve triangular zones, equations (1-3) of claim 10 are applied, with equation (2) being replaced with the following equation: 7T TG 1 1 cos l- or mc ms 23. The method of claim 17, wherein each of the local vertices has a respective gate regulation state with an assigned polarity weight index, and the controller is adapted to respond to transient conditions by selecting a regulation state. by gate of a new local vertex, to minimize the change in the polarity weight index between a local vertex present and the new local vertex.