MXPA98007521A - Encoder and decoder - Google Patents

Abstract

The problems of pseudo-synchronization and out-of-synchronization caused by erroneous detection of synchronization codes of an encoder in which an error correction/detection coding and a synchronism restoring method using synchronization codes. There are provided a coding unit (212) for encoding a sequence of inputted multiplex codes (201) into error correction/detection codes comprising information bits and inspection bits;and a code sequence assembling unit (213) for assembling a sequence of output codes (205) by inserting a synchronization code into any of a plurality of periodically predetermined synchronization code insertion positions in the code sequence (201) and by arranging the information bits in arbitrary positions in the code sequence and the inspection bits in positions other than the synchronization code insertion positions in the code sequence (201).

Description

"CODING SYSTEM AND DECODING SYSTEM" TECHNICAL FIELD The present invention relates generally to a system for transmitting and / or storing the information through a medium of a high error ratio, such as a transmission line. More specifically, the invention relates to an appropriate encoding and / or decoding system for carrying out error correction / detection coding of a compressed code string obtained by high efficiency compression coding to transmit and / or store the compressed code string.

ANTECEDENT TECHNIQUE For example, in a system for carrying out highly efficient compression coding of an image and / or voice information to have a small information content for transmitting image information and / or compression encoded speech through a radio transmission line, such as a visual radio telephone, a portable information terminal and a digital television broadcasting system, is important the way - z - of transmitting the chain of code obtained with superior quality since the transmission line has a • high error ratio. In a case where the code chain is transmitted and / or stored through this means of a high error ratio, an error correction code, such as a Bose-Chaudhuri-Hocquenghem code (BCH), a code Normally Recommended (RS) and a convolutional code, it is frequently used as the means to reduce the ^ fc 10 error ratio. In addition, an error correction code, such as a checksum and a cyclic redundancy check (CRC), is used as the means to allow error correction on the receiving side. Error correction and / or error detection mentioned above is added excessive bits (redundancy) to the information transmitted and / or stored in accordance with a predetermined rule to examine whether the chain of • code transmitted and / or stored obeys the rule during decoding, to carry out the correction / error detection based on the results. However, in this method for encoding a code string obtained by high efficiency compression coding in error correction / detection codes to transmit and / or store the codes, there is a disadvantage as it is difficult to combine with a synchronous recovery technique to recover an output caused by a codeword error in • the transmission line / medium. As a synchronous recovery technique, a method 5 is often used to insert a uniformly decodable code called a synchronization code to resume decoding immediately after the synchronization code is detected when an output occurs. In order to produce a code word uniformly decodable synchronization code, • the code word must be combined with another code word in order not to form the same bit pattern as the synchronization code. However, in a correction / error detection coding, it is usually difficult form a code word to prevent a certain bit pattern from occurring. When the same bit pattern occurs as the synchronization code, a pseudo synchronization may occur by error detection of the synchronization code. 20 In order to avoid this problem, a method is used to prevent pseudo synchronization by detecting whether the same bit pattern exists as the synchronization code in the code string after performing the correction / error detection coding, inserting a bit simulated in the bit pattern in accordance with a v-ssße- a certain rule when the same bit pattern exists, and suppressing the simulated bit in the same rule in a system • decoding. However, in a case where the code string is transmitted and / or stored through a medium where the easy occurrence of errors, errors may occur in the inserted bit so that there is a problem as it can occur a new exit or a new pseudo synchronization. In addition, in a case where the coding of correction / error detection of a code string is • It takes place to insert a synchronization code there is also a problem since the coding efficiency is decreased since it is required to add many inserted bits to the code string in order to compensating an excess of information bit, for which error detection and / or detection coding is to be carried out, at the end portion of an interval • synchronization between adjacent synchronization codes. On the other hand, in order to improve the error correction / detection capability, the redundancy of the transmitted and / or stored information can be improved. However, if redundancy is improved, that increases the number of bits required to transmit the same information.

Therefore, if the correction capability is improved / -I "5 > • * detection of error, it is required to provide a transmission line with a higher transmission rate or • increases the number of bits of the information to be stored. Furthermore, if the transmission ratio and the stored capacity are equal, the amount of information, which can be transmitted and / or stored, decreases as redundancy is improved. In a case where the information of an image and / or voice is encoded by compression in a highly efficient manner for be transmitted and / or stored in order to add redundancy • to improve the resistance to error, coding by compression towards a smaller amount of information, must be carried out and the transmission and / or storage ratio is equal, so that the image quality and sound quality. Therefore, as a method to provide a smaller redundancy and a high resistance to error, there is a method called hierarchical coding. This is a method to improve the resistance to error using the The same means of redundancy as compared to when the error correction / detection code is used, classifying the information encoded by high efficiency compression according to the magnitude of the errors that influence the quality of the image and the quality of the image. sound using a correction code / error detection of a higher error correction / detection capability while having a high redundancy, for information under a large error influence, and using an error correction / detection code of lesser 5 redundancy while there is no correction capability / high error detection for information which is not greatly influenced by the error. For example, in a coding system, which is formed by combining the prediction compensated by movement with the orthogonal transformation and that is used frequently • for the high-efficiency compression coding of a dynamic image, that is, in a system for predicting motion compensation, a dynamic input image signal to orthogonally transform its residual prediction by means of a DCT (discrete cosine transformation) or similar, the correction / error detection codes of a high capacity correction / detection of • Error is used for motion vector information which greatly deteriorates the image quality if an error occurs, and for lower coefficients the orthogonal transformation coefficients of the residual prediction signal and the correction / error detection codes of a low error correction / detection capability are used for higher coefficients of the orthogonal transformation coefficients of the residual prediction signal, which are under a small influence of the error. • In order to achieve this hierarchical coding, it is required to switch the error correction / detection codes of the correction / error detection capabilities different than half of the output code string. With a method to switch the correction / error detection codes of different error correction / detection capabilities, there is a method to add a header information representative of the class • of error correction / detection codes to a code string. Figure 11 shows an example of a code string to which the header information is added to switch the error correction / detection codes.

In this example, two classes of error correction / detection codes FEC1 and FEC2 are switched. The headings 1101 to 1104 have information of • representative heading of the class of error correction / detection codes and the number of words of code. In a coding system, the code words, which are encoded for error correction / detection, are placed after the header information. In a decoding system, the header information is decoded and the codes of error correction / detection are decoded in accordance with the decoding of the header information. However, in the method for switching the error correction / detection codes by adding this header information, there is a problem as the number of bits of the code chain to be transmitted and / or stored is increased by adding the header information. In a case where the image and / or voice information is encoded by high compression efficiency to be transmitted and / or stored, if the number • of bits is occupied by the header information, the number of bits used for high-efficiency compression coding and the image and / or voice information is decreased so that the image quality and sound quality. As mentioned above, if the error correction / detection coding of the string • code in which the high-efficiency compression coding of the image signals is carried out dynamics and so on, is carried out, an optional bit pattern is produced. Therefore, in a case where the correction / error detection coding is combined with the synchronous recovery technique using a synchronization code capable of being decoded uniformly, there is a problem as pseudo synchronization is caused by error detection of the synchronization code. Also, in a case where the simulated bit is inserted to prevent pseudo synchronization, there is a problem because a new output or a new pseudo synchronization is caused by the error of the inserted bit. Further, in a case where error correction / detection coding of the code string is carried out and the synchronization code is inserted, it is conventionally required to use many inserted bits to compensate for an excess of information bits, for which encoding for detection and / or error correction will be carried out in the final portion of a synchronization interval between the adjacent synchronization codes so that there is a problem since the coding efficiency is decreased. In addition, in an encoding / decoding system for switching the correction / error detection codes of different error detection / correction capabilities by adding a header information, the number of bits to be transmitted and / or stored by adding the information of heading is increased. Therefore, in a case where an image and / or voice information is encoded by high efficiency compression to be transmitted and / or stored, there is a problem since the content of the information assigned to the image information and / or the • Voice is decreased to reduce image quality and sound quality.

EXHIBITION OF THE INVENTION Therefore, a main object of the present invention is to eliminate the problems previously mentioned and provide coding systems and • decoding that can prevent pseudo synchronization and an output due to the detection of the error of a synchronization code. Another object of the present invention is provide coding and decoding systems that prevent pseudo-synchronization and output due to error detection when an error correction / detection coding is combined with a synchronization recovery technique using a code of synchronization. A further object of the present invention to provide encoding and decoding systems that can decrease the number of inserted bits used in the final portion in a synchronization interval for improve coding efficiency, when the correction / error detection coding is combined with a synchronization recovery technique using a • synchronization code. A still further object of the present invention is to provide coding and decoding systems that can decrease the number of bits of a code string to which a header information representative of the error correction / detection coding class should be added. and that transmits and / or stores to improve the quality of • information. (1) A first coding system, in accordance with the present invention, comprises: a coding means for encoding a code string of entry into an error correction / detection code comprising an information bit and a check bit; and an assembly means of the code string for inserting a synchronization code into any of a plurality of code insertion positions of synchronization in an output code string, to place the information bit in an optional position in the output code string, and to place the check bit in a position other than the positions to insert the synchronization code in the chain of exit code in order to assemble the chain of exit code. F A first decoding system, in accordance with the present invention, comprises: means for detecting the synchronization code for detecting a synchronization code in a plurality of predetermined synchronization code insertion positions based on a chain of code , which is coded to an error correction / detection code comprising a bit of information and one check bit; a half of • resolution of the code string to resolve the code string in order to extract the information bit from the error correction / detection code and the error correction / detection code check bit placed in a position other than the synchronization code insertion positions; and a decoding means for receiving the information bit and the check bit • extracted by the resolution medium of the code string to decode the correction / detection code error. In this way, in the first coding / decoding system, the synchronization code exists only at the insertion position of the predetermined synchronization code in the code string of the synchronization code. , and the check bit of the error correction / detection code exists in a position other than the insertion position of the synchronization code. For the • both, even when the same bit pattern as the synchronization code is contained in the check bit, there is no probability that it is detected erroneously and that the same bit pattern as the synchronization code is a synchronization code . Therefore, since it is not required to use a special error correction / detection code to prevent a specific bit pattern for By inserting a bit to prevent a synchronization code after the correction / error detection coding, the degree of freedom for the error correction / detection code used can be increased. Also, since there is no likelihood that a new synchronization detection error due to the insertion of an error in an inserted bit, it is possible to improve the resistance to errors. • (2) In a second coding system in accordance with the present invention, a means of transformation of the code chain to the first coding system. The code string transformation means transforms an input code string other than the synchronization codes placed in a plurality of code insertion positions of the code.

The synchronization is predetermined in an output code string so that a large distance from the synchronization code is equal to or greater than a predetermined value. The code string transformed by the code string transformation means is allowed to the encoding means to be encoded in an error correction / detection code comprising an information bit and a check bit. In a second decoding system in accordance with the present invention, the means of transformation of the code chain to the first decoding system. The transformation means of the code chain transforms a code string other than the synchronization code which exists in a synchronization code insertion position and which is transformed in a manner that a large distance from the synchronization code in the code chain decoded by the decoding means is equal to or greater than a value • default, towards the original code string. In this way, in the second system of coding / decoding, the coding system carries out the transformation process in such a way that the large distance from the synchronization code with respect to a bit string placed in the insertion position of the synchronization code is equal or greater than a predetermined value, and the decoding system performs the inverse transformation. Therefore, since the same bit pattern as the code of • synchronization is not contained in the bit string, it is possible to prevent the detection of the error of a synchronization code. In addition, if the transformation is carried out in such a way that the large distances between the synchronization code and the other code chains are greater, the synchronization code can be distinguished from the other code chains even when an error is mixed. in the code strings so that you can decrease the • probability of error detection of the synchronization code due to errors. Since this process of inverse transformation / transformation is carried out only in the insertion position of the synchronization code, the upper part is smaller than those in conventional methods to carry out the process of • Inverse transformation / transformation through the entire code chain. Also, in the chain of supported code To the coding system, it is not required to carry out the transformation process in order not to produce the same bit pattern as the synchronization code, and it is not required to use a special code string. In particular, in a case where a length coding system Variable for switching and using different codeword frames is used as an input of this coding system, and a codeword frame is prepared so as not to produce the same pattern as the synchronization code in the coding system. of variable length, there is a problem as it decreases the coding efficiency. However, the second encoding / decoding system can eliminate this problem. (3) A third coding system, in accordance with the present invention, comprises: a coding means for encoding an input code string to an error correction / detection code; the synchronization code insertion means for inserting a synchronization code in the code string; and a determining means for determining the number of bits of an information to be encoded towards an error correction / detection code immediately before the synchronization code in the code chain, wherein the coding means causes a correction code. / error detection immediately before the synchronization code is a degenerate code, which degenerates adaptively on the basis of the number of bits determined by the means of determination.

A third decoding system according to the present invention comprises: a decoding means for decoding a code string, which is coded to an error correction / detection code and to which a synchronization code is inserted; a synchronization code detection means for detecting the synchronization code in the code chain; and a means of determination to determine the number of bits of information that is codes towards an error correction / detection code • immediately before the synchronization code in the code string detected by the synchronization code detection means, wherein the decoding means is decoded by identifying whether the code of correction / error detection immediately before the synchronization code is a degenerate code based on the result determined in the middle of • determination. In this way, in the third system of Encoding / decoding, since a degenerate code is used that degenerates to a number of bits required to encode the information bit remaining in the end portion of a synchronization interval as the error correction / detection code immediately before the synchronization code, it is not required to use many inserted bits in order to compensate the rest of the information bit in the final portion of the interval of • synchronization so that coding efficiency can be improved. 5 (4) A fourth coding system in accordance with the present invention, comprises: a coding means for encoding a code string containing classes of input information to an error correction / detection code; and a switching medium to switch the class of a correction / detection code • Error in accordance with the input information classes in the code chain. A fourth decoding system, in accordance with the present invention, comprises: a means decoding to decode a code string, which is encoded to a different class of error correction / detection code of the information class to generate the original information; and a means to determine the kind of correction / detection code of error on the basis of the kind of information generated by the decoding means, to inform the decoding means. In this way, in the fourth coding / decoding system in a case where the coding / decoding is carried out by switching the error correction / detection code in accordance with the information class, the coding system switches • the correction / error detection code in accordance with the information class of the 5-input code string, and the decoding system determines the error correction / detection code class based on the decoded information to carry out the same switching as that of the coding system. Therefore, it is not necessary to use a header information representative of the correction code class / • error detection unlike conventional systems so that it is possible to remove the top due to the header information. (5) A fifth coding system for according to the present invention comprises: a means of code string transformation to transform an input code string other than synchronization codes that are placed in a plurality of synchronization code insert positions predetermined in an output code string and in intervals of a predetermined number of bits before and after the insertion positions of the predetermined synchronization code in an output code string so that a large distance from the code of synchronization is equal to or greater than a predetermined value; encoding means for encoding a code string transformed by the means of • code string transformation to an error correction / detection code comprising a data bit and a check bit; and a code string assembly means for inserting a synchronization code into any of a plurality of predetermined synchronization code insertion positions in the output code chain, for F 10 placing the information bit in an optional position in the output code chain, and to place the check bit in a position other than the insertion positions of the synchronization code in the output code string in order to assemble the code string of departure. A fifth decoding system in accordance with the present invention, comprises: a synchronization code detection means for detecting a synchronization code in an insertion position of predetermined synchronization code and in a range of a predetermined number of bits before and after the insertion position of the predetermined synchronization code, on the basis of a code string that is encoded to a correction / detection code. error comprising an information bit and a check bit and towards which the synchronization code; the means of solving the code chain to solve • the code string for extracting the information bit from the error correction / detection code and the check bit from the error correction / detection code placed in a position other than the synchronization code insertion position; encoding means for receiving the information bit and the checked bit extracted by the resolution means of the string of code to decode the code of • error correction / detection; and a means of transforming the code chain to transform a code string other than the synchronization code, which is transformed so that a large distance from the The synchronization code in the decoded code chain by means of the decoding means is equal to or greater than a predetermined value and exists at the insertion position of the synchronization code and in a range of a certain number of bits before and after of the synchronization code insertion position, towards the original code string. In this way, in the fifth coding / decoding system, the input code string is transformed into the code insertion interval of the code.

Synchronization as well as in the range of the predetermined number of bits before and after the insertion interval of the synchronization code so that the large distance is equal to or greater than the predetermined value, and the decoding system carries out the inverse transformation of the string of code so that the same bit pattern as the synchronization code is not contained in this interval. Therefore, even when transmitting / storing a coded bit string through a transmission line or a storage medium to cause a bit loss where a bit part is lost, and an addition of bits where If an excess of bits is added, the synchronization code can be distinguished from the other code strings if the number of bits lost / added is equal to or less than the predetermined number of bits, so that the decoding system can carry out synchronization detection correctly. (6) A sixth coding system, in accordance with the present invention, comprises: a multiplexing means for multiplexing the classes of compressed codes, which are obtained by compression coding, of an input signal in order to produce a chain of code multiplexed; and a code string assembly means for supporting the multiplexed code string for assembling an output code string, wherein the means for assembling the code string inserts a synchronization code into any of a plurality of code insertion positions. periodically predetermined synchronization code in the output code string 5. In this case, in order to insert the synchronization code into any of the plurality of periodically predetermined synchronization code insertion positions in the code string of output, the assembly medium of the code string • inserts a fill bit in the output code string or periodically determines the plurality of synchronization code insertion positions in the output code string and inserts an information (an information indicator) representative of the limit of the multiplexed code chain for inserting the synchronization code into any of the plurality of insertion positions of the synchronization code. In this way, the synchronization code can be inserted only at any of a plurality of periodically predetermined synchronization code insertion positions. The prefill bit is preferably a code that can be decoded uniformly in a direction towards back of the exit code string. Therefore, if the decoding system compares the final coding position of the code string immediately before • of the fill bit with the starting position of the fill bit, it is possible to easily detect an error in the input code string. In addition, the large distances of the padding bit from the synchronization code and the portion thereof preferably are equal to or greater than a predetermined value. In this way, there is an advantage in the probability that a pseudo synchronization will occur. A sixth decoding system in accordance with the present invention comprises: a synchronization code detecting means for detecting a synchronization code in an output code string; a medium of demultiplexing to demultiplex on the basis of the position of the synchronization code detected by the means of detecting the synchronization code from the • string of input code, to produce a chain of compressed code; and a means of decoding for Decoding the compressed code to send a reconstructed signal, wherein the synchronization code detection means detects the synchronization code in a plurality of periodically predetermined synchronization code insertion positions in the chain of the entry code.

In this way, in the case of a sixth coding / decoding system, since the coding system inserts the synchronization code in the multiplexed code chain, which is obtained by multiplexing 5 classes of compressed codes, only in the insertion positions of the synchronization code periodically predetermined, the decoding system can carry out synchronization detection only at the insertion positions of the synchronization code of the synchronization code. so that the number of synchronization code detection processes can be decreased as compared to conventional systems to insert a synchronization code into a code string in an optional position. In addition, in accordance with the decrease in number of synchronization code detection processes, it is possible to decrease the probability that f a pseudo synchronization occurs due to bit string admitted in the decoding system changed to the same bit system as the synchronization code due to a bit error. Therefore, in accordance with the present invention, it is possible to decrease the number of events that can occur from the pseudo synchronization so that the amount of processing in the synchronization code detection can be decreased. (7) In a seventh coding system in accordance with the present invention, a means of • chain code transformation to the sixth coding system. The code transformation means of code 5 transforms a code string other than the synchronization code which is placed at the insertion position of the synchronization code in the output code string so that a large distance from the code of synchronization is equal to or greater than one value default. • A seventh decoding system in accordance with the present invention, further comprising: a means of code string transformation to transform a code string other than the code of synchronization that is transformed so that a large distance from the synchronization code is equal to or ter than a predetermined value at the insertion position of the synchronization code in the input code string, towards the original code string. Therefore, in the seventh encoding / decoding system, in addition to the construction of the sixth encoding / decoding system, the insertion of the bit in view of the synchronization code error ie the transformation of the large distance of the The bit string placed in the position of inserting the synchronization code from the synchronization code is carried out in such a way that the same bit pattern as the • synchronization code is contained in the string of the bit code. Therefore it is possible to ensure that the error detection of the synchronization code does not occur with respect to an error of an assumed bit number or less in order that it is possible to decrease the probability of error detection of the synchronization code. In addition, in the present invention, the code of Synchronization is a string of code that is inserted into a code string for synchronization recovery and that can be decoded uniformly. For example, if a code string to insert a synchronization code is a multiplexed code string that is obtained By multiplexing a plurality of compressed code classes obtained by compression coding of an admitted picture signal for each frame, the synchronization code is a code representative of a division of a coding frame, divisions of the plurality of compressed code classes and other divisions. As described above, according to the present invention, the following advantages can be obtained: j ^ -xg '(1) According to the first coding / decoding system, synchronization codes are inserted only at the insertion positions of the synchronization code placed at regular intervals, 5 and the check bits of the correction code / Error detection are shifted in order to exist in positions other than the insertion positions of the synchronization code. Therefore, even when the same bit pattern occurs as in the synchronization code • 10 in the check bit, the same pattern and the synchronization code does not occur at the insertion position of the synchronization code and in theory there is no chance of synchronization being detected. Also, if inserting the bit into a string of code in the position of insertion of the synchronization code is carried out in order not to produce a pseudo-synchronization code, it is possible to eliminate the difficulty W to form a codeword in order not to produce the same bit pattern of the bit of synchronization. (2) In accordance with the second coding / decoding system, in addition to the construction of the first coding system, the insertion of the bit is carried out in view of the synchronization code, that is, the transformation process is brought to out of so that the large distance from the synchronization code is equal to or ter than a predetermined value with respect to the bit string placed in • the insertion position of the synchronization code, and the decoding system performs transformation 5 backwards so that the bit code does not contain the same bit pattern as the synchronization code. Therefore, it is possible to ensure the prevention of the error detection of the synchronization code that may occur due to the errors of the assumed number of bits or less, of • 10 way that the probability of error detection of the synchronization code is decreased. Also, if this transformation is carried out, it is possible to distinguish the synchronization code from other code strings even when an error is mixed in the code string that the probability of error detection of the synchronization code can be decreased due to errors. In addition, since the coding of • Error correction / detection is carried out after the code word is transformed by the bit insertion, error protection is carried out for the inserted bit. Therefore in comparison with conventional systems to carry out the insertion of bits after the correction / error detection coding, the probability of an error occurring is decreased in the inserted bit. Also, since the bit insertion is carried out only at the insertion position of the synchronization code, the increase in the number of w codes due to bit insertion is less than in conventional systems for carrying out the insertion. 5 bit through the entire code chain, and in this way the coding efficiency is improved. (3) According to the third coding / decoding system, since the error correction / detection code immediately before the synchronization code is a degenerate code, it is possible to decrease the number of bits inserted to compensate the rest of the code. bit of information in the portion immediately before the synchronization code in order to improve coding efficiency, compared to the conventional coding systems. (4) According to the fourth system of f coding / decoding, the coding system uses the rule of multiplexing in the high efficiency compression coding system such as a image and voice and with commutation of the error correction / detection code according to the information class of an input code string, and the decoding system determines the error correction / detection code class on the basis of the decoded information to carry out the same switching and that of the coding system. Therefore, it is not necessary to add the information of • header representative of the error correction / detection code class, and it is possible to assign the number of bits to the high efficient compression coding such as the image and the voice so that it is possible to improve the quality of the information , such as the quality of the image and the quality of the sound. (5) According to the fifth system of encoding / decoding, the coding system • transforms a string of input code so that a large distance in an insertion range of the synchronization code as well as a large distance in a range of a predetermined number of bits before and after the insertion interval of the synchronization code are equal to or greater than a predetermined value, and the decoding system carries out the inverse transformation of the input code string so that it is possible to prevent the same pattern of bits that the synchronization code is contained in this interval. Therefore, even when a bit string coded through a transmission line and / or a storage medium that can cause a bit loss to lose a part of the bit is lost and an addition bit to add an excess bit is transmitted / stored, * • »• ** - '232 - If the number of missing / added bits is equal to or less than a predetermined number of bits, it is possible to distinguish • a synchronization code of other code chains so that the decoding system can correctly perform synchronization detection. (6) According to the sixth coding / decoding system, since the coding system inserts the synchronization codes only in the insertion positions of the coding code. synchronization periodically predetermined in a chain • of multiplexed code, which is obtained by multiplexing classes of compressed codes, the decoding system can carry out synchronization detection only in the insertion positions of the synchronization code so that the number of synchronization code detection processes can be decreased compared to conventional systems for inserting synchronization codes into a code chain at optional positions. In addition, since the probability of a pseudo-synchronization occurring by varying the bit string admitted to the decoding system in the same bit pattern as the synchronization code is decreased in accordance with the decrease in the number of processing processes.

By detecting synchronization code, it is possible to prevent pseudo-synchronization according to the present invention in a manner that decreases the amount of processing w for detecting the synchronization code. (7) According to the seventh coding / decoding system, in addition to the construction of the sixth encoding / decoding system, the insertion of bit in view of the error of the synchronization code, ie the transformation of the large distance of the F 10 bit string in the position of inserting the synchronization code from the synchronization code is carried out so that the same bit pattern as in the synchronization code is not contained in the bit string. Therefore, it is ensured that the error detection of the The synchronization code does not occur with respect to errors of the assumed number of bits so that the probability of error detection of the code numbers can be decreased.

F synchronization.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a functional diagram of the first and second preferred embodiments of a dynamic image coding system in accordance with present invention.

Figure 2 is a diagram illustrating a multiplexer rule in a multiplexer of the • dynamic image coding of Figure 1. Figure 3 is a functional diagram of an output coding unit of the dynamic image coding system of Figure 1. Figure 4 is a diagram illustrating an example of a string code output of the dynamic image coding system of Figure 1. 10 Figure 5 is a diagram illustrating an example • a synchronization code. Fig. 6 is a functional diagram of an error correction / detection switching coding part in the output coding unit of Fig. 15 3. Fig. 7 is a functional diagram of a code string assembly unit of FIG. the unit of • output coding of Figure 3. Figure 8 is a functional diagram of the first and second preferred embodiments of a dynamic image decoding system in accordance with the present invention. Figure 9 is a functional diagram of an input decoding unit of the dynamic image decoding system of Figure 8.

Figure 10 is a functional diagram of a code string resolver of the unit of • Input decoding of Figure 9. Figure 11 is a diagram illustrating an example of a code string obtained by a conventional error correction / detection switching coding system. Figure 12 is a diagram illustrating an example of a synchronization code where an error is caused by the addition / loss of a bit (s) in the • transmission line, to explain the second preferred embodiment of the present invention. Figure 13 is a diagram explaining the operation of a bit insertion unit of Figure 3 in the second preferred embodiment. Figure 14 is a diagram explaining the operations of a synchronization detector and an inserted bit removal unit of Figure 9, in the second preferred embodiment. Figure 15 is a diagram illustrating an example of a code string wherein synchronization protection is carried out using a frame length information in the first and second preferred embodiments.

* •• -, - ** - - «- Figure 16 is a diagram illustrating another example of a code string wherein f-synchronization protection is carried out using a frame length information in the first and second modes preferred. Figure 17 is a diagram illustrating a further example of a code string wherein synchronization protection is carried out using a frame length information in the first and second f 10 preferred embodiments. Figure 18 is a functional diagram of the third and fourth preferred embodiments of a dynamic image coding system in accordance with the present invention. Figure 19 is a functional diagram of an output coding unit of the third preferred embodiment of a dynamic image coding system in accordance with the present invention. Figure 20 is a diagram illustrating an example of an output code string of the third preferred embodiment of a dynamic image coding system in accordance with the present invention. Figure 21 is a functional diagram of a third and fourth preferred embodiments of a dynamic image decoding system, in accordance with the present invention. • Figure 22 is a functional diagram of an input decoding unit of the third preferred embodiment 5 of a dynamic image decoding system in accordance with the present invention. Figure 23 is a functional diagram of an output coding unit of the fourth preferred embodiment of a dynamic image coding system, 10 in accordance with the present invention. • Figure 24 is a functional diagram of an input decoding unit of the fourth preferred embodiment of a dynamic image decoding system, in accordance with the present invention. Figure 25 is a functional diagram of an example of an output code string of the fourth preferred embodiment of an image coding system • dynamic, in accordance with the present invention. Figure 26 is a diagram illustrating a multiplexer rule 20 in a multiplexer of a dynamic image coding system. Figure 27 is a functional diagram of the examples of the output code strings of the fifth preferred embodiment of a dynamic image coding system, in accordance with the present invention.

Figure 28 is a diagram illustrating other examples of the rules of multiplexing in a multiplexer of • a dynamic image coding system. Figure 29 is a diagram of a chain of output code where the synchronization codes are processed when the multiplexing shown in Figure 28 is carried out. Figure 30 is a code box for explaining the examples of the bits of fillers used for the present invention. • Figure 31 is a diagram explaining a process in the decoding system when the filler bits of Figure 30 are used. Figure 32 is a diagram that explains the characteristics of the filler bits in Figure 30. Figure 33 is a diagram of the examples of the output code strings when the interval of «JF insertion of the synchronization code is shorter than a synchronization code. Figure 34 is a diagram of examples of the use of synchronization codes of different lengths. Figure 35 is an exemplary diagram of the output code strings of the sixth preferred embodiment of a dynamic image coding system, in accordance with the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION Referring now to the accompanying drawings, preferred embodiments of the present invention will now be described.

(First Preferred Modality) Figure 1 is a functional diagram of the first preferred embodiment of a coding system dynamic image, in accordance with this • invention, wherein a coding system having an error correction / detection code switching function of the present invention is combined with a high compression coding system efficiency using an adaptive compensatory prediction in motion and a discrete cosine transformation coding that serves as a coding class of ^ P orthogonal transformation. A coding system comprises the combination of an adaptive prediction compensated in motion and a discrete cosine coding is detailed in e.g. Literature 1"International Standard of Multimedia Coding" by Hiroshi Yasuda, Maruzen (June 1991). Therefore, only the operation of the coding system will be described schematically.

In addition it will be assumed that the information bits are separated from the detection bits in an error correction / detection code similar to the BCH code. • In Figure 1, with respect to an input dynamic image signal 131 that serves as an object to be coded 5, which is supported for each frame, first a compensated adaptive prediction in motion for each small region is carried out such as a macroblock. That is, in an adaptive predictor 101 compensated in motion, a vector of movement between 0 10 input dynamic image signals 131 and an image signal which is stored in a frame memory 102 and which has been encoded and / or decoded locally is detected and a prediction signal 132 is produced by the motion compensated prediction the basis of motion vector. In this moving-compensated predictor 101, an appropriate prediction mode for coding is selected from the prediction coding f compensated in motion and the coding between the frame (prediction signal = 0), which directly encodes the input dynamic image signal 131 to produce the corresponding prediction signal 132. The prediction signal 132 is admitted in a subtraction apparatus 103, wherein the prediction signal 132 is subtracted from the input dynamic image signal 131 for send a residual prediction signal 133. The residual prediction signal 133 is transformed into discrete cosine (DCT) in a discrete cosine transformer 104 for each • block that has a predetermined size in order to produce a DCT coefficient. The DCT coefficient is quantized by means of a quantizer 105. The data of the DCT coefficient quantized by the quantizer 105 is divided into two parts, one of which is encoded by variable length by means of a variable length encoder 106 first. , and the other of which is quantified inversely by means of an investment quantifier 107 • which is to be transformed into inverse discrete cosine (inverse DCT) by means of an inverted discrete cosine transformer 108. The output of the reverse discrete cosine transformer 108 is added to the signal 132 of prediction in an adder 109 to produce a locally decoded signal. This locally decoded signal is stored in the memory 102 of the frame. • On the other hand, the information in the prediction mode and the movement vector that have been determined by adaptive predictor 101 compensated in motion is encoded in variable length by means of a second encoder 110 of variable length. The variable length codes (compressed codes) sent from the first and second variable length encoders 106 and 110 are multiplexed by means of a multiplexer 111 to be sent as a multiplexed code string 201.

• The multiplexer 11 sends the multiplexed code string 201, a 5 FEC class identification signal 202 representative of the class of an error correction / detection code corresponding thereto and a synchronization code insertion request signal to request that a synchronization code be inserted. The code string 202, the identification signal 202 of the FEC class and 203 insertion request signal • synchronization code are supported in an output coding unit 200 for switching and encoding the code string 202 of error correction / detection code classes of different capacities of correction / error detection in order to produce a string 205 of final output code. In this preferred embodiment, the output coding unit 200 • corresponds to a coding system in accordance with the present invention. Figure 2 is a diagram illustrating a multiplexing stream in multiplexer 111. Multiplexing is carried out for each coding frame. First a synchronization code 301 is multiplexed. When the synchronization code 301 is multiplexed, the system 200 The synchronization code insertion request coding is sent from the multiplexer 111, and the coding system 200 learns that the multiplexed code word is a synchronization code. Then, the image headers 203 representative of the different encoding modes of the coding frame are multiplexed to make the code string 201 multiplexed. Then, a prediction mode information 303 representative of a prediction mode in an adaptive compensatory MC predictor in motion in each region is multiplexed, and a motion vector information 304 and the DCT coefficient 305 of a predictive residual signal (a which will be referred to below as the "residual DCT coefficient") are multiplexed. When the header 302 of the image, the prediction mode information 303, the motion vector information 304 and the residual DCT coefficient 305 are multiplexed, the FEC class identification signals 202 representative of the correction code class / Error detection that correspond to them are sent. The correction / detection error codes of high correction / detection capabilities are used for the header 302 of the image, the prediction mode information 303 and the motion vector information 304 which greatly deteriorate the quality of the image and mix an error On the other hand, if an error is mixed in the residual DCT coefficient 305, it is possible to prevent the quality of the image from deteriorating greatly by detecting the error and by grading the residue so that it is zero. Therefore, the error correction capability is not required to be high, and only error detection can be carried out. Figure 3 is a functional diagram of an output coding unit of Figure 1. The unit 200 of output coding comprises a bit insertion unit 211, an error correction / detection switch encoder 212 and a code string assembly unit 213. Figure 4 shows an example of an exit code string 205 produced by the output coding unit 200. In Figure 4, PSC represents a synchronization signal, PH represents an image header, a MODE represents a prediction mode information, MV represents a motion vector, CHK represents a check bit of a correction code / error detection, DOEF is a residual DCT coefficient and STUFF represents a fill bit (one bit inserted). This string 205 of exit code has the following characteristics. (1) The synchronization PSC codes are insert in only the synchronization code insertion positions indicated by the arrows that are placed at regular intervals (each bits of sync period).

The length of the sync period is scaled to be greater than the length of the PSC synchronization code and the maximum length of the CHK check bit. The check bit CHK is shifted so as to be placed immediately before the insertion position of the synchronization code. (2) The correction / error detection code in the final part of a table is a synchronization period between a synchronization PSC code and the next PSC, it is a degenerate code to encode only the finally remaining information bit, and the padding bits STUFF having the number of bits required to move the check bit CHK (CHK6 in the example of Figure 4) are inserted. (3) The identification signal of the FEC class is representative of the class and number of correction / error detection codes does not exist in the output code string 205 of Figure 4. In this output code string 205 , since the check bit CHK is shifted as described in (1), no check bit CHK enters the insertion positions of the synchronization code which is indicated by the arrows, so that there is no probability of occurrence a pseudo synchronization by means of the CHK check bit. In addition, in a case where the correction / error detection coding of the • End of the frame is carried out as described in (2), it has been required to insert many inserted bits (simulated bits 5) in the prior art. However, in the preferred embodiment, since the end of the frame has the degenerate code, the number of inserted bits may be small. In addition, as described in (3), since the header information representative of the class and number of correction code / error detection are • contained in the string 205 of the exit code, the number of codes is not increased. By comparing the multiplexed code string 201 of Figure 2 which is sent from the multiplexer 111 with the output code string 205 of FIG. 4, the construction and operation of the output coding unit 200 of FIG. 3 to produce this string 205 of • exit code will be described in detail below. When the synchronization code 301 is multiplexes in the multiplexer 111, the synchronization code insertion request signal 203 is sent as described above. For example, as shown in Figure 5, the synchronization code 301 comprises "0" of sync bits O len, a "1" of a bit, and a "xxxxx" of the sync bits nb len representative of the class of the synchronization code 301. The output coding unit 200 sends a synchronization code • (PSC) which serves as an output code string 205 from the assembly unit 213 of the code string 5 when it receives the synchronization code 301 and the synchronization code insertion request signal 203 from the multiplexer 111. As shown in Figure 4, since the synchronization code 301 can be inserted only in the insertion positions of the synchronization code • placed at intervals of the sync period bits, when the end of the produced output code string 205 is not placed in the insertion position of the synchronization code, a STUFF fill bit of so that the synchronization code 301 is placed in the insertion position of the synchronization code as will be described later. ^ ßf After the synchronization code 301 is sent to the output code string 205, the header 302 of the image, information 303 of prediction mode, movement vector information 304 and residual DCT coefficient 305 are coded in the following manner. The insertion of the bit in the multiplexed code string 201 sent from the multiplexer 111 is carries out to prevent a pseudo synchronization so that The t_! > __ ?. . áSEi-ií __ •• *? r "* ~ ¡* faith" ¡f- • does not occur in the bit insertion unit 211. That is, if the same bit pattern exists as the code word • of the synchronization code 301 in the exit code string 201, the bit insertion is performed if it is necessary in order to prevent the synchronization code 301 from being able to be decoded uniformly. For example in a where the synchronization code 301 is a code word having continuous "O" bits of sync O len as shown in the Figure 5, if a "1" is inserted so that the "0" of the sync bits O len or more do not continue in the code strings other than the synchronization code 301, it is possible to prevent a pseudo occurrence synchronization. As described above, since the synchronization codes 301 are inserted only in the insertion positions of the synchronization code, the insertion operations of bits to prevent • Pseudo-synchronization occurs, they can be carried out only in the insertion positions of the code synchronization. Therefore, a counted value 221 representative of the total number of bits of the output code strings 205 produced is sent from the code string assembly unit 213 and is determined by the bit insertion unit 211 on the basis of the value 221 counted if bit insertion is required. .rsrzyzÉ?,?.

Assuming the counted value 221, that is, the total number of bits of the output code strings 205 • produced is total len, the number of "1" in the chain 201 multiplexed code is counted in a range in where O < total len mod sync period < sync O len. If there is no "1" in this range, a "1" of a bit is inserted. A mod B represents a remainder when A is divided by B. Also in order to decrease the probability of error detection in the synchronization code 301, the bit insertion can be carried out in the following manner. In order to detect the synchronization code 301 even when the n-bit error is mixed in the code 301 of In order to synchronize, it is required to determine that a code word having a large distance of n or less than the true synchronization code in a B unit "encoding input of a dynamic image decoding system as described below is a synchronization code. However, if this determination is carried out while the code strings other than the synchronization code 301 remain as they are, the bit patterns having a large distance of n or less from the code of synchronization may still exist in the strings of code íá '^ ja ». other than the synchronization code 301. Therefore, if this is placed in the code insertion position of • synchronization can be determined in a wrong way which is the synchronization code 301. 5 Therefore, inserting bit into the string 201 of multiplexed code is carried out by means of a bit insertion unit 211 so that the code strings are not the synchronization codes placed in the insertion positions of the synchronization code in the multiplexed code chain 201 are transformed to * J have a large distance of 2 * n + 1 or more from the synchronization code 301. Sfically, the number of "1" (which is assumed to be nO) is counted in a range where 0 < total len mod sync period 15 < sync 0 len - (2 * N + 1). If nO is equal to or less than n * n + 1, the "1" of 2 * n + 1 -nO bits are inserted in the string 201 of the multiplexed code. ^ In this way, a string 222 of code where the insertion of bits is carried out by means of the unit 211 bit insertion together with the identification signal 202 of the FEC class representative of the error correction / detection code class is supported in the error correction / detection code switching coding part 212.

Figure 6 is a functional diagram of a correction code switching coding part 212 / • error detection. A latching circuit 603 is a circuit for latching a FEC class 5 identification signal 202. When the output of a synchronization code from the multiplexer 111 to the multiplexed code string 201 is completed to stop the output of the synchronization code insertion request signal 203, the latching circuit 603 engages the FEC class identification signal 202 for • supplying a hooked signal 623 to error correction / detection encoder 604. An error correction / detection coder 604 performs correction / detection coding Error code code 222, which is sent from a bit insertion unit 211 on the basis of the latched signal 623 to send an information bit 631 and a check bit 632. In addition, when the correction / error detection coding of a block is completed, the The correction / error detecting encoder 604 sends a latching signal 625 indicating the latching of the next identification signal 202 of the FEC class to the latching circuit 603. The 603 circuit is hooked, hook in accordance with the latch indicator signal 625 to supply the signal 623 engaged to the error correction / detection coding 604. The aforementioned operation is repeated in the output coding unit 200 so that the error correction / detection coding of the inserted bit code string 222 sent from the bit insertion unit 211 is carried out while switches the error correction / detection code in the correction / error detection encoder 212 over the basis of the identification signal 202 of the class of • FEC sent from the multiplexer 111. Since the identification signal 202 of the FEC class is engaged by the latching circuit 603 only at the moment a block is completed, the same codes apply error correction / detection is made before this switching point. For example, in a case where the header 302 of the image uses a FEC1 code of • correction / error detection and information 303 of prediction mode uses a correction code FEC2 / error detection, if the number of bits of the header 302 of image is smaller than the number of information bits of a block of FEC1, FEC1 is used as the correction code / error detection of information 303 of subsequent prediction mode until the number of bits of the image header 302 reaches the number of information bits of the FEC1. Figure 7 is a functional diagram of a code string assembly unit 213 of Figure 5 3. The code string assembly unit 213 comprises a counter 701 for counting the number of bits of the exit code string 205 , a buffer 702 for temporarily storing the check bit 632 and the number of bits thereof, a switch 703 for to switch the string 205 of exit code and a controller • Switch 704 for controlling switch 703. Counter 701 is readjusted to be of a sync code length length sync len when signal code insertion signal 203 synchronization is supported and counts in sequence from the next bit of the synchronization code until the next synchronization code is supported. He • switch 703 is operated such that bit 631 of information is sent before bit 632 is admitted initial check after the synchronization code is supported. When it supports the check bit 632, it is stored in the memory 702 and the bit number thereof (the number of check bits 711 is sent from the buffer 702 to the controller 704). of the switch.

The controller 704 of the switch controls the switch 703 on the basis of the check bit number 711 and the counter value 221 of the counter 701 so that the check bit is shifted so as to prevent the check bit 632 from being sent to the insertion position of the synchronization code as described above. For example, assuming that value 221 counted is bit_count and number 711 of the check bits is check_len, bit 631 of information is send when the bit_count mod sync_period < sync_period - • check_len, and a check bit 713 is stored in buffer 702 is sent when sync_period check_len < total_bits mod sync_period < sync_period Then, the aforementioned process is repeated while information bit 631 and check bit 632 are allowed. As described above, since ^ the output encoding unit 200 uses a degenerate code as an error correction / detection code in the final portion of a frame carries out the bit insertion to move the check bit, performs the operation different from the usual operations of the portions other than the final portion. That is, when the output of the code string 201 is completed multiplexed in a frame, the multiplexer 111 sends a synchronization code insertion request signal 203 for the next frame. In response to &'; this, the error correction / detection code 604 in the correction switching / error detecting coding part 212 of Figure 6 performs the correction / error detection coding using a degenerate code assuming a shortage of bits 631 of error correction / detection code information is a predetermined bit pattern sent from an inserted fc 10 generator 705. This bit pattern can be a bit pattern where all the bits are "1" or "0", or it can be a specific repeated pattern such as "0101 ...". These offset inserted bits are not sent to the information bit 631. In the code string assembly unit 213 of Figure 7, after the information bit 613 is sent to the end or end, the switch 713 is • switches from the bit generator 705 to the input, and the inserted bits are inserted so that bit 713 of The check stored in the buffer 702 is placed immediately before the next synchronization code. Assuming that the counted value 221 of the counter 701 is total_len when the last bit 631 of information of a frame is sent and that the number of bits 632 checks finally sent is last chick_len, the number of inserted bits stuffing_len is stuffing_len = sync_period - last_check_len - (total_len mod sync_period).

• Furthermore, in a case where a degenerate code is not used, it is required to insert (into_len - last_into_len) bits, that 5 is a shortage of the last bit of information last_into_len from the usual information bit into_len, and to insert a shortage for move the check bit. Therefore, it is required to insert more bits inserted of those in the use of the degenerate code, through into__len 10 last_into_len + (into_len - last_into_len) mod sync _period. Therefore, after the code string assembly unit 213 sends the bits 631 the information of the inserted bits to the string 205 of exit code through the switch 703, and finally send the check bit 713 to the exit code string 205. The first preferred embodiment of the dynamic image decoding system in accordance with The present invention will be described below. Figure 8 is a functional diagram of a dynamic image decoding system corresponding to the dynamic image coding system of Figure 1. The output code string 205 sent from the dynamic image decoding system of Figure 1 passes through a transmission / storage system to be admitted in the input coding unit 800 as the input code string 205 '. In this preferred embodiment, the input decoding unit 800 corresponds to the decoding system of the present invention. The input decoding unit 800 switches the error correction / detection codes on the basis of an identification signal 802 of the class of • 10 FEC representative of the class of an error correction / detection code sent from a demultiplexer 811, downstream to output to a code string 801, which has been encoded by error correction / detection, a signal 803 of detection of synchronization code and an error detection signal 804. The demultiplexer 811 receives the code string 801, the synchronization code detection signal 803 and the signal detection signal 804. • error in order to output separately a residual predictive signal 841 and an information code 842 of adaptive prediction compensated in movement. The residual prediction signal 841 and the code 842 of adaptive prediction information compensated in motion are sent to a first and second variable length decoders 806 and 810, respectively. For a residual DCT coefficient 831 decoded by the ___ 5.l3l__ UgUm ^^ ¡^ ug first variable length decoder 806, a series of processes are carried out, that is, the • Inverse quantization by means of an inverse quantizer 807 and the inverse discrete cosine transformation is carried out by means of an inverse DCT unit 808. Then, the processed residual DCT coefficient is added to an adaptive prediction signal 832 to compensate for movement, which is an output of the adaptive predictor 801 compensated in motion in an adder 809 to be? K 10 sent as an image signal 850 of the projector that is going to be sent as a 850 reconstructed image signal. The reconstructed image signal 850 is sent outside the system and is recorded in a memory 820 of the frame. The adaptive prediction information compensated in movement decoded by the second variable length decoder 810 that is supported to adaptive predictor 801 compensated in motion to produce the signal • 832 adaptive prediction compensated in motion. The processes mentioned above are processes for producing a dynamic image so as to correspond to the dynamic image coding system of Figure 1. The processes of the inverse quantizer 807, the inverse DCT unit 808, the summing machine 809 and the frame memory 820 are basically the same to those of inverse quantizer 107, the inverse DCT unit 108, the adder 109 and the frame memory 102 even though the means of realization may be different. In addition, the processes in the first and second variable length decoders 806 and 810, the multiplexer 811 and the input decoding unit 800 are reverse processes to those of the variable length encoders 106 and 110, the multiplexer 111 and the unit 200. of output encoding except for the case where an error is mixed in the code string. Figure 9 is a functional diagram of the unit 800 decoding input. The input decoding unit 800 comprises a synchronization detector 901 for detecting a synchronization code in the input code string 205 ', a counter 912 for counting the number of bits of the input code string 205', a device Resolution 903 of code string for resolving a code string into bits 912 of information and checking bits 913, a decoder 904 of error correction / detection and a removal apparatus 905 of the inserted bit. The synchronization detector 901 detects the synchronization codes only at the insertion positions of the synchronization code on the base and the counted value 911 of the counter 902. For example, assuming that the interval between the insertion positions of the adjacent synchronization code is sync_period, the value 911 counted is bit_count, and the length of the sync code is sync_len, the synchronization detection is carried out only when 0 < bit_count% sync_period < sync_len. In addition, the synchronization code can be detected in view of the errors in the synchronization code. In the bit insertion unit 211 of the output coding unit of Figure 3, if the code chain is transformed by inserting bit so that there is a large distance of 2 * n + 1 or more from the synchronization code in view of errors of n bits or less, even if it is determined that the code string having a large distance of not less than a true synchronization signal is a synchronization code, error synchronization detection does not occur when the n bit error or less is mixed. Figure 10 is a functional diagram of resolution apparatus 903 of the code chain. The input code string 205 'is switched to the information bits 1021 and the check bits 913 by means of a first switch 1002 controlled by a controller 1001 which will be described later. When the information bits 1021 are sent from the first switch 1002, a The information bit length of the information bits 1021 are transmitted to a buffer 1004 via a second switch 1003 to be stored therein. A counter 1005 counts the number of output bits from the second switch 1003. A comparator 1006 compares a counted value 1023 of the counter 1005 with an information bit length 1024 sent from a correction / detection code information output unit 1007. of mistake. When both are equal, the counter 1005 is readjusted, the identification signal 802 of the FEC class representative of the class of an error correction / detection code is engaged by means of a latching circuit 1008., and the buffer 1004 sends the information bit 904. The output 914 of the latching circuit 1008 is admitted in the error correction / detection code information output circuit 1007 and is sent to the correction / detection decoder 904. error shown in Figure 9. As described above, the error correction / detection code check bits are shifted to be placed between the information bit of the error correction / detection code after the string 205 of code. The controller 1001 controls so that the displaced check bits are separated from the information bits. When the input of the information bits of the correction / error detection code of a block that is completed, the value counted 1023 • corresponds to the length 1024 of the information bit in the comparator 1006. In response to this, the controller 1001 receives a length 1025 of the check bit from the error correction / detection information output unit 1007 and calculates the positions of the check bits placed between the following information bits. When determined by the comparator 1006 that both correspond to each other, assuming that the • counted value 911 of the number of input bits of the string 205 'of the code is bit_count and the length of the check bit is check_len, the starting position of the check_start check bit is check_start = (bit_count / sync_period + 1) * sync-period - check_len, and the final check-end check-end position is check-end = (bit_count) / sync_pepod_ + 1) * sync_period '. He • controller 1001 controls switch 1002 so that check bits 913 are sent from check_start to check-end of the 911 value counted. Since the end of a frame is a degenerate code and the correction / error detection coding of it is carried out, it is specially processed. When it reaches the end of a frame, an 803 signal is sent representative of the detection of the following table. In response to this signal 803, the controller 1001 calculates the positions of the check bits of the last error correction / detection code of the frame and the number of insufficient bits of the information bits. It is assumed that the counted value 911 of the number of bits of the code string 205 'allowed when it is started to support the last error correction / detection code of a frame is pre_last_count, the value 911 counted when the input of the code is completed. string 205 'of the code of a frame is the total_count, the value 911 counted during the process is bit_count, the length of the check bit of the last correction / error detection code of a frame is last_check_len, and the length of the check bit of the correction / error detection code immediately before the last error correction / detection code is pre_last_check_len. First, the information bit overrun and deficiency due to the error correction code which is a degenerate code and due to bit insertion, is calculated of course. Among the information bits of the last error correction / detection code of a frame, the number of bits contained in the input code string 205, last_? Nfo_len, is last_mfo_len = total__count - last_check_len - pre_last_count - pre_last _check_len. When last _mfo_len is shorter than the information length of the error correction code info_len, it is determined that the error correction code is a degenerate code. Further, when the counted value 1023 is within the last_into_len scale until info_len, the switch 1021 is switched to a bit pattern 5 sent from an inserted bit generator 1015, to compensate for the deficiency of information bits due to the degeneracy. The output bit pattern from the inserted bit generator 1015 generates the same bit pattern as that of the generator 705 of inserted bits of the Figure 7 of the encoder. • On the other hand, when last_info-len is longer than info_len, it is determined that the error correction code is the bit part inserted, so that the information bits 912 are not sent to the portion where the value 1023 counted is equal to or greater than infor_len. With respect to the check bits, the switch 1002 is controlled in order to send, as the check bit, the output code string 205 when total_count check_len < bit_count < total_count The error correction / detection decoder 904 receives the information bits 912 and the check bits 913, which are sent from the resolution device 903 of the code chain and decode the error correction / detection code on the basis of the signal 914 identification of the FEC class representative of the C 'class of correction code / error detection engaged by latch circuit 1008 of FIG. 10, to send a code string 915 corrected for the error and an error detection signal 804. The code string 915 corrected for the error is admitted to the allowed bit removal apparatus 905. The inserted bit removal apparatus 905 removes the inserted bits to prevent the pseudo-synchronization signal inserted by the bit insertion unit 211 of the output coding unit 200. As described above, since the bit insertion is carried out only in the synchronization insertion position, the synchronization insertion position is determined on the basis of the counted value 911 of the counter 902. For example, when the synchronization code word is that shown in Figure 5 and when the bit insertion unit 211 inserts bits in the "000011" portion of the first sync_len bits of the synchronization code so that the large distance from the code synchronization is greater than 2 * n + 1, the number of "1" (= nO) of the bits "sync_0_len - (2 * n + 1)" of the insertion position of the synchronization code is counted. When nO is equal to less than 2 * n + 1, 2 * n + 1 - nO bis are removed. Nevertheless, "F" J- .-? £ S _--, &since it is determined that the inserted bit is "1", when the bit determined as the bit inserted by the inserted bit removal unit "905" is "0" , an error is considered to be mixed in the synchronization code insertion interval 5. In this case, the error detection signal 804 is sent.Thus, the code string 801 decoded by the decoding unit 800 input is multiplexed in reverse by means of the F 10 demultiplexer 811. This is the operation for separating and sending the multiplexed codeword as shown in Figure 2. This inverse multiplexer 811 works with the first and second decoders 806 and 810 of variable length. First, when the synchronization code detection signal 803 is supported from the output decoding system 800, the demuxer 811 returns w to the initial state of the frame process. Then, the error correction / detection code class towards the The header of the image is sent as the identification signal 802 of the FEC class representative of the error correction / detection code class, and the code string 801 is admitted to decode the image header 302 so as to be determine if there is no error in the header of the image. When do not there is an error, the error correction / detection code class towards the prediction mode information 303 is sent as the identification signal 802 of the FEC class, and the code string 801 is allowed to demultiplex the information so of prediction to send it to the second variable length decoder 810. When all the prediction mode information is decoded, the second variable length decoder 810 sends a signal representative of this to the demultiplexer 811. In response to this, the demultiplexer • 811 sends an identification signal of the FEC class representative of the class of an error correction / detection code to the motion vector information 304, and initiates the demultiplexing of the information 304 of motion vector. The demultiplexed motion vector information is sent to the second variable length decoder 810 to be decoded.

• When the decoding of all motion vector information is completed, a signal is sent representative of the same from the second variable length decoder 810 to the demultiplexer 811. In response to this, the demultiplexer 811 sends an identification signal of the FEC class representative of the class of an error correction / detection code to the residual DCT coefficient, and demultiplexes the residual DCT coefficient 305 that is sent to the first variable length decoder 806. • As described above, the error correction / detection code class is determined on the basis of the multiplexing rule that is defined in the demultiplexer 811 to be the same as that of the output coding unit 200. . Therefore, the exit code string 205 is not required to contain the header information representative of the code of correction / error detection and so on. • In the error detection / correction decoder 904, it can be detected by the error detection code, that an error is mixed in the input code string 205 '. Also, as described in what In the foregoing, an error of the inserted bits can be detected by the unit 905 of removing the inserted bit. In these cases, the error detection code 804 is sent from the input coding unit 800. Also, when a code word is detected, it does not exist in the variable length codeword box in the variable length decoding process, it is determined that an error is mixed. Further, when it is determined that a part is against the multiplexing rule in the demultiplexing process in the demultiplexer 811, it is determined that an error is mixed. In these cases, the input decoding unit 800 and the demultiplexer 811 carry out the following processes so as not to greatly deteriorate the reconstructed image. (1) When an error is detected in the residual DCT coefficient 5, the remainder of the corresponding part is graded to be 0. When an intra-coding mode is selected as a prediction mode, the signal of the reconstructed image in the corresponding region can be predicted on the basis of the reconstructed image signal 10 in the reconstructed frame and the surrounding region. • (2) In a case where an error is detected, in the prediction mode information and the motion vector, when the prediction mode information and the motion vector information in the region, in Where the error is detected can be assumed on the basis of the prediction mode information and the motion vector information in the surrounding region, the • supposed information. When possible, the signal of the reconstructed image in the corresponding region is predicts on the basis of the reconstructed image signal in the reconstructed frame and the surrounding region. (3) When an error is detected in the header of the image, if the header of the image is used as it is, there is a probability that the image quality deteriorates greatly. Therefore, the reconstructed image of the last frame is used as the reconstructed image of the current frame. In the processes mentioned above (1), (2) and (3), when the error has an influence on the Subsequent codes to the following synchronization code due to the use of variable length coding, the same processes are carried out for that portion. Even though it has been described that the detector 901 of the F 10 synchronization code detects the synchronization codes only at the insertion positions of the synchronization code (at intervals of sync_period bits), the bit loss and / or the insertion of error bits may occur in a transmission medium / storage. In In this case, the synchronization codes can be detected in positions other than the insertion positions of the synchronization code and it can be determined that the F positions, in which the synchronization codes are detected, are the code insertion positions of synchronization.

(Second Preferred Modality) With reference to Figures 12 to 14, the second preferred embodiment of the present invention is will describe below.

In the preferred embodiment, a dynamic image coding system and a system of • Dynamic image decoding can safely detect synchronization even when a chain of code 5 is transmitted / stored on a transmission line / storage medium where the number of bits decreases due to the loss of a part of a chain of bits or the number of bits is increased due to the addition of excessive bits. 10 Figure 12 is a functional diagram showing • the beginning of a process to detect synchronization when bit addition / loss occurs. It is assumed here that the correct synchronization code comprises "0" of the bits sync_0_len and that "1" of a bit as shown in Figure 12 (a). Also, in Figure 12, "x" represents a bit that is not a synchronization code. Figures 12 (b) to 12 (e) show the manner in which F that the synchronization code is changed by adding / losing bits. It is assumed here that the number of bits added / lost (Nid) is one bit when maximum. Figure 12 (b) shows that a bit is removed from a bit string before a synchronization code so that the entire synchronization code is shifted forward by a bit. Figure 12 (c) shows that adds a bit to a bit string before a synchronization code, so that the entire synchronization code is shifted back by a bit. Figure 12 (d) shows that a bit of a synchronization code is deleted so that the bits after the bit deletion position indicated by the arrow are moved forward by a bit. In addition, Figure 12 (e) shows that a bit is added to a synchronization code in the bit addition position which is indicated by the arrow so that the bits after the position of the addition of bits are shifted back • by a bit. In order to correctly detect the synchronization even when bit addition / loss occurs, it is required to determine that the bit strings shown in the Figures 12 (b) to 12 (e) are synchronization codes. As can be seen from Figure 12, the number of "1" contained in the range of the bits + Nid in the insertion positions • Correct synchronization code is sync_0_len - 3 * Nid bits when it reaches the maximum. Therefore, the synchronization can be detected in the range of + Nid bits in the synchronization code insertion positions on the decode side and if the number of "1" contained in this scale is less than the aforementioned value, it can be determined that is a synchronization code. In addition, in the coding system, the code strings are transformed so that the bit patterns of Figures 12 (b) to 12 (d) do not occur. Mainly with respect to the difference from the first preferred embodiment, these coding / decoding systems will be described below. The total construction of the second preferred embodiment of a dynamic image coding system, in accordance with the present invention, is the same as F 10 that of the first preferred embodiment of a dynamic image coding system except for the operation of the bit insertion unit 211 of Figure 3. Figure 13 shows the operation of the insertion unit 211 of bit. That is, in unit 211 bit insertion in the first preferred embodiment, the bit insertion operation is carried out only during the code insertion interval of F synchronization. On the other hand, in the bit insertion unit 211 in the second preferred embodiment, the The bit insertion is carried out in a synchronization code insertion slot of the + Nid bits in order to prevent the same bit pattern as the synchronization code from occurring even when the addition / loss occurs to the maximum of the Nid bits.

Assuming that the value 221 counted in Figure 3 is total_len and that the interval between the positions of • sync code insertion is sync_per? Od, bit insertion unit 221 counts the number of "1" (which 5 is assumed to be = nO) in the region of total_len mod sync_period = sync_0_len - 1 - 3 * Nid on the basis of total_len mod sync_period = sync_period - Nid (mod: excess operation), and insert the "1" of "3 * Nid + 1 - nO" if nO is less than 3 * Nid + 1. 10 Figure 13 shows an example of the operation • of the bit insertion unit 211 when syncjperiod = 12, sync_0_len = 9, and Nid = 1. In this example, since nO = 2, the "1" of 3 * Nid + 1 - nO = 2 bits are inserted . By this bit insertion, it is ensured that the "O" number of the + Nid bits in the insertion interval of the synchronization code is equal to or greater than 3 bits * Nid so that it is possible to uniformly identify the • synchronization codes. On the other hand, all the construction of the The second preferred embodiment of the dynamic image coding system according to the present invention is the same as that of the first preferred embodiment with the exception in the operations of the synchronization detector 901 and the bit removal apparatus 905. inserted in Figure 9. Figure 14 shows the pz-miBaí &tisti- operation of a 905 bit removal device inserted. • That is, the synchronization detector 901 detects the synchronization codes within the scale 5 of the + Nid bits before and after the insertion position of the synchronization code in order to detect the synchronization even when the addition / loss of Nid bits. First it is determined, if there are 10 sync codes during each code insertion position • synchronization; that is, assuming that the counted value 911 of the counter 902 is bit_count, the number of "0" (which is assumed to be = nsO) within the scale of bit_count mod syncjperiod = sync_0_len - 1 + Nid is counted 15 on the basis of bit_count mod sync_period = syncjperiod - Nid. When nO is less than 3 * Nid, it is determined that a synchronization code exists in this region. • Figure 14 shows the operation when sync_period = 12, sync_0_len = 9, and Nid = 1. In this example, the number of "0" is counted within the scale of (bit_count mod sync_period) is from "1" to "8". In the example of Figure 14, since nsO = 2, it is determined that there is a synchronization code. Then it is determined which of the bits of the code string is shifted by the addition / loss of bits in the insertion interval of the synchronization code where it is determined that a synchronization code exists. In the case of sync_0_len bits shown in Figure 14, the amount displaced from the 5 position of the last "1" is determined. Specifically, after searching for a "1" that appears first from (sync_0_len + 1 bits) th from the head of the synchronization code determination region, which bit is the searched "1" of the head of this synchronization code is derived. region of 10 synchronization code determination (assuming that • this is the first_l_position bit). On the basis of the derived results, the displaced quantity is derived from the "number of displaced bits = first_l_pos - (sync_0_len + 1 + Nid)" (forward offset in the case of negative backward offset in the case of positive). The example of Figure 14, since the first_l_pos = 10, the number of bits displaced = 10 - • (9 + 1 + 1) = -1, so that the chain of codes is found to be moved forward by a bit. In contrast to the first preferred embodiment, in the inserted 905 bit removal device, the inserted bit removal process is carried out in the range of the + Nid bits before and after the insertion position of the synchronization code . That is, about 25 the basis of bit count mod sync period = sync period - Nid, -É, ~ ^ _ * - & , ,, 77 the number of "1" (which is supposed to be = nO) is counted in the bit_count region mod syncjperiod = sync_0_len - 1 - 3 * Nid. When nO is equal to or less than 3 * Nid + 1, the "1" of 3 * Nid + 1 - nO bits are removed. In the second preferred embodiment, if the region in which the addition / loss of bits occurs in a transmission line or a storage medium, can be determined by a certain method, the synchronization detection process, the insertion process of bit and the bit removal process that considers addition / loss • of bits, it can be carried out only in that region. In addition, also in the dynamic image coding system in the first preferred embodiment as described above, synchronization detection which corresponds to the addition / loss of bits in a transmission line and / or a storage medium is carried out. Therefore, the synchronization detector 901 • can detect synchronization in the insertion interval of the synchronization code, that is, in the bit + Nid range, similar to the second preferred mode. In this case, even when a pseudo synchronization, which is erroneously determined as being a synchronization code while it is a portion other than the synchronization code can occur, it is possible to inhibit the quality of a reproduced image of - 7S deteriorate due to a synchronization detection error in a transmission line and / or a storage medium that tends to cause the addition / loss of bits so that the quality of the image can be improved. In addition, if the region in which the addition / loss of bits occurs in a transmission line and / or drive means can be determined by a certain process, that process can be carried out only in that region, and can be carried out. in other regions a usual synchronization detection. • Furthermore, in the first and second preferred embodiments as described above, synchronization can be further protected using information representative of the length of a frame (a which will be referred to below as a "frame length information"). Figures 15, 16 and 17 show examples of code strings using the ^ w INDICATOR of the frame length information. In the example of Figure 15, an INDICATOR of frame length information and a CHKP check bit of an error correction / detection code to protect the frame length information INDICATOR are placed immediately after a PSC synchronization code. The number of bits of the last frame, that is, information representative of the number of bits from the synchronization code of the last frame to the • synchronization code of the current frame, it is stored in the frame length information INDICATOR. 5 The coding system counts the number of bits of a code string of a frame to transform the counted number into a frame length INDICATOR, and carries out the correction / error detection coding to produce a CHKP check bit . Then, as shown in Figure 15, the coding system • produces a chain of code immediately after the synchronization code of the next frame. On the other hand, after the decoding system detects the synchronization codes by the same method as those in the first and second preferred embodiments, take the subsequent frame length INDICATOR and the bit ^ CHKP check out of the code chain carries out the correction / error detection coding for decode the frame length information INDICATOR. Then, the decoded frame length information INDICATOR is compared to a derived value by counting the number of bits from the detected synchronization code to the last one to the code of current synchronization (counted value of the frame length) to check if there is no error detection of the synchronization codes. • If the count value of the frame length is different from the code length of the last frame 5 indicated in the frame length information INDICATOR, there is a probability that a synchronization code has been detected incorrectly so that the code of Synchronization detected erroneously is detected again using the length information indicator box. That is, a code of • synchronization, which could not be detected, exists before the current synchronization code by the number of bits indicated by the frame length information INDICATOR. In this case, the interval between the last code detected synchronization and the current synchronization code is divided into two frames, that is, the interval between the last synchronization code and the position • indicated by the frame length information INDICATOR, and the interval between position and code current synchronization to carry out the decoding process. However, if the number of bits indicated by the frame length information INDICATOR is greater than the number of bits of the last synchronization code detected the current synchronization code, it is assumed that 1 - The frame length information INDICATOR is erroneous so that the process of detecting the synchronization mentioned above is not carried out. If the number of bits of the frame length information INDICATOR 5 and the check bit CHKP are large, the synchronization code PSC, the frame length information INDICATOR and the check bit CHKP can be extended in a plurality of intervals. of synchronization, as shown in Figure 16. In this case, the process of inserting bits into the system of • coding and the process of removing bits in the decoding system that are carried out in order to maintain a constant large distance between the code string other than a synchronization code and the synchronization code can not be carried out in a range in which the frame length information INDICATOR and the CHKP check bit exist. • In the examples of Figures 15 and 16 in a case where the final half of a synchronization PSC code 20 contains information representative of the synchronization code class (the distinction between a frame synchronization code, a synchronization code GOB and so on), the frame length information INDICATOR is not only protected but the final half 25 of the synchronization PSC code can also be protected , • by an error correction code. In this way, since the class of a synchronization code can be detected exactly in addition to the position of the synchronization code, the resistance to errors is further improved. In the example of Figure 17, a box length information INDICATOR and a CHKP check bit are placed at the end or end of a frame (immediately before a sync code in the following frame). In this case, after the decoding system detects the synchronization code in the following frame, it extracts a frame length information INDICATOR and a CHKP check bit immediately before the detected synchronization code performs the decoding. of correction / error detection to carry out the re-detection of the synchronization code by the same processes as those shown in Figures 15 and 16. In the example of Figure 15, since there are synchronization codes only in the positions for insertion of the synchronization code, the indicator of the frame length information to be recorded may be a derived value by dividing the number of bits in the frame by an insertion interval of the synchronization code (= bits sync period). Therefore, the 13 - The length of the frame can be indicated by a smaller number of bits. In addition, in the first and second preferred embodiments, even if examples of a hierarchical coding have been shown to change an error correction / detection code in accordance with the importance of the encoded information, the same code can be used in the frame correction / error detection or an error correction / detection code may not be used. In these cases, it is possible to improve the ability to detect synchronization compared to conventional systems using the bit insertion process by keeping a code string other than the synchronization code at a large distance greater than one value predetermined from the synchronization code, and the synchronization code detection process corresponding to the bit insertion process as described in this preferred embodiment. In addition, in the preferred embodiments mentioned above, even though it has been shown that a dynamic image signal is encoded by high efficiency compression to be transmitted / stored, the present invention can be applied to the transmission / storage of a static image, a voice, data or the like. By For example, when the compression coding at high efficiency of a static image signal is carried out using the orthogonal transformation, the • Error correction / detection can be switched to more intensively protect the error of a low component of a transformation coefficient. In the method for modeling and encoding the speech in a driving source and a speech filter, the error correction / detection code can be switched in order to carry out the error protection of a cycle more intensively, a vocal parameter and so on. • (Third Preferred Modality) The third preferred embodiment of the present invention will be described below. In this modality Preferred, the correction / error detection code is not used. At this point, this preferred embodiment is different from the first and second preferred embodiments. Figure 18 is a functional diagram of a dynamic image coding system in this preferred embodiment. Using the same reference numbers as those in Figure 1 for parts corresponding to those of Figure 1, different points of the first preferred embodiment will be described primarily. In this preferred embodiment, the construction and operation of the output coding unit 200 are different. Also, even when the basic operation of a multiplexer 111 is the same as the multiplexer • 111 of Figure 1, the multiplexer 111 in this preferred embodiment sends only a multiplexed code 5 string 201 and a synchronization code insertion request signal 203, since the error detection / correction code is not used. Figure 19 is a functional diagram of the output coding unit 200 of Figure 18. The output coding unit 200 comprises a counter 1701 for counting the number of bits of an output code string 205, a switch 1703 for switching the output code string 205, a switch controller 1704 for controlling the switch 1703, and a Generator 1705 of fill bits to generate fill bits. Figure 20 shows an example of a string 205 • of output code generated by the output coding unit 200 of Figure 19. The same are used signs than those in Figure 4 for code words corresponding to those of the output code string of Figure 4. In a manner similar to Figure 4, each of the synchronization PSC codes is inserted only in one of Code insertion positions of synchronization that are periodically placed, that is, YES. 16 -. 16 - at regular intervals (bits sync__period) and indicated by arrows. Figure 20 does not contain the bit of • CHK check for error correction / detection code. At this point, Figure 20 is different from Figure 4. A fill bit STUFF is inserted into the end part of a frame of the output code string 205 so that the synchronization PSC code is inserted into the position. of insertion of the synchronization code. The number of bits of the padding bit STUFF is equal to or less than the syncjperiod. • The construction and operation of the output coding unit 200 of Figure 19 to produce this output code string 205 will be described in detail below. 15 The counter 1701 is graded to be "1" when a synchronization code insertion request signal 203 is admitted from a multiplexer 111 to the same • and an initial bit of a synchronization code 301 is admitted to it as a multiplexed code string 201, and then graduated to be a synchronization code length sync_len when all the bits of the synchronization code 301 are admitted to it. Then, the counter 1701 counts in sequence from the next bit of the synchronization code 301 until a bit is sent immediately before the next synchronization code. • When the bits of the initial bit of the synchronization code to the bit before the next 5 synchronization code are admitted as a multiplexed code string 201. The controller 1704 of the switch controls the switch 1703 in order to switch the switch 1703 to the multiplexed code string 201 to send the multiplexed code string 201 as a string 205 of exit code. Then, the last part of a frame, the insertion of bits (bit stuffing) is carried out so that the next synchronization code is inserted at the insertion position of the synchronization code. He multiplexer 111 sends a synchronization code insertion request signal 203 for the next frame when the output of the multiplexed code string f 201 of a frame is completed. In response to this, the switching controller 1704 switches the switch 1703 to the fill-bit generator 1705 for sending a fill bit 1223 as an output code string 205. Fill bit 1223 can have all bits of "1" or "0" or a specific pattern such as "0101" ...

This preferred embodiment of the dynamic image coding system in accordance with • present invention, will be described below. Figure 21 is a functional diagram of a dynamic image decoding system corresponding to the dynamic image coding system of Figure 18. Using the same reference numbers as those in Figure 8 for the parts corresponding to those in Figure 8, the points different from the first preferred embodiment will be described mainly. In this preferred embodiment, the construction and operation of the input coding system 800 are different from those in the first preferred embodiment. In addition, the signals admitted from the An input decoding unit 800 to a demultiplexer 811 is only a code string 801 and a synchronization code detection signal 803 and no signal is admitted from the demultiplexer 811 to the input coding unit 800. Figure 22 is a functional diagram of the input decoding unit 800. The input decoding unit 800 comprises a synchronization detector 1901 for detecting a synchronization code in an input code string 205 ', and a counter 1902 for counting the number of bits of the input code string 205'. • Counter 1902 is reset to "0" at the initial decode stage and counts up to a value 1911 counted for each "1" each time a bit of the string 205 'of input code is admitted. The synchronization detector 1901 detects the synchronization codes only in the positions of insertion of the synchronization code based on the counted 1991 value of the counter 1902. For example, assuming that the insertion interval of the synchronization code is syncjperiod, the counted value 1911 is bit_count, and the length of the synchronization code is sync_len, the synchronization detection is carried out only when 0 < bit_count mod syncjperiod < sync_len, wherein A mod B represents a detector 1901 that sends a synchronization code detection signal 803 when a synchronization code is detected. The code string 801 from the input decoding unit is admitted to the multiplexer 811, while the input code string 205 'is sent as is. Then, similarly to the dynamic image decoding system of Figure 21, the demultiplexing and coding processes are carried out. In a case where the last STUFF padding bit of the frame is a predetermined bit pattern, it is determined whether the padding bit STUFF corresponds to a predetermined pattern in the demultiplexer 811. When it does not correspond to it, it is determined that there is an error in the string 205 'of the input code, so that the process to prevent the quality of the image from deteriorating greatly which has been described with respect to the dynamic image coding system in the first preferred embodiment, can be cape.

(Fourth Preferred Modality) The fourth preferred embodiment of the present invention will be described below. In this preferred embodiment, the complete construction of the dynamic image coding system is the same as that of the dynamic image coding system of Figure 18 and the operation of an output coding unit is different from that in the third preferred embodiment. Figure 23 is a functional diagram of an output coding unit 200 in Figure 18. Using the same reference numbers for the parts corresponding to those of the output coding unit of Figure 19, the difference of the unit from F output coding of FIG. 19 is that a bit insertion unit 1211 is added to perform the bit padding process to prevent a pseudo synchronization code. In a bit insertion unit 1211, the insertion of bits to prevent a pseudo synchronization so that it does not occur is carried out for the string 201 of F 10 multiplexed code. Since it is not possible to uniformly decode a synchronization code if the same bit pattern as the synchronization code is contained in the output code string 205, the bit insertion is carried out in order to prevent this. For example, as shows in Figure 5, when the synchronization code comprises "0" 's of bits sync_0_len, a "1" of a bit and "xxxxx" of the sync_nb_len bits representative of the class of the synchronization code, it is possible to prevent a pseudo-synchronization occurs if a "1" is inserted so that the "0" 's of the sync_0_len bits or more are not continuously placed in the code string other than the synchronization code. The synchronization code is inserted only in the synchronization code insertion system.

Therefore, the operation of inserting bits for preventing the occurrence of pseudo synchronization can only be carried out at the synchronization code insertion positions. Therefore, it is determined whether it is required to carry out the insertion of bits on the basis of a counted value 1221 representative of the total number of bits of an output code string 205. Assuming that the value 1221 counted is total_len, the number of the "1" s in the multiplexed code string 201 is counted in a range of 0 < total_len_mod_sync_pepod < sync_0_len If it does not exist a "1" in this interval, a "1" of a bit is inserted.

• Here, A mod B represents a remainder when A is divided by B. In addition, in order to decrease the probability of error detection of a synchronization code due to the error, the insertion of bits can be carried out in the following way. In order to detect a synchronization code yet • When an error of n bits is mixed in the synchronization code, it is required to determine if a word of code having a large distance of n or less from a true synchronization code in an input decoding unit of a dynamic image decoding system as will be described later, is a synchronization code. However, if this determination is carried out while the code strings other than the synchronization code are left as they are, the bit patterns that have a distance • Large of n or less since the synchronization code can still exist in code strings other than the 5 synchronization code. If this is placed in the insertion position of the synchronization code, it can be mistakenly determined as being a synchronization code. Therefore, the next insertion of bits to the multiplexed code string 201 is carried out • by means of a bit insertion unit 211 so that the code strings other than the synchronization codes placed in the insertion positions of the synchronization code in the code string 201 multiplexed are transformed in order to have a large distance of 2 X n + 1 or more from the synchronization code. Specifically, the number of "1" (which • is assumed to be nO) is counted in a range in which 0 < total_len mod syncjperiod < sync_0_len - (2 X N + 1).

If nO is less than 2 X n + 1, the "1" of 2 X n + 1 - nO bits are inserted in the multiplexed code string 201. With respect to the code string 1222, where the insertion of bits has therefore been carried out, the insertion of bits (STUFF in Figure 20) is carried out in the last frame interval similar to the output coding unit of Figure 19, to be sent as an output code string 205. • This preferred embodiment of the dynamic image decoding system according to the present invention will be described below. The entire construction of this dynamic image decoding system is the same as that of the dynamic image decoding system of Figure 21, and the operation of an 800 input coding system. same is different from that in the third modality • preferred. Figure 24 is a functional diagram of an input decoding unit 800. Using the same reference numbers for parts that correspond to those of an input decoding unit of Figure 22, the difference between the preferred embodiment and the third preferred embodiment will be described primarily. In this preferred embodiment, a bit removal unit 1905 is added. An input code string 205 'is admitted to an inserted bit removal device 1905 and a process is carried out to remove the inserted bits so as to preventing a pseudo-synchronization code inserted by the bit insertion unit 1211 from the unit The output coding of Figure 23. As described above, since the insertion of bits is carried out only in the insertion positions of the • synchronization, the insertion positions of the synchronization code are determined on the basis of a counted value 1911 5 of a counter 1902. For example, assuming that the synchronization code is a code word shown in Figure 5 and that when the 1211 bit insertion unit performs the insertion of bits towards the initial position of "0000 ..." of the synchronization code so that the large distance of the synchronization code is greater than 2 X n + 1, the number of "l" 's of sync_0_len - (2 X n + 1) bits of the insertion position of the synchronization code is counted. When nO is less than 2 X n + 1, remove 2 X n + 1 - nO. Since it is determined that the inserted bit is "1", when the bit determined to be the inserted bit is "0", an error is considered to be mixed in the insertion interval of the synchronization code. In this case, an error detection signal (not shown) can be sent to a demultiplexer 811 and the same process as that in the first preferred embodiment can be carried out to prevent a reproduced image from deteriorating greatly.

The process of bit insertion by the bit insertion unit 1211 of Figure 23 can be carried to • so that inserted bits of a predetermined number of bits are inserted in all intervals of synchronization code insertion other than the synchronization code. Figure 25 shows an example of an exit code string 205 when this bit insertion process is carried out. In the drawing, SB represents an inserted bit. 4fek 10 For example, as shown in Figure 5, when a synchronization code comprises "0" 's of the Sync_0_len bits, a "1" of one bit and "xxxxx" of the bits of sync_nb_len representative of the class of the synchronization code. An SB bit inserted from a bit is inserts at a predetermined position a range of the sync_0_len bits from the head of the synchronization code insertion interval. WJP "The inserted SB bit can always be" 1. "Also, in accordance with the bit pattern in an interval bits of sync_0_len from the head of the synchronization code insertion range, the inserted SB bit can be appropriately determined such that the number of "l" 's in the range is equal to or greater than 1. In addition, the SB bit inserted can be a parity odd in the range of the sync bits 0 len from the head of the synchronization code insertion interval to prevent the same bit pattern from occurring as the synchronization code and to detect a mixed error in this bit pattern. Figure 25 (b) shows an example of an output code string where this bit insertion process is carried out. In this example, a bit SB inserted from a bit is inserted into the initial portion of the insertion position of the synchronization code. This bit SB inserted is determined so that the number of "l" 's in a range of the bit SB inserted from the bits sync_0_len -1 of the next bit is always an odd number. For example, in the example shown in Figure 25 (b) the SB bit inserted is "1". Also, in the correct example of Figure 25 (b), since the SB bit inserted is "1" even though all the other bits are "0" in the range of the bits of sync_0_len - 1 the next bit to the SB bit inserted, the "1" of a bit or more always exist in the insertion interval of the synchronization code so that the same bit pattern does not occur as the synchronization code. In addition, since the inserted SB bit serves as a parity check, it is possible to detect a mixed bit error in this range.

Also, the inserted SB bit may be an odd parity check bit for all the bits before • the next position for inserting the synchronization code. However, in order to prevent the same bit pattern from occurring as the sync code only when all bits of sync_0_len-1 of the next bit to the inserted bit SB are "0", the inserted SB bit is always graduated to Be a "1" In this way, it is possible to carry out the error detection 10 by checking the parity of all the bits. • In order to decrease the probability of error detection of a synchronization code due to the error, it is desired to insert more bits. For example, in order to correctly detect the synchronization even when an error of n 15 bits is mixed, the "1" of the bits 2 X n + 1 are inserted at a predetermined position in this interval. In this preferred embodiment, the operation of the • bit removal unit 1905 of Figure 24 is different to correspond to the operation of the aforementioned bit insertion unit 12 1211. That is, the bit removal unit 1905 removes the bit SB inserted in a predetermined position in which bit insertion has been carried out by the bit insertion unit 1211.

In a case where the SB bit inserted is always a "1", it is determined that there is a bit error when A bit at the bit insertion position in the input code string 205 'is "0" so that an error detection signal (not shown) can be sent to the reverse multiplexer 811 to prevent it from being detected. greatly deteriorate a reproduced image. In the first to the fourth preferred modalities, while the information 303 of the prediction mode, the information 304 of motion vector and coefficient • Residual DCT 305 have been multiplexed in the multiplexer 111 for each coding frame as shown in Figure 2, the prediction mode information 303, the motion vector information 304 and the coefficient 305 of residual DCT can be multiplexed for each coding region (e.g., a macroblock GOB) as shown in Figure 26. In this case, the header 302 of the • Image and other information may have a different error correction / detection code or the same code correction / error detection. Alternatively, an error correction / detection code can be used for only the header of the image or for a part of the code string of a predetermined number of bits of each frame, or no code can be used. correction / error detection.

In addition, multiplexing can not be carried out only for each frame (image), but it can also be • carried out for each part of a frame or for each layer of a plurality of frames so that the synchronization code 5 can be inserted for each of these multiplexing units (layer unit). Figure 28 shows examples of this multiplexing. In the examples in Figure 28, the multiplexing processes are carried out for each of four layers, that is, each macroblock layer of a plurality • of coding blocks, each GOB layer and a plurality of macroblocks, each image layer (frame), and each session layer of a plurality of images. Between these layers, the session, image and GOB layers use their synchronization signals (SSC, SEC, PSC and GSC in the drawing) respectively. Different codes are used for SSC, SEC, PSC and GSC so that it is possible • identify which layer of the synchronization code is detected. When the synchronization code shown in the Figure 5 is used, these synchronization codes can be distinguished by the portion of the sync_nb_len bits representative of the class of the synchronization code. Likewise, when this multiplexing is carried out, the same processes as those for the code of I synchronize the frame in the above preferred modes can be carried out for a part or all the synchronization codes of the session, image or GOB. Figure 29 shows an example of a chain of exit code where this process is carried out. As shown in Figure 29, the padding bits STUFF are inserted before PSC and GSC, and the SSC, PSC and GSC are inserted in the insertion positions of the synchronization code indicated by the arrows in the drawing. Therefore, similar to the preferred modality • previously mentioned showing the PSC frame synchronization code, the accuracy of the detection of each synchronization code can be improved. You can add the same length information of the frame length information INDICATOR of Figures 15, 16 and 17 to each synchronization code of the image and GOB session. In a case where the INDICATOR of • Table length information is protected by a correction / error detection code as shown in Figures 15 and 16, if the error correction / detection code is not used only for the frame length information INDICATOR but is also used for a portion of the sync_nb_len bits representative of the class of a synchronization code , it is possible to improve the probability that the class of the synchronization code, in addition to the position of the same, can be detected correctly. In addition, part or all of • header information (SB, PH and GF in the drawing) of the session, image and GOB can be protected using the 5 error correction / detection code so that it is possible to improve the resistance to error of each header information. In a case where the process of filling in to prevent a pseudo code from being carried out synchronization, as this preferred embodiment, the following process can be carried out so that the syncjperiod synchronization code insertion interval is equal to or less than the length of the synchronization code. First, the process of the output coding unit of the dynamic image coding system will be described. It is assumed in the present that the code of • synchronization is a code word comprising the "0" of the sync_0_len bits and a 1-bit "1" as shown in shows in Figure 5. In the output coding unit of Figure 23, assuming that the counted value 1221 representative of the number of bits sent from the bit insertion unit 1211 is total_len, when a remainder of the division of total_len through the interval sync code insertion sync period is equal ^ taiiMü? ^ A ^ a remainder of the division of a value, which is derived by subtracting 1 from the number of the sync_0_len bits from the "0" • initials of the synchronization code, through the sync_period, that is, when 5 total_len mod syncjperiod = (sync_0_len - 1) mod sync_peridod (1) the number of "1" that is supposedly ni) in the output bits before the bits (sync_0_len - 1) from the output bit during that moment is counted, and a "1" of 1 bit is counted inserts if there is no "1" (that is, if neither = 0). Figure 33 (a) shows an example of an exit code string, for which this process has been carried out. In the drawing, each of the arrows descends indicating an insertion position of the code of synchronization and a synchronization code comprises "0" of 23 bits (ie, sync_0_len = 23), and a "1" of 1 bit. In the example shown, an insertion interval of ^ B synchronization syncjperiod code is 8, which is shorter than the synchronization code length (= 24 bits). 20 In the drawing, intervals 1 to 4 represent ranges for counting those not mentioned above. In this interval, the number of "1" is not counted in sequence. If ni = 0, a fill bit is inserted in the next bit of the interval. Since neither > Or in interval 1, I do not know requires inserting the fill bit. Since ni = O in When the interval 2, a one-bit fill bit 3301 is inserted in the next interval. In interval 3, ni = 1 due to insert bit 3301 inserted so that it is not required to insert a fill bit. 5 If this bit-filling process is carried out, the same bit pattern does not exist as a synchronization code in a portion other than the synchronization code in an output code string such that no pseudo synchronization occurs . -át 10 On the other hand, in order to decrease the probability that a synchronization code is detected erroneously due to a transmission line error, a bit insertion can be carried out in the following manner. 15 Even when an n bit error enters a synchronization code, the synchronization code can be correctly detected by performing a bit insertion process so that the large distance between the portion other than the synchronization code and the code 20 synchronization in a string of output code in a 1211 bit insert is equal to or greater than 2 xn + 1. In this process, when a derived residue by dividing a total counted value 1221_ representative of the total number of bits of the output code string 205 of Figure 23 by an insertion interval ? ^ ^^? ^ zíí ^ ?? »r, of the synchronization code the sync_period is coincident with a rest derived by dividing a value, which is derived by subtracting 2 xn + 1 from the initial number of bits of" 0"from a code of synchronization, using the sync_period, that is, when total_len mod syncjperiod = (sync_0_len - (2 xn + 1)) mod syncjperiod (2) the number of "1" (which are assumed to be neither) in the output bits of the bits of (sync_0_len - (2 xn + 1)) from the output bit during that moment. If the number of "1" is less than (2 x n + 1) bits, that is, if neither < 2 x n + 1, the "1" bits (2 x n + 1 - ni) are inserted. As shown in Figure 5, when the synchronization code starts from "0" a plurality of bits is used, if the number of "1" in a bit string immediately before the synchronization code is insufficient, synchronization error detection may occur in that portion. In order to prevent this, a bit insert (STUFF in Figure 20) in the last interval of a frame can be sent so that the number of bits of the "1" in a sync_period bit range from the synchronization code to the insertion position of the synchronization code immediately before the synchronization code is equal to or greater than 2 xn + 1 bits. In order to do this, an STUFF that always contains the "1" of 2 x n + 1 bits can be used, or the STUFF can be determined according to an output code string. That is, the STUFF can be determined such that the number of bits of "1" of the sync_period bits immediately before the synchronization code in the output code string containing the STUFF is equal to or greater than 2 xn + 1 bits . Figure 33 (b) shows an example of an exit code string for which a process has been carried out. In the drawing, intervals 1 to 4 represent intervals for counting the aforementioned. In each interval, the number of ni of "1" is counted in sequence. If neither < 2 x n + 1, a fill bit is inserted in the next bit of that interval. Since ni = 1 in interval 2, the fill bits 3311 of (2 x n + 1) - 1 = 2 bits are inserted in the next interval. An interval of 3, ni = 3 due to the insert bits 3311 inserted so that inserting the fill bits is not required. In addition, in order to prevent a synchronization code error detection immediately before the synchronization code, an STUFF is determined in the following manner. It is assumed that a bit immediately preceding STUFF is 3311. Since the number of "1" in a range • (interval 5) of the syncjperiod bits from an insertion position of the synchronization code immediately 5 before bit 3312 to a insertion position of the synchronization code immediately after bit 3312 is only one bit, synchronization error detection may occur in this portion towards the synchronization code having a plurality of "0" placed continuously as shown in the Figure 5. Therefore, • the position in which the synchronization code is inserted is shifted to the next insertion position of the synchronization code and a STUFF 3313 containing many "1" is sent. In this way, since the "1" s of 2 x n + 1 or more are contained in a range (interval 6) of the syncjperiod bits immediately before the synchronization code, it is possible to prevent detection of the synchronization error. If this bit-filling process is carried out, the large distance from the synchronization code may be 2 xn + 1 or more in a portion other than the synchronization code in the output code string so that the probability of synchronization error detection can be decreased. xsátSS - 10Í The processes in an output decoding system of a dynamic image decoding system will be described below. In the bit 1905 removal apparatus of Figure 24, assuming that the value counted 1905 representative of the number of bits of an input code string is total_len, and then the total_len fills the conditions in which it is a 1, the number of "1" (which is assumed to be ) in the bits of input of the bits of (sync_0_len - 1) from the bit of ^ fc 10 input at that moment is counted. If there is no "1", that is, if ni = 0, it is removed in one bit. In order to detect a synchronization code even when an n-bit error is mixed in the synchronization code in a case where the The process of bit insertion by the bit insertion unit 1211 so that the large distance between a portion other than the synchronization code and the synchronization code in an output code string is equal to or greater than 2 xn + 1, can be carried out next process. When total_len arrives at a value that fills formula (2), the number of "1" (which is assumed to be ni) of the bits of (sync_0_len = (2 xn + 1)) from the input bit in that moment in the output bits is counted. When the number of "1" is less than (2 x n + 1), * A * aA? LjAL? ^., *! to"* ? *? ** St? TO ? that is, when ni < (2 x n + 1), (2 x n + 1 - ni) the bits are removed (2 x n + 1 - ni). • In the output coding unit, and the input decoding unit, if the aforementioned processes are carried out so that the synchronization code insertion interval sync_period has a smaller number of bits than the code length of synchronization, the number of bits of the STUFF filler bits can be decreased so that you can improve coding efficiency. In particular, • when a synchronization code is long, or when many synchronization codes are inserted, the degree of improved coding efficiency due to the decrease in the number of bits of the STUFF padding bits is large.

For example, in a system for dividing a screen into one or a plurality of macro blocks or lines of macro blocks to insert the synchronization codes in each unit, • such as a GOB / slice in a dynamic image encoding, many dynamic image patterns are inserted, so that the degree of coding efficiency due to the decrease in the number of STUFF bits is increased. In addition, when a structure having a plurality of layers is multiplexed as shown in FIG.

Figure 28, synchronization codes having different lengths of compliance with the layers can be used. Figure 34 (a) shows examples of these synchronization codes. Among four kinds of synchronization codes, each SSC, SEC and PSC have 32 bits, which comprise "0" of 23 bits, and a "1" of 1 bit and 8 bits representative of the class of the synchronization code. On the other hand, a synchronization GSC code comprising "0" of 16 bits and a "1" of 1 bit, and is a code word shorter than the other synchronization codes. The reason why only GSC is the shortest code word is as follows. GOB is a coded unit, comprising one of a plurality of macro blocks (MB) and that is formed by dividing a screen into small regions so that there are usually more sync codes of the GOB layer than the other synchronization codes . Therefore, if the length of the synchronization code is decreased, the code quantity of the output code string may be decreased. In addition, it is possible to send more GSC if the amount of code is equal, and it is possible to divide the screen into small GOB regions for coding, so that the quality of a reproduced image can be improved when a transmission line error occurs.

A process for preventing a pseudo-synchronization as described in the fourth preferred embodiment is • say, a bit padding process to prevent the same bit pattern from occurring as a 5 sync code in a code string other than the synchronization code, can be carried out of course. If the bit padding process to decrease the probability of error detection of a synchronization code due to a transmission line error, e.g., a process of bit padding to prevent the same bit pattern as a shorter synchronization code (GSC in the example of Figure 34 (a)) from being produced in a bit string, for which only the same bit pattern is secured bit as the long bit length of the synchronization code (SSC, SEC, PSC in the example of Figure 34 (a)) does not occur, and it is carried out, it is possible to prevent the same bit patterns being produced as all the codes of • synchronization. This process can be carried out for code strings of all layers or for strings of lower layer code (GOB layer, macro block layer in the example shown) than a layer using the shorter code or for layer code strings (image layer, GOB layer, macro block layer) below a layer immediately above that layer. By way of _-2 - s & _ alternative, this process can be carried out only for strings of code of a predetermined layer. • In order to easily identify the synchronization codes of different lengths even when a transmission line error occurs 5, the processing of a synchronization code either before or after the synchronization code can be carried out in the following manner. (i) In a case where a code of synchronization comprising a plurality of "0" bits • and the subsequent "1" is used, the relative positions of the prolonged codeword and the short codeword of the synchronization code insertion position of "1" may be different. In the example of Figure 34 (b), the "1" 3211 of the PSC and the "1" 3412 of GSC are placed in the different position, all the bits (3413 to 3411, 3414 to 3412) placed in the same positions in the other • Sync codes are "0". In this way, since the large distance of the synchronization code and a As the partial code string of the same is increased, it is possible to easily identify the different synchronization codes even when a transmission line error occurs. (ii) A fill bit can be inserted before a short synchronization code. For example, if a bit -ta_j & -fill 3401 comprises one or a plurality of "1" is inserted before a short GSC, the large distance between • OSC and a partial code string of another synchronization code can be increased. (iii) A fill bit can be inserted after a short synchronization code. For example, a bit insert 3402 can be carried out after a GSC in order to increase the large distance from a portion identifying the class of a synchronization code in long synchronization codes. • (Fifth Preferred Modality) The fifth preferred embodiment of the present invention will be described below. In this preferred embodiment, the entire constructions of a dynamic image coding system and a dynamic image decoding system are the same as those in the first preferred embodiment with the exception of the processes carried out on the head and the final portions of a synchronization interval by an output coding unit 200 and an input decoding unit 800. Figures 27 (a), 27 (b) and 27 (c) are examples of a string 205 of exit code of a system of dynamic image coding in this preferred embodiment. In this output code string 205, a part 2701 of a code string of the last frame (frame nl) is placed after the synchronization code PSC and an information 2702 (SA) of the indicator 5 representative of a limit 2703 (a point of a code string of the current frame) between the code string 2701 and the current frame (frame n), that is, the boundary between the multiplexed code strings are placed such that the fill bit (STUFF in the Figure 4) no -? K 10 exists in at least one box. At this point, this output code string 205 is different from the output code string of Figure 4. In the output coding unit 200, of the dynamic image coding system, the number of bit resid_bit of the residual code strings of the table is checked during each synchronization code insertion position. When the sum of resid_bit and • the bit numbers of a PSC synchronization code and an SA information of the indicator is smaller than the bits of sync_period of the synchronization code insertion interval, the synchronization PSC code is sent before the residual code strings of the frame are sent to the exit code string 205. Then, the SA information of the indicator (representative of resid_bit in this case) is sent and then the residual code strings 2701 are sent. Then, the code strings in the following box are sent. The input encoding system 800 of the dynamic image decoding system, a synchronization code is detected in each of the insertion positions of the synchronization code. When the synchronization code is detected, it is determined that the SA information of the indicator and the residual information of the frame are placed after the synchronization code detected and the subsequent process is carried out. • For example, the boundary between a table n-l and a table n in Figure 27 will be described. After the decoding process immediately before 2704, the PSC of the synchronization code is completed and detected a synchronization code in the insertion interval of the subsequent synchronization code. When the synchronization code is detected, the information 2702 • the indicator is decoded and the bits of the code strings in the n-l box are derived. On the basis of This, the bits of the number of bits indicated by the indicator information are extracted from the code string immediately after the indicator information (towards 2703 in Figure 27), and the code string 801 is sent in a manner that these are placed after 2704.

In this preferred embodiment, the correction / error detection coding of a part or all of the • Strings of exit code can be carried out as shown in Figure 27 (a). In this case, all error correction / detection code classes 5 may be the same or different. In addition, as shown in Figure 27 (b), the correction / error detection coding may not be carried out. Also, as shown in Figure 27 (c), the frame length information indicator representative of the number of bits of the code strings of a frame as shown in Figures 15 and 16 can of course be inserted. In this case, the INDICATOR of the The frame length information may be representative of the number of bits from the frame synchronization PSC code to a PSC synchronization code of the following frame. In a case where the correction / error detection coding as shown in Figure 27 (a) the SA information of the indicator, the residual code 2701 chains of the nl table, and the code strings of the n-chart after 2703 combine to be a bit of information, and the '^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ • The SA information of the indicator, for which the error correction / detection coding has been carried out. In this case, the PSC synchronization PSC code (or a part thereof), the frame length information INDICATOR of the indicator information may be combined to carry out the correction / error detection coding. The examples of the STUFF fill bits will now be described. Figures 30 (a) and 30 (b) show examples of the code boxes of the STUFF padding bits as examples of the padding bits STUFF above mentioned. Both of Figures 30 (a) and 30 (b) are characterized in that the decoding can be carried out uniformly in the backward direction to a chain • output code, so that the starting position of the STUFF fill bits can be identified uniformly. Therefore, an error mixed in a code string can be detected by comparing the final decoding position of a code string immediately before the fill bit STUFF, with the starting position of the fill bit STUFF, and the point of game of backward decoding can - llí identify yourself when you use a coding system to decode in a backward direction from the code of • synchronization. Also, in the STUFF filler bits shown in the code boxes of Figures 30 (a) and 30 (b), the first bit is always "0", so that the error detection can be carried out by simplified decoding as will be described later. Figure 31 shows an example of a process of decoding of a code string containing the padding bits STUFF shown in the code boxes of Figures 30 (a) and 30 (b). Even though Figure 31 shows an example of the fill bit immediately before the insertion position of the synchronization code, it can carry out the same process by inserting a fill bit immediately before another optional synchronization code insertion position. In Figure 31, the • arrows 3101 to 3103 represent the examples of the final decoding positions of a chain of code that is indicated by "xxx- • •") immediately before the STUFF padding bit when the decoding is carried out in a forward direction, and the right end of each of the arrows indicates the final decoding position. When no error is mixed in a code string and decoding is carried out normally, the final decoding position of a code string immediately before the fill bit • STUFF is matched to the starting position of the STUFF fill bit as shown by arrow 3101. 5 On the other hand, when mixing an error in a code string, the final decoding position of a code string immediately before of the padding bit STUFF is shifted from the starting position of the padding bit STUFF as shown by arrows 10 3102 and 3103. In this case, it is determined that there is an error in the code string. In the decoding system, when the decoding of a code string immediately before the fill bit STUFF is completed, the fill bit STUFF before the next insertion position of the synchronization code is read, and it is determined if the fill bit read STUFF is coincident with the codes in • the code box shown in Figures 30 (a) and 30 (b). If the STUFF fill bit does not match any of the codes, it is determined that an error exists. When determining whether the fill bit STUFF is matched to the code box, a small bit error may be permissible. Therefore, it is possible to decrease the error detection of an error when an error is mixed in the same STUFF fill bit.

The code box in Figure 30 (a) always begins with "0" and has the subsequent bits of "1". Therefore, in order to carry out the error detection, it can only be determined whether the next bit towards the final decoding position of the code string immediately before the fill bit STUFF is "0" with the detection of error can be carried out only by the first "0" and some "1" subsequent. Therefore, even when the error detection accuracy decreases slightly, the performance required for • Decoding can be decreased. Therefore, in a case where a code frame starting from a specific bit pattern is used where all the STUFF padding bits comprise a specific bit or a plurality of bits. bits, the decoding process can be simplified. In addition, the STUFF filler bits shown in the code boxes of Figures 30 (a) and 30 (b) • contain a large number of bits of "1", and large distances from the synchronization code that contains a of "0" and a part of it are larger as shown in Figure 5, so there is an advantage in that the probability of a pseudo synchronization occurring is low. Specifically, in the code box of Figure 30 (a), all of only the first bits of the STUFF filler bits are "0" and all other bits iHl HA. are "0", so the large distance between the synchronization codes all of which are "0", and a part of • the same is (the length of the fill bit STUFF is -1). Also, in the code box of Figure 30 (b), only the first and last bits of the STUFF padding bits are "0" and all the other bits are "1", so the distances large since the synchronization code of a part of it are (the length of the fill bit STUFF is -2). In this way, if the large distances between the STUFF fill bit and the • sicronization code or a part thereof is selected to be greater than a predetermined value, e.g. (the length of the fill bit STUFF -2), so there is difficulty in producing a pseudo-synchronization code even when an error is mixed in a code string. Referring to Figure 32, this effect will be described. Figures 32 (a-0) and 32 (b-0) show examples of code strings when the usual padding bits (all bits are "O") and padding bits STUFFs shown in the code box of Figure 30 (a) are used, and Figures 32 (a-1) and 32 (b-1) show examples when a 1-bit error is mixed in Figures 32 (a -0) and 32 (b-0), respectively. As can be seen from Figure 32 (a-1), if only a 1-bit error is mixed in the usual padding bits where all the bits with "0", are ¿GÜ ^^ l-É produces the same bit pattern as in the synchronization code as it was shown by the broken line • in Figure 32 (a-1), so that a pseudo synchronization occurs. On the other hand, the fill bit STUFF 5 representative of the code box of Figure 30 (b), is not of the same pattern of the synchronization code even when an error is mixed as shown in Figure 32 (b-2) , so that no pseudo synchronization occurs. In this way, the fill bit in this The preferred embodiment has advantages since it is possible to easily detect an error of a code string, and it is difficult to produce a pseudo-synchronization code if an error is mixed in a code string, so that it is possible to provide an intense resistance to error . In addition, the fill bit in this preferred embodiment can decode uniformly in a backward direction to identify the starting position thereof, • that is, the final position of a code string immediately before the STUFF fill bit. For the Thus, after coding, by which the informational code string can be decoded in both forward and backward directions, it is carried out; the string of code immediately before STUFF can be decoded in the backward direction as is shown on arrow 3104 in Figure 31.

In the preferred embodiment, mentioned above, the padding bit STUFF can be determined in the following manner. (1) In a case where a 5 synchronization code contains "0" of the sync_0_len bits as shown in Figure 5, if all the bits of the STUFF filler bits or at least in the code insertion positions of synchronization are graded to be "1" the large distances between the "0" portions of the ^ fc code 10 synchronization and the STUFF fill bits can be increased. Therefore, it is possible to decrease the probability that an error is mixed in the STUFF padding bits to produce a pseudo synchronization. (2) The padding bit STUFF may be a code word representative of the length thereof. In the decoding system, the length of the STUFF from the point, where the coding of a • code string other than the padding bit STUFF is completed, is determined and the STUFF decoding is decoded to decode the STUFF length information. In this case, if both are coincident with each other, it can be determined that an error is mixed in the code string. In addition, the length of the code string of the 25 STUFF padding bits can be indicated by numbers . v-rn ** .- *. ,,. «Naife, fífo binaries. For example, if the STUFFs are 5 bits, a "5" can be indicated by binary numbers to make it • "00101". Alternatively, a derived value by taking a complement of "1" or "2" from a value indicated by 5 binary numbers, can be used as a code word of the padding bits STUFF. Therefore, the number of bits of "0" in the STUFFs is decreased so that it is possible to inhibit the occurrence of a pseudo synchronization similar to that mentioned above (1). 10 (3) In a case where coding is carried out • out using a code word that can be decoded in both forward and backward directions, it is required to decode the padding bits STUFFs in the backward direction from the end point of the box in the decoding system, to find the starting point (the boundary point between STUFF and another code word). In this case, the STUFFs can be determined to make a codeword, which begins with "0" (s) of 1 bit or a plurality of bits and which has the residuals of the "1", such as "01111111". In this way, if the STUFFs are decoded in the backward direction to look for the position of "0", it can be uniformly determined that the position sought is the starting point of the STUFFs. Also, in this example, the bits that are not the portion The initiality of the filler bits is "1" so that it is possible to decrease the probability of a pseudo-synchronization similar to that mentioned above. • (4) The padding bit STUFF may be a check bit, a parity check bit or the like 5 for an error correction / detection code of a part or all bits of an output code string. In this way, correction / error detection of an error bit mixed in the output code string can be carried out. 10 As described in the previous Examples, the • STUFFs padding bits are produced in accordance with a default rule, and STUFFs padding bits in an input code string are checked with the production rule in a decoding system. Whether determines that the padding bits STUFFs are against the production rule, it can be determined that an error is mixed in the input code string. Therefore, if a process to prevent a reproduced image from deteriorating greatly is carried out in a system of dynamic image decoding, it is possible to improve the quality of a reproduced image when an error is mixed in the input code string. Furthermore, in the aforementioned preferred embodiment, the synchronization code insertion interval syncjperiod can be determined in the following manner. (1) In a case where an error correction / detection code is used, a syncjperiod synchronization code insertion interval may be greater than the minimum number of bits required to carry out the synchronization detection by means of a coding system, that is, the sum of the length of a synchronization code and the maximum value of a check bit for an error correction / detection code. Since the mean value of the bit numbers is the last STUFFs padding bits of a frame is sync_period / 2, if syncjperiod has the minimum bits, by which synchronization detection can be carried out, it is possible to decrease the number bits of the STUFFs padding bits to improve coding efficiency. (2) In a case where an error correction / detection code is not used, a synchronization code insertion interval syncjperiod may be greater than the minimum number of bits required to carry out the synchronization detection by means of a decoding system, that is, the length of a synchronization code. Since the average value of the bit numbers of the last padding bits STUFFs of a frame is syncjperiod / 2, if syncjperiod, it has the minimum bits, by means of which the detection of • synchronization, it is possible to decrease the number of bits of the filler bits STUFFs to improve the coding efficiency. (3) In a case where the INDICATOR of the frame length information is used as shown in Figures 15, 16, 17 and 27, a syncjperiod synchronization code insertion interval may be shorter than the length of a synchronization code. For the • Therefore, it is possible to decrease the number of bits of the filler bits STUFFs to improve the coding efficiency. (4) In a case where the transmission / storage is carried out by splitting into packets or cells at certain intervals in a transmission line or storage medium, a syncjperiod synchronization code insertion interval may be matched to the intevalo of the packages or cells, or a divisor thereof. Therefore, since the head of the packets or cells is always placed in the synchronization code insertion position, it is possible to detect a synchronization code even when the packet or cell occurs due to packet loss or cell loss . (5) The synchronization code insertion interval syncjperiod is preferably shorter than the minimum number of bits in a frame required. Therefore, it is possible to decrease the number of bits of the filling bits 5 STUFFs to improve the coding efficiency.

(Sixth Preferred Modality) The sixth preferred embodiment of the flft 10 present invention will be described. Figure 35 shows examples of the output code strings a dynamic image coding system in this preferred embodiment. In these output code strings, in order to decrease the probability of error detection of a synchronization code due to errors, the bit insertion process is carried out as described in the preferred embodiments. • previously mentioned. In addition, the information, such as the header information is placed in 20 predetermined positions or in predetermined positions based on the synchronization code. Figure 35 (a) is a string of code before a bit insertion process is carried out, and the Figure 35 (b) is a string of code after it is performs a bit insertion process. In the i_Éi_éÉ =?.? ^ drawings, each of the portions 3201, 3202, 3261 and 3262 shown by the inclined lines, show the information placed in the predetermined position (the predetermined position based on the 5 synchronization code), and each hollow arrows 3211 and 3212 indicate the position, in which the information is inserted. The information 3261 and the code string information 3262 in Figure 35 (b) correspond to the information 3201 and the information 3202 of the code string in the Figure 35 (a), respectively. In some cases, when the • chain of code (a) is transformed into the chain of code (b) this information can be transformed, that is, the transformation from the information 3261 and the transformation from the information 3202 to the information 3262). In Figure 35 (b), 3203 represents a bit inserted in the bit insertion process. Since • the bit string subsequent to the inserted bit is shifted backwards through the bit insertion process, a The part of the code chain immediately before the information to be inserted in a predetermined position is shifted so that the information is inserted in the predetermined position. For example, assuming that the total of the numbers of the bits inserted from the synchronization code 3205 immediately before the information 3201 is Nsl, the Nsl bits indicated by the sign 3221 in the Figure • 35 (a) immediately before the 3201 information, they can be moved to the portion of the 3231 sign in the Figure 35 (b) immediately after the information 3201. If the information such as a representative indicator of a specific position in a code string is contained in the information 3201 and / or 3202, this can be transformed. Specifically, for example, if m 10 the information representative of the position indicated by the arrow 3241 is contained in the information 3201, the information representative of the position in the information 3261 is transformed in order to indicate the representative position of the arrow 3251 after the position by the number Nsl of the inserted bits. •

Claims (32)

1. CLAIMS; • 1. An encoding system comprising: a coding means for encoding a string of input code to an error correction / detection code comprising an information bit and a check bit; and means for assembling the code string in order to insert a synchronization code at a position of a plurality of code insertion positions of • predetermined synchronization in an output code string, to place the information bit in an optional position in the output code string, and to place the check bit in a position other than the 15 insertion positions of the code synchronization in the chain of the exit code to assemble the chain of exit code. A decoding system comprising: a synchronization code detection means 20 for detecting a synchronization code in a plurality of predetermined synchronization code insertion positions, based on a code string, which is coded to an error correction / detection code comprising an information bit and a check bit; a code string resolution means for resolving the code string in order to extract the information bit from the error correction / detection code and the check bit from the error correction / detection code 5 placed in a position that does not are the synchronization code insertion positions; and a decoding means for receiving the information bit and the check bit extracted by the resolution means of the code string to decode the error correction / detection code. # 3. An encoding system comprising: a means of transforming the code chain to transform an input code string other than the synchronization codes placed in a plurality of predetermined synchronization code insertion positions in a chain of exit code, so that a large distance from the code • synchronization is equal to or greater than a predetermined value; 20 a coding means for encoding a code string transformed by means of the code stream transformation means, to an error correction / detection code comprising an information bit and a check bit; and a means of assembling the code string to insert a synchronization code into any one of a • plurality of predetermined synchronization code insertion positions in the output code chain, to place the information bit in an optional position in an output code string and to place the check bit in a position other than the positions of inserting the synchronization code in the output code string to assemble the string of 10 exit code. • 4. A decoding system comprising: a synchronization code detection means for detecting a synchronization code in a predetermined synchronization code insertion position 15 based on a code string, which is encoded to a code of correction / error detection comprising an information bit and a check bit and • towards the synchronization code; means for resolving the code string in order to resolve the code chain to extract the information bit from the error correction / detection code and the error correction / detection code check code placed in a position that does not be the insertion position of the synchronization code; a decoding means for rebinding the information bit and the check bit extracted by the • means of resolving the code string to decode the code is error correction / detection; and 5 a means of transforming the code chain to transform a code chain other than the synchronization code, which is transformed so that a large distance from the synchronization code in the code chain decoded by the means of 10 decoding is equal to or greater than the value • Default and that exists at the insertion position of the synchronization code, towards the original code string. 5. An encoding system comprising: an encoding means for encoding an input code string to an error correction / detection code; • a means of inserting the synchronization code to insert a synchronization code in 20 the code string; and a determining means for determining the number of bits of an information to be coded to the error correction / detection code immediately before the synchronization code in the code chain, 25 the encoding means encodes the error correction / detection code immediately before the synchronization code using a degenerate code that degenerates • adaptively on the basis of the number of bits determined by means of determination. 6. A decoding system comprising: a decoding means for decoding a code string, which is coded to an error correction / detection code and into which a synchronization code is inserted; 10 a means of synchronization code detection • to detect the synchronization code in the code chain; and a determining means for determining the number of bits of an information that is encoded to an error correction / detection code immediately before the synchronization code in the code string detected by the code detecting means. • synchronization, the means of code decoding is 20 decodes identifying whether the error correction / detection code immediately before the synchronization code is a degenerate code based on the determined result of the determination means. 7. A coding system comprising: to? -Is?? .í. «- v-irt tflt? Ffl-r ^ fr: a ^ te < ^ ^ rti8 ^ A * A¿ ^^ an encoding means for encoding a code string containing classes of input information to the error correction / detection code; and a switching means for switching the class of error correction / detection code in accordance with the classes of the input information in the code chain. 8. A decoding system comprising: a decoding means for decoding a "J 10 code string, which is coded to a different kind of error correction / detection code in accordance with the information class, to generate the original information, and a means to determine the type of correction / detection code error on the basis of the kind of information generated by the decoding means, to inform the decoding means • 9. A coding system comprising: a means of transforming code string 20 to transform a code string of input other than synchronization codes, which are placed in a plurality of predetermined synchronization code insertion positions in an output code string in a range of a predetermined number of bits 25 before and after the code insertion positions of synchronization predetermined in a chain of exit code so that a large distance from the code of sincroni tion is equal to or greater than a predetermined value; 5 an encoding means for encoding a code string transformed by the code string transformation means into an error correction / detection code comprising an information bit and a check bit; Y • 10 a code string assembly means for inserting a synchronization code into any of a plurality of predetermined synchronization code insertion positions in the output code string, to place the information bit in a single position 15 optional in the output code chain, and to place the check bit in a position other than the synchronization code insertion positions in the • output code string to assemble the output code string. 10. A decoding system comprising: a means of detecting synchronization code for detecting a synchronization code in a predetermined portion of synchronization code insertion in a range of a predetermined number of bits before and 25 after the predetermined synchronization code insertion position, based on a code string that is encoded to a correction code / • error detection comprising an information bit and a check bit and towards the synchronization code; 5 a code string resolution means for resolving the code string in order to extract the information bit from the error correction / detection code and the error correction / detection code check bit placed in a position that does not be the position 10 insertion of the synchronization code; • a decoding means for receiving the information bit and the check bit extracted by the resolution means of the code string to decode the error correction / detection code; and 15 a means of transforming the code chain to transform a code chain other than the synchronization code that is transformed so that a large distance from the synchronization code in the decoded code chain by the means of The decoding is equal to or greater than a predetermined value and exists at the synchronization code insertion position and in a range of a predetermined bit number before and after the synchronization code insertion position, towards the synchronization code 25 original code. 11. A coding system comprising: a multiplexing means for multiplexing the different classes of compressed codes, which are obtained by compression coding of a signal of 5 input in order to produce a multiplexed code string; and a code string assembly means to support the multiplexed code string for assembling an output code string, the means for assembling the code string inserts a synchronization code into any of a plurality of code insertion positions. synchronization code periodically predetermined in the output code string. 12. A coding system comprising: a multiplexing means for multiplexing the classes of compressed codes, which are obtained by compression coding of an input signal in order to produce a multiplexed code string; and a code string assembly means for supporting the multiplexed code string in order to assemble an output code string, the means of assembling the code string by inserting a synchronization code into any one of 25 a plurality of code insertion positions of Tlr .i-Bfen t'i &M .iy.ii. "'Tour-?' || g ^ | || periodically synchronize predetermined in the output code string, and insert appropriately a bit of • fill in the output code string. 13. A coding system comprising: a multiplexing means for multiplexing classes of compressed codes, which are obtained by compression coding of an input signal to produce a multiplexed code string; and a means of assembling the code string for mg 10 to support the multiplexed code string in order to assemble an output code string, the means of assembling the code string by presetting a plurality of synchronization code insertion positions periodically placed in the 15 output code string, inserting an information indicating a limit of the multiplexed code string and inserting a synchronization code into any of a plurality of synchronization code insertion positions. 14. A coding system according to any of claims 11 to 13, wherein the multiplexing means multiplexes a compressed code that is encoded by compression for each of the frames or segments of the frames of an image signal of entry, 25 for each of the tables or segments of the table and wherein the means of assembling the code string inserts a synchronization code into an insertion position • the synchronization code immediately before or after the end portion of each synchronization unit 5 multiplexed for each of the frames or segments of the frames of the multiplexed code chain. 15. A coding system according to any of claims 11 to 13, further comprising a chain transformation means of 10 code to transform a string of code other than the • synchronization code, which is placed at the insertion position of the synchronization code in the output code string so that a large distance from the synchronization code is equal to or greater than one value 15 predetermined. 16. A decoding system comprising: a means of detecting the synchronization code for detecting a synchronization code in an output code string: a demultiplexing means for demultiplexing based on the position of the synchronization code detected by the means for detecting the synchronization code from the input code string in order to produce a compressed code string; and a decoding means for decoding the compressed code towards an output of a reconstructed signal, the synchronization code detecting means detects the code at a plurality of periodically predetermined synchronization code insertion positions in the input code string. A decoding system according to claim 16, further comprising a means of code string transformation to transform a code chain other than the synchronization code, which is transformed so that a large distance from the code of synchronization is equal to or greater than a predetermined value at the insertion position of the synchronization code of the input code string, towards the original code string. 18. A coding system comprising: means for assembling the code string to insert a synchronization code into one of a plurality of periodically predetermined synchronization code insertion positions in an output code string, and to insert appropriately in the string of code, a bit of stuffing, which is capable of t? gS ^^ | decode uniformly in a backward direction of the exit code string. • 19. A coding system according to claim 18, wherein the means of assembling the The code string inserts a fill bit immediately before any of the plurality of synchronization code insertion positions in the output code chain. 20. A decoding system comprising: a decoding means for decoding an input code string wherein a synchronization code is inserted into any of a plurality of periodically predetermined synchronization code insertion positions and where it is inserted 15 appropriately a stuffing bit that is capable of being coded uniformly in a backward direction; and an error detection means for detecting a • error in the input code string comparing a decoding end position of a code string 20 immediately before the fill bit, which is decoded by the decoding means, with a starting position of the fill bit. 21. A decoding system according to claim 20, wherein the fill bit is 25 inserts immediately before any of the plurality of synchronization code insertion positions in the input code string. • 22. A decoding system according to claim 19, wherein the means of 5 decoding decodes a code string immediately before the fill bit to a backward direction from the starting position of the fill bit. 23. A coding system comprising: fe 10 a means of assembling a code string for inserting a synchronization code into any of a plurality of periodically predetermined synchronization code insertion positions in an output code string, and for insert properly the 15 code string, a fill bit that is capable of being decoded uniformly in a backward direction of the output code string and whose large distances • from the synchronization code and a part of it are equal to or greater than a predetermined value. 24. A coding system according to any of claims 18 to 23, wherein the fill bit is placed immediately before the synchronization code. 25. A decoding system comprising: a decoding means for decoding an input code string, wherein a synchronization code is inserted into any of a plurality of periodically predetermined synchronization code insertion positions and where it is inserted suitably a stuffing bit, the stuffing bit is capable of being uniformly decoded in a backward direction and the large distances from the synchronization code and a part thereof being equal to or greater than a predetermined value; and an error detection means for detecting an error in the input code string by comparing a decoding end position of a code string immediately before the fill bit, which is encoded by the decoding means with a starting position of the code. fill bit. 26. A decoding system according to any of claims 20, 22 and 25, wherein the fill bit of the input code string is placed immediately before the synchronization code. 27. A coding system according to any of claims 11 to 13, wherein the multiplexing means produces a code string, multiplexing the compressed code string for each of a plurality of layers, and the assembly means of The code string supports the multiplexed code string to add a synchronization code to at least a portion of the plurality of layers to produce an exit code. 28. A coding system according to claim 27, wherein the assembly means of the code chain causes the synchronization codes to have different lengths in a part or all of the plurality of layers. 29. A coding system according to claim 27 or 28, further comprising a means of transforming the code chain to transform a code chain other than the synchronization code into a part or all of the layers, to which the synchronization code of the output code string is added so that a large distance from the synchronization code is equal to or greater than a predetermined value. 30. A coding system according to claim 29, further comprising a means of transforming the code chain to transform a code chain other than the synchronization code or a part or all of the layers, to which is added the synchronization code of the output code string of ^^ áSg? jj? j way that a large distance from a synchronization code that has a shorter length of codes • Synchronization having different lengths, is equal to or greater than a predetermined value. 31. A decoding system according to claim 16, wherein the input code string comprises a multiplexed code string, which is multiplexed for each of a plurality of layers, with a synchronization code being added to at least a • 10 part of the plurality of layers. 32. A decoding system according to claim 31, further comprising a means of transforming the code chain to transform a code string other than the synchronization code that 15 is transformed so that a large distance from a synchronization code having a shorter length of the synchronization codes having different lengths in a part or all of the added layers is equal to or greater than a predetermined value.