MXPA98007024A - Device generator of pn codes and radiocommunication system mo - Google Patents

Abstract

The present invention relates to a PN code generating apparatus, a code of the predetermined number of stages, is generated using a primitive polynomial G (x), then the code content of each of the stages is shifted to the next stage. Thus, a state establishment section obtains the status of a code of the PN code generating section, after having moved the specific times, from a code state of the PN code generating apparatus at a certain time, based on xi mod. G (x), where i is the number of times of displacement

Description

APPARATUS GENERATOR OF PN CODES AND MOBILE RADIOCOMMUNICATION SYSTEM.

Background of the Invention The present invention relates to a PN code generator apparatus, applicable to a mobile device in a mobile communication system, in which an intermittent reception is effected, for example, a CDMA communication system (Code Division Multiple Access). ) and a mobile radio communication system.

Description of Related Art Recently, mobile communications using a CDMA system have caught the attention of the public in the field of digital mobile communication. In the United States of America, the standardization of a mobile communication system within a CDMA system has been carried out by the TIA (Association of the Telecommunications Industry), which is included in the "Standard for Station Compatibility". Base - Mobile Station, for the Digital Broadband Dual Spectrum System Broadband Spectrum (IS-95-A) and so on In a CDMA system, the transmission data are spectrum widens, with a spreading code REF .: 28246 which is different for each channel. For example, the IS-95-A includes a short PN code of the 15th order (the period is approximately 26 ms.) And a long PN code of the 422 order (the period is approximately 41 days), consumed in a spectrum widening. Thus, the long PN code is also used in the randomization of a direct link and in the assignment of an insertion position of the energy control bit. Fig. 1 illustrates a schematic configuration of a conventional PN code generating apparatus. As an example, the case of a PN code of the 422 order is illustrated, which requires 42 delay elements in a shift register. The code generating section PN 100 comprises a feedback register with feedback, consisting of 41 circuits EX- R (Exclusive circuit 101, 42 time delay elements 102, 42 coefficients of primitive polynomials 103 and 42 multipliers 104. In the PN code generating apparatus described above, the initial values of the delay elements are set in such a way that not all the values are 0 at the same time and the value of the delay element 102 is offset, corresponding to the input of a displacement clock 105, considering the feedback of the value of the last slot.

Any output of the delay element is obtained as a PN code. In a CDMA mobile communication system, a mobile device establishes the initial value of the delay element 102 in a timing of the system in the acquisition process of synchronization with a base station, then generates a PN code, using a chip ratio consumed in the widening, in a CDMA system, in the form of a scroll clock. A mobile device in a mobile communication system, performs the reception of monitoring, to verify a call, once it is in a specific predetermined period, with a base station, when waiting. This is called an intermittent reception, in which all the circuits that are possible, except for a chronometer to measure the timing of the next monitoring reception, are turned off during the period of non-reception, to reduce the consumption of electrical energy. However, in a conventional PN code generator apparatus, since it is necessary to maintain the synchronization of a code pattern of a long PN code for a period much longer than the period of intermittent reception, even during the period of non-reception , it is not possible to turn off the appliance, which brings the problem of not being able to achieve the reduction of the electric power consumption.

Brief Compendium of the Invention The present invention is carried out, taking into account the facts mentioned above. The object of the present invention is to provide a PN code generating apparatus and a method capable of acquiring the synchronization of a long PN code., immediately when the device is restarted, after the stopped state in an intermittent reception. The first aspect of the present invention adopts the constitution comprising a PN code generation section, to generate PN codes with a predetermined length, using primitive polynomials G (x), then shifting the content of the code and a section of establishment. state, to obtain a code state of the PN code generating section, after having been moved the specific times, from a code state of the PN code generating apparatus for a certain time, based on the polynomial x ^ modG x ), where i is the number of trips. The first polynomial x nodG x), is previously calculated or obtained, where i is the number of displacements necessary for the PN code generation device, in the case that it is assumed to be operating, during the period of time since turn off, until the next power on. The state in which the PN code generator is assumed should be present when the next ignition is obtained, using xxmodG (x), which indicates only the number of displacements corresponding to the length of the PN code (42 displacements in this example), which are sufficient to obtain the state of the generator apparatus of PN codes (the content of the delay element), just after being turned on, using the state of the PN code generating apparatus (the content of the delay element), just after it has been turned off. Accordingly, it is possible to calculate the state of the PN code generating apparatus, at the time of restarting a monitoring reception, while the PN code generating apparatus is being turned off during the time of non-reception and turned on just before the timing of the reception. next monitoring reception. This makes it possible to keep the PN code generation apparatus off, during almost all the time of non-reception, which results in the reduction of the electric current consumed.

The second aspect of the present invention comprises a masking calculation section, to acquire the number of offsets: which corresponds to a period of time, until the PN code generating apparatus restarts after having calculated ^ modG? ). It is possible to make a device generating PN codes with the code status, maintaining a synchronization with a much smaller number of displacements, than the number of displacements: i by means of providing a, to mask the calculation section. The third aspect of the present invention comprises a masking table, in which a plurality of polynomials x1modG (x) obtained, for a plurality of numbers of displacements, previously selected, are recorded as masking values and a section of masking assignment, to read the masking value of the masking table, based on the value of n, to obtain the status of a device generating PN codes, consequent to the time n * T (n is an integral number), wherein the minimum period for calculating the target state of a PN code generating apparatus is T. It is possible to obtain the state of a PN code generating apparatus, after moving a specific number of times, from the state of the generating apparatus of PN codes at a certain time, with only the number of displacements that is an integral number of times, of the delay elements of the shift register.

Brief Description of the Drawings Fig. 1 is a schematic diagram of a conventional PN code generating apparatus; Fig. 2 is a configuration diagram of a feedback shift register, with a remaining general circuit; Fig. 3 is a configuration diagram of a feedback shift register, with the remaining, partially improved general circuit, illustrated in Fig. 2; Fig. 4 is a diagram showing a configuration of a feedback shift register, to obtain the polynomial residue M (x) x2; Fig. 5 is a diagram showing a configuration of a PN code generating apparatus and its change of status at a certain time; Fig. 6 is a configuration of a PN code generating apparatus, configured based on the remainder; Fig. 7 is a schematic diagram of a configuration of a PN code generating apparatus, in accordance with the first embodiment of the present invention; Fig. 8 is a flow chart, for calculating the state of a PN code generating apparatus, in the first embodiment of the present invention; Fig. 9 is a schematic diagram of the configuration of a PN code generating apparatus, in accordance with the second embodiment of the present invention; Figs. 10A and 10B are a flowchart, for calculating the state of a PN code generating apparatus, of according to the first embodiment of the present invention; Description of the Preferred Modality Before explaining in detail, the preferred embodiments of the present invention, an explanation of the principle of calculation is given, to obtain the state of a PN code generating apparatus, after having been displaced, the specific times, of state of a device generating PN codes, at a certain moment. First, it is considered a cyclic code. A cyclic code (n, k) (n: length of the code, k: length of the information bit) is obtained as a residue, when M (x) xn-k is divided by G (x), where a polynomial with a bit of information as an efficient, is represented as M (x) of (kl) 2 order, which is shown in the following formula.

M (X) .n-k = Q (x) G (x) + R (x) (1) In this, R (x) of (n-k-l) 2 order, is a polynomial of residue, to give the value of redundancy bit. Formula (1) is transformed as shown below.

M (x) xn k = Q (x) G (x) (2) These results in a code M (x) n-k-R (x), which can be divided by G (x) without a residue.

A division circuit for, G (x) = xm + gm_1x x + + glx + g0 (m = n-k) it is generally achieved using a feedback shift register, illustrated in Fig. 2. To obtain R (x) in formula (1) using the circuit of Fig. 2, the (k) bits of the highest coefficients orders of M (x), are entered sequentially to the left input and the (nk) bits that contain 0, are entered. Then, the residual corresponding to a coefficient of R (x) is obtained in (m) numbers of the delay elements, in the register of displacement with feedback. Right here, entering (n-k) bits of 0 is the equivalent to (n-k) bits of smaller orders when (n) bits of the coefficients are entered, with higher orders of M (x). However, it is obvious that (nk) bits of 0, should be entered with the configuration of Fig. 2, which is modified to the configuration that is illustrated in Fig. 3. In this configuration, to enter (k) bits from the coefficients with higher orders of M (x), it is sufficient to obtain a residue corresponding to a coefficient in m numbers of elements of delay in the register of displacement with feedback. This configuration results in the equivalent to automatically multiplying xn-, by means of modifying an input position of the coefficient of a polynomial divided from the lowest order, to the highest order, of a generating polynomial. Generally, a cyclic code is calculated using a feedback register, as illustrated in FIG. 3. FIG. 3 illustrates a circuit for obtaining a polynomial residue M (x) xn-k. When applying this property, a circuit to obtain a residual polynomial M (x) x2, as illustrated in Fig. 4. This is, in the case of obtaining a polynomial residue M (x) x3"(i = m ), an input is executed to an EX-0R circuit (EXCLUSIVE OR) corresponding to (i) order, in the shift register with feedback, and in the case of obtaining a polynomial residue M (x) (x ^ + x3 ) (i! = j, i, j = m), the revenues are executed by the EX-OR circuits, corresponding to order i and order j, respectively at the same time in the record with feedback, which is obvious from Then consider the case of obtaining a residue of M (x) x1, when i> m.Formula (3) below, is obtained, by replacing nk in Formula (1), with i.

M (x) 1 = Q (x) G (x) + R (x) (3) Formula (3) is also expressed in another Formula, below.

R (x) = M (x) x1 modG (x) (4) Using the characteristics of the residue calculation, formula (4) is transformed as shown below.

R (x) = M (x) (x1 modG (x)) modG (x) (5) R (x) = M (x) S (x) modG (x) (6) Where S (x) = xx modG (x) and S (x) is a polynomial of less than (m-l) 2 order. According to the orders whose coefficients are 1 in S (x), when entering (k) bits, of a coefficient with a higher order in M (x), for each circuit EX-OR, sequentially in a record with feedback ( division circuit) at the same time, a residue is obtained, even in the case of M (x) x1 (i >; m). The technical argument to obtain the state of a PN code generator (the content of the shift register), after moving the specific number of times, from the state of the PN code generator, to a certain moment, without the number of displacements , is solved by applying the previous principle. It is assumed that a primitive polynomial (generator) of a PN code generator is G (x) of (m order) and the state of a PN code generator at a certain time is M (x) of (m order ). However, the configuration of the PN code generator is composed from the configuration illustrated in Fig. 2, except for an input of a dividend polynomial, assuming conveniently a PN code generator with the input. In Fig. 2, the content of each shift register is 0, after being deleted. That state is changed by the state of a PN code generator at a certain moment, after sequentially entering (m) bits, from a coefficient with the highest order in M (x), to a left input. To obtain the state of a PN code generator, which has been moved a specific number of times (i times), at a certain time, sequentially (i) bits of 0 are input to the left input, which is equivalent to the operation of an ordinary PN code generator. This operation is also equivalent to obtain the remainder of M (x) x, from the point of view of the division. Therefore, by obtaining x ^ modG? X) and entering (m) bits sequentially, a coefficient with the highest order of M (x), according to each order of coefficient 1 of x1modG (x), for each circuit EX-OR of a record with feedback (division circuit), the state is obtained when it has been displaced i times (residue). Accordingly, when obtaining x1 mod G (x) in advance, it is possible to obtain the state after moving i times, with only the times of m bits displacement, which allows drastically reducing the number of opening / closing times in the case of a CMOS circuit, even when small sums are necessary in a division circuit. The basic principle is as described above. An example is shown in detail in the third-order polynomial G (x) = x3 + x + l. G (x) generates a PN code of a period of 23-l. Fig. 5 illustrates a configuration and state changes during which, one bit is shifted from the state, in a certain period of time; and a PN code generator. An explanation is given to obtain the state, after five displacements from the beginning of the state, to a certain period of time; t, using the above mentioned principle.

First you get ^ odGí).

Based on the obtained residue, 1, 0 and 0, according to this order, they are entered in the configuration that is illustrated in Fig. 6. The last state illustrated in Fig. 6 is obviously the same as the state in Fig. 6. t + 5, of Fig. 5.

Thus, it is possible to obtain the status of a PN code generator (the content of the shift register) after moving the specific number of times from a certain time, without moving the specific number of times, using the state of the PN code generator at a certain time. The embodiments of the present invention are explained in detail, with reference to the drawings, in the following.

First Modality Fig. 7 is a diagram illustrating the schematic configuration of a PN code generating apparatus in the first embodiment of the present invention. A PN code generating apparatus in this embodiment comprises, a PN 100 generating section, for generating a 42-stage PN code, a parallel converter / series 200 section, for converting between parallel / serial • the content of a challenge element. of a PN 100 code generating section, a maintenance section of the masking value 300 to maintain the masking value, a masking calculation section 400, to calculate the masking value, which must be maintained by the maintenance section of the masking value 300, an AND block 500, to calculate the AND value of an output of the maintenance section of the masking value 300 and an output of the parallel converting section / series 200. In the code generating section PN 100, the 42 EX-OR 101-1 to 101-42 circuits are connected in series and the 42 delay elements 102-1 to 102-42 are inserted in series-, after the output of circuits EX-OR 101-1 to 101-42, respectively. 42 multipliers 103-1 to 103-42, are prepared respectively, corresponding to circuits EX-OR 101-1 to 101-42. Each of the multipliers 103-1 to 103-42, respectively, multiplies each of the coefficients of the primitive polynomials gO to g41 and an output in the last of the elements of delay 101-42 to exit a multiplied value for each one of circuits EX-OR 101-1 to 101-42, respectively. A record with feedback is composed of 42 circuits EX-OR 101-1 to 101-42, 42 elements of delay 102-1 to 102-42 and 42 multipliers 103-1 to 103-42, in which, 42 coefficients of polynomials Primitives are respectively multiplied. The initial setting of values is executed in such a way that the initial values of the delay elements 102-1 to 102-42 are not all 0 at the same time. The value of the delay element is shifted in each input of the multipliers 104, considering the feedback of the last stage value. A PN code is obtained by bringing the output of any delay element. The parallel converter section / series 200 is composed of 42 closing sections connected in series 201-1 to 201-42 the closing sections connected in series 201-1 to 201-42 respectively close the content of the delay elements and transfer the content closed to a section of adjacent posterior closure. In other words, the parallel / serial 200 converter section closes the PN code in 42 stages, inputted in parallel from the PN code generating section, so that the serial output works as a shift register. The maintenance section of the masking value 300 is composed of 42 closing sections 301-1 to 301-42, each one being prepared correspondingly to the circuits EX-OR 101-1 to 101-42, in the section generating PN codes . The closing sections 301-1 to 301-42 are for closing the masking value in the masking calculation section 400. The masking calculation section 400 obtains the number of times of shifts, which is the required number of times of offset, in the code generating section PN 100, to calculate the state (the content of the delay element 102) of the code generating section PN 100, at the specific time, after the state (the content of the delay element 102) of the generating section of PN 100 codes at a certain time. S (x) = x ^ odGy) is obtained by replacing i by x1 mod G (x) in Formula (6), with the number of displacement times obtained. The AND 500 block is composed of 42 AND 501-1 to 501-42 doors, each prepared between each of the sections of closing 301-1 to 301-42 in the maintenance section of the masking value 300 and each of the circuits EX-OR 101-1 to 101-42 in the code generating section PN 100. An operation of a generating apparatus of PN codes, configured as described above, is explained with reference to the flow chart of FIG. 8. Up to now, the code generator section PN 100 is executing the normal code generation (S201). When it is judged that the determined condition is set to turn off the code generator section PN 100 (S202), the closure sections connected in series 201-1 to 201-42 each close the content of each of the elements of delay 102-1 to 102-42 respectively, and the inerto timer starts concurrently (S203). Thus, the operation of the code generating section PN 100, except for the stopwatch, is turned off (S204). Thus, after the stopwatch is finished (S205), a receiving preparation is started (S206). The time set in the stopwatch is a bit shorter than the next monitoring reception timing, including the estimated time of the process in which the masking calculation section 400, calculated the masking value. As soon as the receiving preparation is started, the time period for restarting the PN 100 code generating section from the sections is first obtained. previously closed 201-1 to 201-42, closed in the code generating section PN 100 (S207). Then, the number of times of displacements in the code generating section, corresponding to this period of time, until the reset and the number of displacement times obtained are obtained, is assigned as i (S208). Then, the masking calculation section 400 calculates to x1 mod G (x) to obtain a masking value (S209). Each of the closing sections 301-1 to 301-42 in the maintenance section of the masking value 300 maintains the masking values, calculated in the masking calculation section 400 (S210). Then, the delay elements 102-1 to 102-42 in the code generating section PN 100 are erased to the value of 0 (S211). When using the closing sections connected in series 201-1 to 201-42 in the parallel converter / series 200 section, having the closed content of the delay elements 102-1 to 102-42 which is equivalent to the previous state of the generator of PN codes, as a shift register, the number of clocks corresponding to the number of steps of a PN code (in this case, 42 clocks), are entered as the scroll clock 202 and the shift clock 104 to the generating section of PN codes 100, obtaining the projected state of the code generating section PN 100 (S212).

When the state of the code generating section PN 100 reaches the state after a specific number of times (i), the displacement clock 104 is entered into the desired timing, corresponding to the number of offsets (i) and the generation of the PN code in the code generating section PN 100 (S213). Thus, it is possible to calculate the state of a PN code generator, after it has been moved a specific number of times, from the state of a PN code generator (the content of the shift register) in a certain time with fewer numbers of displacements that the specific number of times of displacements, which allows to turn off the generating section of PN codes, during a period of non-reception, in an intermittent reception system. For example, in a CDMA mobile communication system, according to the IA-95-A standard, the minimum non-reception period is 1.28s. and the displacement clock used is 1.2288 MHz. When it is assumed that 80ms. in 1.28s. it is used in monitoring the reception, approximately 1.20s. will be for a period of non-reception, which corresponds to 1,474,560 times of travel. When applying the previous modality, it is possible to calculate the following state with 42 times of displacements, just before the monitoring begins, instead of moving a generating section of PN codes 1,474,560 times, which reduces 1,474,560-42) times of displacement of operations of a PN code generation section. Additionally, in the first embodiment described above, a period of time until the start is obtained, in step S206. However, the number of times of displacement during a period is possible, to start in advance, since the period of non-reception is already known. In the case that the number of times of displacement is acquired directly in advance, as in this case, it is not necessary to always calculate the period.

Second Modality A PN code generating apparatus of the second embodiment of the present invention comprises a mask value table 601, in which a plurality of pre-calculated masking values and an instruction section and masking assignment 602 are stored to select a masking value in the masking value table 601 to be used, instead of the masking calculation section 400 of the first embodiment of the present invention. Fig. 9 illustrates a diagram of a schematic configuration of a PN code generating apparatus, in the second embodiment of the present invention. Additionally, same parts that were described in the first modality above, have the same symbols. In Fig. 9, 100 denotes a code generating section PN 100 which is the same as any conventional section and the shift register is comprised of 42 circuits EX-OR 101-1 to 101-42, delay elements 102- 1 to 102-42 and multipliers 103-1 to 103-42, to multiply the 42 coefficients of the primitive polynomials gO to g41. 200 denotes a parallel / serial converter section, which is composed of the closure sections connected in series 201-1 to 201-42, each to close the content of the delay elements 102-1 to 102-42 in the code generating section PN 100. 300 denotes a maintenance section of the masking value and 500 denotes an AND block. In the mask value table 601, the masking values previously calculated, for example, for 2: LxT (i> 0) are recorded, while T is the minimum period for obtaining the state of the code generating section PN 100, when calculated. The masking assignment and instruction section 602 controls a read masking value of the masking value table 601, based on the value of n, to calculate the state of the PN 100 code generating section (the content of the masking elements). delay) time nxT (n is a whole number) after the state of the section generator of PN 100 codes (the content of the delay elements) in a certain time. An operation of a PN code generating apparatus, configured as described above, is explained using the flow chart of Fig. 10. Now, the code generator section PN 100 is executing the normal code generation (S401). When it is judged that the determined condition is set to turn off the code generating section PN 100 (S402), the closing sections connected in series 201-1 to 201-42 each close the content of each of the elements of delay 102-1 to 102-42 respectively in a timing. such that a period of time until the restart is an integral number of times of pe of minimum time T and the internal chronometer starts concurrently (S403). Thus, the operation of the code generating section PN 100, except for the stopwatch, is turned off (S404). Thus, after the stopwatch is finished (S405), a receiving preparation is started (S406). The time set in the stopwatch is a bit shorter than the next monitoring reception time, which is the same as in the first mode. As soon as the receiving preparation is initiated, the instruction and masking allocation section 602 obtains the period of time to restart the PN 100 code generating section from the sections previously closed 201-1 to 201-42, closed in the generating section of PN 100 codes as nxT (n is an integral number) (S407). The n of the period of time that will be until the restart (nxT), is converted into a binary number (S408). Thus, it is judged whether aj = l while j = 0, or not (S409 and S410). When the result shows that aj = l, the instruction section and masking assignment 602 reads the masking value for 2:? XT, from the masking value table 601 to keep the closing sections 301-1 through 301- 42 in the maintenance section of the masking value 300 (S411). So then, after the delay elements 102-1 to 102-42 in the code generating section PN 100, are erased to the value 0 (S412), using the closure sections connected in series 201-1 to 201-42 in the parallel converter section / series 200, the closed content of the delay elements 102-1 to 102-42 having the number of clocks corresponding to the number being equivalent to the state of the code generating section PN 100, as shift register. of steps for a PN code (in this case 42 clocks) are entered as scroll clock 202 and scroll clock 104 to the code generating section PN 100, obtaining the projected state of the code generating section PN 100 (S413). At this time, the contents of the delay elements 102-1 to 102-42 are enclosed in the closing sections connected in series 201-1 to 201-42 (S414). Then, it is judged whether j exceeds k, or not, as long as j = j + l (S415). Until j exceeds K, the process described above is repeated, from step S409 to S414. When the state of the code generating section PN 100 reaches the state after a specific number of times (i), the displacement clock 104 is entered into the desired timing, corresponding to the number of offsets (i) and the generation of the PN code in the code generating section PN 100 (S416). Thus, according to the second embodiment of the present invention, it is possible to calculate the state of a PN code generator, after it has been moved a specific number of times, from the state of a PN code generator (the content of the shift register) in a certain time with fewer numbers of offsets than the specific number of times of offsets, which allows the generating PN code section to be turned off, during a period of non-reception, in an intermittent reception system. In the first mode, it is calculated x1 mod G (x), based on the number of times of displacement, however, when the value of i is very large, x3"mod G (x) is not calculated in real time. In this modality, the period of non-reception is established to an integral number of times of the minimum period of time T, for example, 21 * T (i <0) is assumed, then the masking values for the period 2 * T they are previously calculated, to register in a masking table and the states of the PN code generating section are calculated sequentially, using a plurality of masking values. According to the process described above, the final projected state of the PN code generating section is obtained. In the explanation described above, the code generating section PN 100 is composed of a feedback register with feedback, that is, the hardware (hardware) for calculating the state of the PN 100 code generation section. It is also preferable to achieve the same processing functions as those of the generating section of PN codes and peripheral circuits, with a processing such as a CPU or DSP in software (software). As described above, when installing a PN code generating apparatus in the first embodiment or in the second embodiment of the present invention, in an apparatus in a mobile station, in a mobile radio communication system, it is possible to reduce the power consumption of the device. apparatus in the mobile station, in an intermittent reception. Thus, it is preferable to install a PN code generating apparatus of the present invention in a base station apparatus, in a mobile radio communication system. In addition, in the case of a portable information terminal for radio communication in a CDMA system, it is possible to reduce the electrical energy consumed, by including a generator of PN codes. It is also preferable to incorporate a PN code generating apparatus of the present invention, into an LSI, or a circuit (or printed card). In the above embodiments of the present invention, an explanation of a PN code generator with 42 stages is given, however the present invention is applicable to a PN code generating apparatus with any number of stages. It is noted that, with regard to this date, the best method known by the requested, to carry out the present invention, is that which is clear from the present, discovering the invention. Having described the invention as above, the content of the following is claimed as property.

Claims (1)

1. CLAIMS A PN code generating apparatus, characterized in that it comprises: a shift register for generating a PN code, the shift register having a plurality of delay elements connected by series, wherein the number of the delay elements is corresponding to the number of orders in a primitive polynomial G (x), a plurality of exclusive OR circuits, each prepared in an input stage of each of the elements of delay and means of multiplication, to multiply a feedback code, which leaves the predetermined delay element by means of the coefficient of each order of the primitive polynomial G (x), in such a way that each multiplied value is entered into an exclusive OR circuit, corresponding to each order respectively; masking means to generate a masking polynomial S (x), based on the following formula; S (x) = x modG (x) where i is the number of times of displacement in which the record of displacement, must be displaced during a certain period, from the first moment, until a second moment; Y means of state establishment, to enter a code maintained in the shift register at the first moment, within the exclusive OR circuit, corresponding to the order of S (x) that has coefficients 1, from the highest order to the lowest order of the code, in such a way that a state of the shift register is established, in the second moment, after entering the lowest order. The PN code generating apparatus according to claim 1, characterized in that the masking means calculates the number of times of displacement "i", in which the shift register must be moved during a period, since the termination of a operation to generate PN codes, until the operation is restarted. The PN code generating apparatus according to claim 1, characterized in that the masking means maintain in advance the number of times of displacements "i" ", in which the shift register must be displaced during a period, from the termination of a PN code generation operation, to the restart of the operation. The PN code generating apparatus according to claim 1, characterized in that the masking means further comprise: storage means, for storing a plurality of masking polynomials S (x), previously calculated and corresponding to a plurality of times numbers of displacement "i", or information concerning each order of the masking polynomial S (x); Y selection means for selecting a masking polynomial S (x), or the information concerning each order of the masking polynomial of the storage means. The PN code generating apparatus according to claim 1, characterized in that the masking means further comprise: storage means, for storing a plurality of masking polynomials S (x), previously calculated and corresponding to a plurality of times of displacement times "i", or information concerning each order of the masking polynomial S (x); Y selection means for selecting a masking polynomial S (x), or the information concerning each order of the masking polynomial of the storage means, based on a value of n, as long as nxT (n is an integral number and T is a unit of time) is a period of time from the first moment, until the second moment. The PN code generator apparatus according to claim 5, characterized in that the selection means select S (x), corresponding am x, or information concerning the order of S (x), by sequentially increasing the value of i, as long as n = prL. The PN code generating apparatus according to claim 1, characterized in that the state setting means comprise: parallel / serial conversion means for serially outputting a plurality of bit data, saved in parallel, while saving in parallel the memory bit data of each delay element, indicative of a state of the shift register at the first moment; and a plurality of prepared AND circuits, corresponding to each exclusive OR circuit, for calculating a logical product of bit data, graduated from the parallel / serial conversion means and each order of S (x), to input the logical product to a corresponding exclusive OR circuit. An apparatus of a mobile station in radio communication with a base station in a CDMA system, the apparatus of the mobile station characterized by a PN code generating apparatus according to claim 1. An apparatus of a base station in radio communication with an apparatus of mobile station, the base station apparatus is characterized by comprising the PN code generating apparatus according to claim 1. A method for generating a PN code, using a shift register, wherein the shift register has a plurality of delay elements connected in series, wherein the number of the delay elements corresponds to the number of orders of a primitive polynomial G (x), a plurality of exclusive OR circuits, each prepared in a layer one input stage of the delay elements and multiplication means, to multiply a feedback code, which is output from the element of delay by means of the coefficient of each order of the primitive polynomial G (x), in such a way that each multiplied value is entered into an exclusive OR circuit, corresponding to each order respectively, the method is characterized because it comprises the steps of: generate a masking polynomial S (x), based on the following formula; S (x) = xxmodG (x) where i is the number of times of displacement in which the displacement register must be moved during a certain period, from a first moment, to a second moment; and changing the state of the shift register at the first moment to a registration state at a second time, by entering a code of the shift register at the first moment, within the exclusive OR circuit, corresponding to the order of S (x ). A computer program product for operating a computer, the computer program is characterized in that it comprises: a computer reading medium; a first program instruction means for instructing a computer processor, to move a plurality of bit data, forming a code for a next step according to a shift clock and to multiply the coefficient of each of the orders of a primitive polynomial G (x), by means of bit data, in which the order corresponds to the specific orders in the code, in such a way that a new code is generated; and a second program instruction means, to instruct a computer processor to obtain the state of a code, after the specific number of times has been shifted, from a state of the code in a certain time, based on x1. mod G (x), where i is the number of times of displacement and where each of the program's instruction means is recorded in the medium in an executable form and can be loaded into the memory of a computer to be executed by the processor associated.