MXPA97008135A - Galois field multiplier for reed-solo decoder - Google Patents

Abstract

A Reed-Solomon decoder includes an optimized Galois field multiplication circuit. The circuit has a plurality of multipliers, connected in a linear chain, wherein the first multiplying of the first multiplier is the quantity A, and the second multiplying is a constant. The circuit operates on a linear combination of alpha values that are added to alpha j, each multiplier in the chain generates a successive alpha value. A plurality of selectors activate the outputs of the multipliers according to the magnitude alpha j. An addition circuit, preferably realized as a logical network of XOR gates, is connected to the selectors to add the activated outputs of the multipliers to form the end product

Description

DB GALOIS FIELD MULTIPLIER FOR DES ^ IFTgAnn nía DESCRIPTION OF THE INVENTION This invention relates to forward error correction code decoders. More particularly, this invention relates to a structure for performing multiplicative operations on the arithmetic of the Galois field during the decoding of Reed-Solomon. Reed-Solomon coding is now well established as an error correction code to protect transmitted data and the transmission of modem of image and audio data by digital techniques. Various implementations have been described. For example, our application EP 96301869.2 describes the implementation of a very large-scale integrated circuit ("VLSI") of a Reed-Solomon decoder in a digital receiver. A modern application of Reed-Solomon coding has been proposed in the European Telecommunications Standard DRAF pr ETS 300 744 (May 1996), which uses coded orthogonal frequency division ultiplexing ("COFDM"). The Standard specifies the frame selection structure, channel coding and modulation REF: 25805 for digital terrestrial television. It has been developed to adapt digital terrestrial television within the existing spectrum allocation for analogue transmissions, and still provide adequate protection against high levels of co-channel interference and adjacent channel interference. The indicated Standard requires an external Reed-Solomon code concatenated with an internal perforated convolutional code. This is combined with a bit and symbol interleaving in a MPEG-2 transport stream fashion. An RS code is specified (204, 188, t = 8) as the outer code, which has a polynomial code generator: g (x) = (x +? °) (x *? x) (x +? 2) ... (x + ?? s): D in which ? = 02HEX. The polynomial field generator is: p (x) = x8 + x4 + x3 + x2 + 1 (2) The implementation of physical elements of Galois field multipliers in known Reed-Solomon decoders require considerable resources, and has not been easily adaptable to new technologies and new applications in a production environment.

It is a main objective of the present invention to provide an improved error detection correction and correction circuits that perform extensive multiplicative operations on digital data. It is another object of the invention to provide an improved Galois field multiplier in a VLSI implementation by reducing physical equipment resources. It is a further object of the invention to provide a Reed-Solomon decoder that can be easily adapted to various VLSI circuits for use in telecommunications and similar purposes. These and other objects of the present invention are achieved by a decoder for an electromagnetic signal that is coded according to a BCH code, in which the code is specified by a polynomial g (x), and has a primitive element a. The decoder operates in the terms xxaj, which are formed by the Galois Field Multiplication. The decoder includes circuits for multiplication of Galois fields to form a product A * B, where "*" is the field multiplication operator of Galois. Each field multiplication circuit of Galois has a plurality of multipliers, in which a first multiplicand is the quantity A, and the second multiplicand is a constant ok.

The multipliers are interconnected, preferably in a linear chain, with the output of a multiplier connected to a first input of another multiplier. A plurality of selectors allow the outputs of the multipliers. The selectors have selection lines that are established according to a representation of a magnitude B. An addition circuit, preferably realized as a logical network of XOR gates, it is connected to the selectors to add the permitted or enabled outputs of the multipliers to form the final product A * B. The addition is made by the addition circuit that is carried out without a conveyor. According to one aspect of the invention, the multipliers comprise constant coefficient multipliers. According to another aspect of the invention, there is a plurality of lines connected to the selection lines, which are established according to the representation of the quantity B. The invention provides a decoder for an electromagnetic signal encoded according to a code BCH which is specified by a generator polynomial g (x) and has a primitive element a, the decoder is of a type which operates in a term x ^, where the improvement has a Galois field multiplier which has a plurality of constant coefficient multipliers. An input of each constant coefficient multiplier is a first multiplying A, and a second multiplying of the constant coefficient multiplier is a constant a, where an output of the constant coefficient multiplier is connected to the input of a successive constant coefficient multiplier. A plurality of bit lines carry a binary representation of a quantity B which controls a plurality of switches, each switch being connected to the output of one of the respective constant coefficient multipliers. An addition circuit is connected to perform the addition module 2 to the switches to sum the outputs of the constant coefficient multipliers, whereby the summed outputs come out as a binary representation of the quantity A * B. The invention provides a method to perform the decoding of Reed-Solomon, where a is a primitive element in a Reed-Solomon code. It is carried out by providing a VLSI circuit which has a Reed-Solomon decoder in it, and performing the Galois field multiplication in the circuit to obtain a product x ^ by the steps of: (1) identifying a combination linear of values an in which they have a sum equal to a3, where for each value of an, n is a whole number; (2) generate each value an by multiplying ap by an "k, where k is an integer number, (3) multiply each value an by xlf to get products onxlf and (4) add the products an xx to provide the value x ^ 3 For a better understanding of these and other objects of the present invention, reference is made to the detailed description of the invention, by way of example, which can be read in conjunction with the following drawings, in which: Figure 1 is a functional block diagram of the Reed-Solomon decoder, Figure 2 is another block diagram of the Reed-Solomon decoder which operates according to the diagram of Figure 1, Figure 3 is a schematic illustrating the generation of inputs in a Galois field, Fig. 4 is a block diagram of a FIFO that is incorporated in the decoder illustrated in Fig. 1, Fig. 5 shows a tapered feedback deviation record for generating syndromes in the decoding illustrated in Figure 1; Figure 6 shows a flow diagram of the Berlekamp algorithm used in the Reed-Solomon decoder in the prior art; Figure 7 shows a block diagram of an apparatus used to perform the Berlekamp algorithm used in the decoder illustrated in Figure 1; Figure 8 shows a block diagram of the array for carrying out a Chien search in the decoder illustrated in Figure 1; Figure 9 is a schematic of a preferred embodiment of a Galois field multiplier according to the invention; Figure 10 is a schematic of another preferred embodiment of a Galois field multiplier according to the invention; and Figure 11 is a more detailed scheme of an addition circuit which is found in the embodiments of Figures 9 and 10. The approach to decoding Reed-Solomon is initially explained with reference to Figures 1 and 2. invention can be carried out with this decoder, and with other Reed-Solomon decoders which use the Galois field arithmetic. A packet of 208 octets R (x) 2 is introduced into a FIFO 4, which is performed as a RAM capable of storing 448 octets. The FIFO 4 simply acts as a delay while the decoding progresses. Only 188 octets of information are required to be stored. The 20 parity octets can be discarded as they are not used after the calculation of the syndromes S (x) 6. The decoder 8 receives data interleaved in the packet R (x) 2. A flag 10 VALID indicates that the current octet of the packet R (x) 2 is a valid octet in the current package. The EOP 12 packet flag is raised at the same time that the 10 Valid flag indicates that the last packet octet has been received. An OS 14 error flag is raised in the case where a packet is prematurely terminated by the deinterleaver. This results in a restart operation for the entire decoder. The CORRECT 16 common link contains the corrected data. The RS-VALID 18 line indicates that the data is in the CORRECT 16 common link. This line is only activated when the data octets are on the line. The RS_EOP 20 line is a line that indicates that the packet end has been detected. The line PACK_ERR 22 is activated when the line RS_E0P 20 is activated. It indicates that the decoder 8 has been unable to correct a previously released package. The RS_OS 24 line means that a significant error condition has occurred within the packet. This signal propagates through the system, and indicates that the current block will not provide more valid data. With reference to figure 4, the first 188 bytes of the packet R (x) 2 appear in the line WD 26 of the FIFO 4, and are written in one direction of the RAM 28 in accordance with the state of the counter 30. Thus similarly, a delayed version of the R (x) 2 packet on the RD 32 line is read from the addresses selected according to the state of the counter 34. The syndromes are calculated in block 36 of syndrome calculation (figure 1) according to with the following equation. n - i (3) Sj '? I r? Xij la i > (? = 0 where S3 is the syndrome jés? mo; n is the number of octets in a packet; m0 is an arbitrary integer (which is equal to zero); rxL is the ites octet in a packet; and ccx is the? th in a field of Galois. Referring now to Figures 1-7, the syndrome is generated by a bank of three units 38, 40, 41 operating in parallel (Figure 5). The Galois field inputs a1 are produced by a tapered feedback deflection recorder 42 (FIG. 3), which comprises a plurality of tilting circuits 44 having adder circuits 46, the positions of which are determined by the polynomial generator given above . Although the syndromes 24 are determined for convenience, in reality only S0-S19 is used for the rest of the decoder 8. The Berlekamp algorithm executed in the block 48 (figure 1) is a known method used to derive the location polynomial,? (x) 50, and the evaluator polynomial, Q (x) 52. Its flow chart is shown in Figure 6. The following notation is used: Rl is the deviation recorder that contains the syndrome octets produced by the previous syndrome block; R2 contains a polynomial locator,? (X), with TO, . R3 contains the polynomial D; R4 contains the evaluator polynomial, Q (x), with Q10 = 0; R5 is the temporary storage for polynomial A; dn is delta; I is the order of the polynomial in Rl; and n is a counter.

In STOP 54, I represents the number of errors found by the algorithm, and the record 56 is maintained (figure 7). In block 58, it is necessary to repetitively exchange the contents of registers R2 60 with register R3 62 for subsequent iterations of the algorithm. The value dn is calculated according to the formula The procedure performed in the apparatus shown in Fig. 7 differs from the algorithm in Fig. 6. Instead of exchanging the contents of the recorder R2 60 with the recorder R3 62, and exchanging the contents of the recorder R4 64 with the recorder R5 66, uses a biostable switch to remember which record contains the respective polynomial. This approach is economical, because temporary storage is not required. The control block 68 is a 5-bit state machine, wherein the decoding from each state determines (a) the next state; (b) activates each of the diversion registers 60-66 and 70; (c) the multiplier selects for multipliers 72, 74, 76, 78 to select entry to registers 60-66 and register 70, which correspond to R1-R5 in block 58; (d) control the time during which each state is active; (e) recalculate variables n and 1 as necessary; (f) and keep an indication which registers contain? (x) and O (x). Chien search block 80 (figure 1) exhaustively evaluates each possible position to determine if it is a root of? (X). The evaluation in a position is carried out according to the equation (5)? («-1) - S?, A -i k k '0 Although only 208 positions have been received, verification is performed for all 255 possible positions, starting with x = o2S4; for example A (-254) = A (a1) =? 1a (al0) ^ + ^ A9 (a9) ^ ...% ^ A3 (a2) ^ Al (a1) ^ 1 (6) * + * 1 ( 7) * 1 (8) etc. Chien search block 80 (figure 1) is shown in greater detail in figure 8. The terms of ? (x) are calculated using two parallel units. The upper unit 82, which has a pair of offset registers 84, 86 fed in a multiplier 88, which is related to the coefficients a1 - a5, will be discussed. The other units 90, 92 and 94 operate identically. The two upper units 82, 90 in Figure 8 are used to calculate? (X). In each iteration the products undergo a rotation operation, so that they are recycled through the diversion recorders. Therefore, in the sixth iteration, the next position is evaluated, and the cell that is furthest to the right of the deviation recorder contains the product? 5 (a5). The product? 5 (a10) is required immediately, and now it is only necessary to multiply the product of the first iteration by a5. Counter 96 is incremented each time? (X) = 0, in order to count the number of error positions found. There are two checks performed to determine if the received packet contains more than the maximum of 10 erroneous bytes. First, the value in the counter 96 is compared to the value in the register 56 (FIG. 7). A difference between these two values indicates that a packet has more than 10 errors. Second, an error in bytes 254-208 found in Chien's search could invalidate the block. These are not received octets, but only used to simplify the Chien search block 80.

The equation used to calculate the error magnitude is given by (9) E (x) O (a ') aJ This result is only added to the octet received if the evaluation of? (X) in that position is equal to zero. The evaluation of O (x) and? ' (x) is carried out similarly for? (x), using the two lower units 92, 94. Unit 94 produces? ' (x), and the reciprocal is obtained with a search table in a ROM (not shown). Those skilled in the art will appreciate that in Galois field arithmetic (a * b) - (aa * ab) - aa + b (10) The actual value of a * b is determined by the field generator polynomial, for example, by the field generator polynomial provided in equation 2. Also, according to the distributive rule, if a = b + c (11) then d »a = d» b + d »c (12) The function of the multiplier can be understood with reference to the following equations: a (x) = a7x7 + a6x5 + a5xs + a4x4 + a3x3 + a2x2 + a ^ 1 + a0 (13) b (x) = b7x7 + b6x6 + bsx5 + b4x * + b3x3 + b2x2 + bxxx + b0 (14) so a (x) * (b) x = c (x) (15) where "*" indicates the multiplication of Galois field. C0 = a0b0 (16) c'x = a0b2 + a1bl + a2b0 (18) c'13 - a6b7 + a7bs (19) C14 = a7b7 (20) With p (x) as in equation (2) c0 = c'0 + c'8 + c'12 + C13 + C14 (21) Cj. = c + c'9 + c'13 + c * 14 (22) c2 + c'2 + c'ß + c'10 + C12 + c'13 (23) etc. A direct implementation of the previous multiplication has been carried out with a general multiplier in physical elements. In some cases, the general multiplier takes the inputs of an associated alpha generator. However, a general multiplier requires a considerable area in an integrated circuit. Because one of the multiples is known, a substantial space saving can be obtained by substituting the general multiplier for a plurality of coefficient and constant multipliers. In multiplicative operations such as those involved in the generation of an S3 syndrome (equation 3), multiplication in successive cycles to develop exemplary terms rx ^ 3, rXiCC4, rx ^ 5 can be done by the structure 98 of the multiplier shown in figure 9. In the discussion that follows, r is simply a constant, not necessarily related to the first octet in a data packet. In this example, the generation of only 3 terms is shown for presentation purposes, it being understood that many more terms can be calculated in practice. The entry to structure 98 of the multiplier is the first multiplying rxt 100, which is multiplied by a multiplier 102 of constant coefficient by the alpha coefficient a3 104. The product rXj_o3 appears in node 106, which becomes the entry term for a multiplier 108 of successive constant coefficient. In the generation, the product rx ^ 4 in the node 110, the multiplier 108 of constant coefficient takes advantage of the relation an = a1 • or "-1 (24) The products are multiplexed in a multiplexer 112 and are typically added by an adder 114 to another value for further processing. Those skilled in the art will appreciate that the constant coefficient multiplier 108 can be implemented with up to three OR-exclusive gates ("XOR"). The inventors have discovered that by taking advantage of the distributive law of multiplication expressed in equation (12) and the fact that an alpha value can be expressed as the linear combination of other alpha values, a Galois field multiplier can be implemented. economic, structured more convenient and more practical. Several representative alpha values are shown as binary numbers in Table 1.

It will be noted that the alpha values can be added by the addition module 2 without generating a bearer bit. For example oß = cr + a3 + a2 + a ° (25) Forming the product a8 * rxi; where "*" represents the multiplication operator of the Galois field arithmetic, which can be done by entering a second multiplying a8, using the distributive law of multiplication. rx ^ a8 = rxLa4 + rx ^ 3 + rxLa2 + rxxa0 (26) Figure 10 illustrates a preferred embodiment of a Galois field multiplier, which is generally referenced with the number 116. An array of 8 constant coefficient multipliers 118 is placed in the same manner as that shown in Figure 9. 8-bit data path is demonstrated; however, the circuit can be constructed with other common link widths. It will be noted that in the special case where n = 0, or °, the input to the first multiplier 120 of constant coefficient is unity. In such an application, the constant coefficient multiplier 120 can be eliminated. The totality of the other multipliers in the array of constant coefficient multipliers 118 multiply by a3, with j = 1 in the example of figure 9. The products formed by the constant coefficient multipliers arrangement 118 are carried out in common links 122 to the first entries of a row of 8 selectors 124. The second inputs of the selectors 124 are the respective bit lines 126 of the second multiplying B which appears in a common link 128. The selectors 124 can be realized as a plurality of AND (Y) gates, wherein the bit lines of each common link 122 are activated in common according to a respective bit line 126. In the present example, bits 0, 2, 3 and 4 of the common link 128 will be set, and the outputs of the selectors 124 in the common links 130 can be represented as the sequence. { 0, 0, 0, A [4], A [3] A [2], 0, A [0]} . The elements of this sequence are summed in an addition block 132, and the sum appears in a common link 134 output. As no load is generated, the additional ones of each of the 8 elements is simply carried out in the addition module 2 in a logical network 136 arranged as gate trees 138 XOR. Figure 11 illustrates one of the 8 identical networks that are used in the add-on block 132, where the logic is applied to the least significant bit of each of the common links 130. Other known add-on circuits are also suitable in block 132 addictor Initial implementations of physical elements of this modality have resulted in a 20% reduction in the gate count, as compared to linear implementations of multiplication according to equations (13) - (20). Although the preceding modality has been discussed with respect to the decoding of Reed-Solomon, it is equally applicable to other codes (N, K), and to the codes "Bose, Ray-Chaudhuri, Hocquenghem" ("BCH") in general, and other devices in which Galois field multiplication is performed. The Galois field multiplier 116 can be effectively used in the Chien search block 80 (Fig. 8) as the general Galois field multiplier 140 and through the decoder 8 (Fig. 2). In the preferred embodiment, the decoder 8 and the Galois field multiplier 116 are implemented in a VLSI circuit.

F, example: In this example, a standard physical element description language conforming to the IEEE 1364-1995 standard is used to describe the implementation of physical elements. First a conventional general Galois field multiplier is developed, according to the following description: GFULL module (X, Y, GFULL); input [7: 0] X; input [7: 0] Y; output [7: 0] GFULL; reg [7: 0] GFULL reg [7: 0] AOB, AlB, A2B, A3B, A4B, A5B, A6B, A7B; reg [14: 0] C; whole i; always @ (X or Y or GFULL) start for (i = 0; i <8; i = i + l) start AlB [i] = X [l] & & Y [i] A2B [Í] = X [2] SSc Y [i] A3B [Í] = X [3] ScSc Y [i] A4B [i] = X [4] S & Y [i] A5B [i] = X [5] & Y [i] A7B [i] = X [7] & amp; Y [i] end C [0] = A0B [0]; C [l] = A0B [1] AAA1B [0]; C [2] = A0B [2] AAA1B [1] AAA2B [0]; C [3] = A0B [3] A1B [2] AA2B [1] AA3B [0]; C [4] = A0B [4] AAA1B [3] AAA2B [2] AAA3B [1] AAA4B [0]; C [5] = AOB [5] A A1B [4] A A2B [3] AAA3B [2] AAA4B [1] A A5B [0]; C [6] = A0B [6] AAA1B [5] A A2B [4] AAA3B [3] AAA4B [2] AAA5B [1] AAA6B [0]; C [7] = A0B [7] AAA1B [6] AAA2B [5] AAA3B [4] AAA4B [3] AAA5B [2] AAA6B [1] AAA7B [0]; C [8] = AlB [7]? A2B [6] A A3B [5] AAA4B [4] AA5B [3] A A6B [2] AAA7B [1] C [9] = A2B [7] AAA3B [6] AAA4B [5] AAA5B [4] AA6B [3 ] AAA7B [2] C [10] = A3B [7] A A4B [6] A A5B [5] A? A6B [4] AAA7B [3] C [ll] = A4B [7] A A5B [6] AAA6B [ 5] AAA7B [4] C [12] = A5B [7] AAA6B [6] AA7B [5] C [13] = A6B [7] AAA7B [6 [C [14] = A7B [7] GFULL [0] = C [0] AAC [8] AAC [12] AAC [13] AC [14]; GFULL [1] = C [1] AAC [9] AAC [13] AAC [14]; GFULL [2] «C [2] AAC [8] AC [10] A C [12] AAC [13]; GFULL [3] = C [3] A C [8] A C [9] AAC [11] AAC [12]; GFULL [4] = C [4] A C [8] AAC [9] AAC [10] AAC [14]; GFULL [5] = C [5] AAC [9] AAC [10] AAC [11]; GFULL [6] = C [6] AAC [10] AC [11] AC [12]; GFULL [7] = C [7] AAC [11] A C [12] AAC [13]; End of module After the Galois field multiplier 116 (figure 10) is described as follows: GFULL module (X, Y, GFULL); input [7: 0] X; input [7: 0] Y; output [7: 0] GFULL; reg [7: 0] GFULL reg [7: 0] A0, A1, A2, A3, A4, A5, A6, A7; whole i; always @ (X or Y or GFULL) start AO = X; Al =. { A0 [6], A0 [5], A0 [4], A0 [3] A0 [7], A0 [2] AA0 [7], AO [1] AA0 [7] AO [0], A0 [7] A2 =. { Al [6], A1 [5], A1 [4], A1 [3] A1 [7], A1 [2] AA1 [7], Al [1] AA1 [7] Al [0], A1 [7] A3 =. { A2 [6], A2 [5], A2 (4), A2 [3] AA2 [7], A2 [2] AA2 [7J, A2 [1] AA2 [7] A2 [0], A2 [7] A4 = { A3 [6], A3 [5], A3 [4], A3 [3] AA3 [7], A3 [2] AA3 [7], A3 [1] AA3 [7] A3 [0], A3 [7] A5 = { A4 [6], A4 [5], A4 [4], A4 [3] AA4 [7], A4 [2] AA4 [7], A4 [1] AA4 [7] A4 [0], A4 [7] A6 = {A5 [6], A5 [5], A5 [4], A5 [3] AA5 [7], A5 [2] AA5 [7], A5 [1 ] AA5 [7] A5 [0], A5 [7] A7 = { A6 [61, A6 [5], A6 [4], A6 [3] AA6 [7], A6 [2] A6 [7] , A6 [1] AA6 [7] A6 [0], A6 [7] for (i = 0; i <8; i = i + l) start A0 [i] «A0 [i] & & Y [0] Al [i] = Al [i] SS Y [l] A2 [i] = A2 [i] ScSc Y [2] A3 [i] = A3 [i] ScSc Y [3] A4 [i] = A4 [i] ScSc Y [4] A5 [i] - A5 [i] ScSc Y [5] A6 [i] = A6 [i] & amp; Y [6] A7 [i] = A7 [i] ScSc Y [7] end GFULL = AO? Al? A2? A3? A4? TO 5 ? A6? A7, end of the module The above modules are processed by a synthesis program, Compass ASICSyn (trademark) which produces the following area reports for the conventional general Galois field multiplier and the Galois field multiplier 116, respectively: #################################################################################################### ####### # AREA REPORT # ################################# ################## # cell "GFULL1" # Name Nums Equivalent of Equal Total- Width per Cell Width Insts gate per Cell Wings Total Cell Gate an02d0 13 1. .5 19.5 8.0 104.0 aoi22dl 25 2. .0 50.0 10.0 250.0 invOdO 42 .5 21.0 4.0 168.0 nd02d0 51 1, .0 51.0 6.0 306.0 oai22dl 15 2, .0 30.0 10.0 150.0 xn02dl 4 3, .5 14.0 16.0 64.0 xr02dl 75 3, .5 262.5 14.0 1050.0 total: 225 448.0 2092.0 Initial: (508.5! (3226.0) Total Bolts: 737 Total Net: 241 Average Bolts per Net: 3.1; Maximum bolts per net: 9 (excluding net of energy and ground) #################################################################################################### ####### # AREA REPORT # ################################# ################## # cell "GFULL2" # Name Nums Equivalent of Equal Total- Width per Cell Width Insts gate per Cell Wings Total Cell Gate an02d0 28 1.5 42.0 8.0 224.0 aoi22dl 2 2.0 4.0 10.0 20.0 invOdO 21 0.5 10.5 4.0 84.0 mx02d0 10 3.0 30.0 12.0 120.0 nd02d0 30 1.0 30.0 6.0 180.0 oai221dl 6 2.5 15.0 12.0 72.0 oai22dl 3 2.0 6.0 10.0 30.0 xr02dl 67 3.5 234.5 14.0 938.0 totals: 167 372.0 1668.0 Initial: (431.5) (2796.0) Total bolts: 542 Net total: 183 Bolts average per net: 3.0; Maximum bolts per net: 13 (excluding net of energy and land) Although this invention has been explained with reference to the structure described herein, it is not confined to the details set forth and this application is considered to cover any modification and change that may be found within the scope of the following claims. It is noted that in relation to this date, the best method known to the applicant to carry out the aforementioned invention, e3 which is clear from the present description of the invention. Having described the invention as above, property is claimed as contained in the following:

Claims (11)

1 • A decoder for an electromagnetic signal that is coded according to a BCH code, in which the code is specified by a generator polynomial g (x) and has a primitive element a, the decoder is of a type which operates in a term x ^ 3, characterized in that: a circuit for forming a product A * B, where "*" is a field multiplication operator of Galois, comprising: a plurality of multipliers, a first input of the multiplier defines a first multiplying A, and a second entry of the multiplier defines a second multiplicand, the second multiplicand is a constant ak, where one output of the multiplier is connected to a first input of another multiplier; a plurality of selectors to activate the outputs of the multipliers, the selectors have selected lines that are set according to a representation of a quantity B; and an addition circuit connected to the selectors to add or add the activated outputs of the multipliers.

2. The decoder according to claim 1, characterized in that the multipliers comprise constant coefficient multipliers.

3. The decoder according to claim 1, characterized in that it additionally comprises a plurality of lines connected to the selected lines, wherein the lines are established according to the representation of the quantity B.

4. The decoder according to claim 1, characterized in that the addition circuit performs the addition without transportation.

5. The decoder according to claim 4, characterized in that the addition circuit comprises a logical network of XOR gates.

6. In an integrated circuit, a decoder for an electromagnetic signal that is coded according to a BCH code, where the code is specified by a generator polynomial g (x) and has a primitive element a, the decoder is of a type which operates in a term x.a3 ~, characterized in that the decoder improvement comprises: a circuit for forming a product A * B, where "*" is a Galois field multiplication operator, comprising: a plurality of multipliers of constant coefficient, a first entry of a first multiplier that defines a first multiplicand A, and a second entry of the multiplier that defines a second multiplicand, the second multiplicand is a constant ak; wherein an output of the first multiplier is connected to a first input of a second multiplier; and a selector circuit for activating the selected outputs of the multipliers according to a representation of a magnitude B.

7. A decoder for an electromagnetic signal coded according to a BCH code that is specified by a generator polynomial g (x) and has a primitive element or, the decoder is of a type which operates in a term xxaj, and which has a multiplier of Galois field, characterized in that: a plurality of constant coefficient multipliers, an input of the constant coefficient multiplier of the plurality define a first multiplying A, and a second multiplying of the constant coefficient multiplier is a constant ok, wherein an output of the constant coefficient multiplier is connected to the input of a successive constant coefficient multiplier; a plurality of bit lines having states that form a binary representation of a quantity B; a plurality of switches, each switch is connected to the output of one of the respective constant coefficient multipliers, and has a control line connected to one of the respective bit lines; and an addition circuit to perform the addition of module 2 connected to the switches to add the outputs of the constant coefficient multipliers, so that the summed outputs come out as a binary representation of a quantity A * B, where "*" is a Galois field operator.

8. The decoder according to claim 7, characterized in that the addition circuit comprises a logical network.

9. A decoder for an electromagnetic signal encoded according to a Reed-Solomon code that is specified by a generating polynomial g (x) and having a primitive element a, the decoder is of a type which operates in a taj term, in which the improvement comprises: a circuit to form a product A * B, where "*" is a Galois field multiplication operator, the circuit comprises: a linear chain of constant coefficient multipliers, an input of a first multiplier in the chain that defines a first multiplying A and a second multiplying the multiplier that is a constant ak, where an output of the multiplier is connected to the input of the successive multiplier; a plurality of AND gates (Y) having first inputs connected to the outputs of the multipliers to allow their output, the gates each have second inputs connected to a common link, where a binary representation of a quantity B appears in the common link; and an addition circuit connected to the selectors to add the activated outputs of the multipliers.

10. The decoder according to claim 9, characterized in that the addition circuit comprises a logical network of XOR gates arranged as a tree to perform the addition of the module 2.

11. A method for performing the Reed-Solomon decoding, where a is a primitive element in a Reed-Solomon code, the method is characterized in that it comprises the steps of: providing a VLSI circuit having a Reed-Solomon decoder in the same; and perform a Galois field multiplication in the circuit to obtain a product x ^ 3 by the steps of: identifying a linear combination of values ctn that has a sum equal to aj, where for each value an, n is a whole number; generate each value on by multiplying an by an "k, where k is a whole number, multiply each value an by x1 # - to provide the products a ', and add the products to'. A Reed-Solomon decoder includes an optimized Galois field multiplication circuit. The circuit has a plurality of multipliers, connected in a linear chain, wherein the first multiplying of the first multiplier is the magnitude A, and the second multiplying is a constant. The circuit operates on a linear combination of alpha values that add to o3, each multiplier in the chain generates a successive alpha value. A plurality of selectors activate the outputs of the multipliers according to the magnitude o3. An addition circuit, preferably realized as a logical network of XOR gates, is connected to the selectors to add the activated outputs of the multipliers to form the final product.