MXPA97007599A - Efficient digital filter and method using recombination of coefficient - Google Patents

Abstract

The present invention relates to a digital filter for filtering an input signal, and for producing a filtered signal, characterized by the digital filter by: an input to receive the input signal, a storage circuit of coefficients for storing a plurality of coefficients previously combined, a selection circuit coupled with the input and with the coefficient storage circuit, to select the appropriate previously combined coefficients from the plurality of previously combined coefficients in response to the input signal, and a coupled combination circuit with the selection circuit, to combine the appropriate previously combined coefficients, in order to produce the filtered signal

Description

EFFICIENT DIGITAL FILTER AND OUE METHOD USES THE PRECOMBINATION OF COEFFICIENTS FIELD OF THE INVENTION The present invention relates generally to communication devices. The present invention relates more particularly to a digital filter for use in communication devices.

Background of the Invention In today's communication devices, digital filters are favored for their ease of implementation, efficient operation, and good operation. These filters can be built using shelf components, such as digital signal processors (PSD), custom designed using digital logic elements or implemented using table lookup techniques based on the. Read only memory (MSL). Many functions can be implemented using these digital filters. A particular application for digital filters is in a communication device such as a radiotelephone headset. The filters are used to filter the signals received and transmitted on the radiotelephone. A radiotelephone headset is used in communication systems, such as cell phone systems for radio communication with one or more fixed base stations. The communication is in accordance with a previously defined protocol, for example, time division multiple access (AMDT) or code division multiple access (CDMA). A radiotelephone headset operating in accordance with the EIA / TIA IS-95 standard for code division multiple access communication must perform a baseband filtering operation on the chip sequences transmitted in phase and quadrature phase , in order to limit both the dispersion of the transmission and the interference between symbols. This standard requires that the sampled impulse response measured match the specified filter coefficients (48 non-zero values), with a square mean error of no more than 3 percent. In addition, the response of the measured frequency must fall within the limits specified by the standard. These limits include having at least 40 dB of stopband attenuation, and no more than 3 dB of passband undulation. The filter uses a clock speed of 4.9152 MHz; the coefficients are separated by a quarter of a chip time (0.20345 microseconds). The memory length resulting from the filter is twelve chip intervals.

Previous attempts to develop a digital filter that provides this operation have given solutions that are unacceptable both in the gate count and in the power consumption. The gate count refers to the number of logic gates used in the filter, and is a measure of the area of silicon required by a design in an integrated circuit. Similar designs that use fewer gates are less expensive to produce. The energy consumption is also proportional to the number of gates. In a consumer product, such as a radiotelephone headset, the minimization of the cost of the product and the consumption of energy are of paramount importance, and therefore, the maximization of the time to talk and the waiting time energized by battery. In one implementation, which uses a digital signal processor for general purposes, which has an accumulation function by multiplication, the implementation of this filter requires a total of 24 accumulation functions per multiplication in each cycle of the clock. At the filter clock speed of 4.9152 MHz, this digital signal processor requires 118 MIPS (millions of instructions per second). This level of operation can not be obtained at a reasonable cost and at power dissipation levels in a radiotelephone headset.

Another implementation uses a query table approach based on MSL (read-only memory) that maps the 12-chip input sequence into an 8-bit output word. As, according to the IS-95 standard, each input chip can have three values (+1, -1, and 0), the size of the resulting read-only memory is 312 (531.441) words per 8 bits. The size of this read-only memory is greater than 300,000 gate equivalents, and is too large to be implemented in a radiotelephone headset. In accordance with the above, there is a need for a digital filter that can implement the described filter with a gate count and reduced energy dissipation levels, BRIEF DESCRIPTION OF THE DRAWINGS The characteristics of the present invention, which are believed to be novel, are stipulated with particularity in the appended claims. The invention, together with other objects and advantages thereof, can be better understood by reference to the following description, taken in conjunction with the accompanying drawings, in the different figures of which like reference numerals identify identical elements, and in the which: Figure 1 is an operational block diagram of a communication device. Figure 2 is an operational block diagram of a digital finite impulse response filter for use in the communication device of Figure 1. Figure 3 is an example input chip sequence to the finite impulse digital response filter. of Figure 2. Figure 4 is an operational block diagram of a selector for use in the digital finite impulse response filter of Figure 2. Figure 5 is a table illustrating the multiplexing logic of the filter for a modality of the finite impulse response digital filter of Figure 2. Figure 6 illustrates the impulse response of two filter modes in accordance with the present invention.

Detailed Description of a Preferred Modality now referring to Figure 1, it shows an operational block diagram of a communication device 100. The communication device 100 may be operable in any suitable system, but will be described particularly by operating in association with a code division multiple access communication system according to the interim EIA / TIA IS-95 standard. In this system, the communication device 100 is implemented as a mobile station or radiotelephone handset configured for radio frequency (RF) communication, with one or more remote base stations. The communication is in accordance with the IS-95 protocol. The communication device 100 includes an antenna 102, a receiving section 104, a transmitting section 106, a controller 107, and a user interface 122. The receiving section 104 includes a radiofrequency front end 109, an analog to digital converter 108. , a rake receiver 110, and a decoder 120. Rake receiver 110 includes a first demodulator branch 112, a second demodulator branch 114, a third demodulator branch 116, and a combiner 118. Antenna 102 sends and receives radio frequency signals to and from a base station (not shown). The radiofrequency signals received on the antenna 102 are filtered, and the frequency is translated (converted downward) into intermediate frequency signals (Fl) by the radio frequency front end 109. The intermediate frequency signals are converted from analog signals to digital data, and are processed differently in the analog-to-digital converter 108. In the rake receiver 110, the output symbols are combined from each scrambler rake receiver finger or finger, by the combiner 118, which forms a received signal. The combiner 118 provides the received signal to the decoder 120. The decoder 120 can be a Viterbi decoder or another type of convolutional decoder, or any other suitable decoder. The decoder 120 retrieves the data transmitted on the radio frequency signals, and outputs the data to the controller 107. The controller 107 formats the data in speech or recognizable information to be used by the user interface 122. The controller 107 is electrically coupled to other elements of the communication device 100, to receive the control information and to provide control signals. In Figure 1 the control connections are not shown, so as not to unduly complicate the figure of the drawing. Controller 107 typically includes a microprocessor and memory. The user interface 122 communicates the information or voice received to a user. Typically, the user interface 122 includes a visual display, a keyboard, a speaker, and a microphone. Upon transmission of the radio frequency signals from the communication device 100 to a remote base station, the user interface 122 transmits input data from the user to the controller 107.

The controller 107 formats the transmission information obtained from the user interface 122, and transports it to the transmitting section 106, to become modulated radiofrequency signals. The transmitter section 106 includes an encoder 126, a digital finite impulse response (RIF) filter 128, a digital-to-analog converter or CDA 130, a first analog filter 132, a second analog filter 134, a quadrature modulator 136, and a clock generator 138. The encoder 126 encodes the transmission information received from the controller, including the separation of the information into phase data and data in the quadrature phase, and provides the transmission information to the digital filter 128. In the preferred embodiment, the transmission information it comprises an input chip sequence corresponding to the phase data, and an input chip sequence corresponding to the quadrature phase data. Input chip sequences consist of chips or samples that take values designated as +1 and -1. The encoder 126 provides a enable signal to an enable input 127 of the digital filter 128, to control the operation of the digital filter 128. In the preferred embodiment, the enable signal comprises a sequence of enable signal values.

Each enable signal value corresponds to a chip in phase and a chip in the quadrature phase. When the enabling signal has a first value, such as the logical 1, the digital filter 128 operates to filter the input chip sequences. When the enabling signal has a second value, such as the logical 0, the digital filter 128 assigns values of 0 to the input chips in phase and quadrature phase before filtering these sequences. The digital filter 128 filters the transmission information received from the encoder as an input signal in a manner that will be described later, and provides the result to the digital-to-analog converter 130 as a filtered signal. The clock generator 138 provides clock signals to a filter clock input 129 of the digital filter 128. These clock signals include a chip clock, which is preferably 1.2288 MHz, and a filter clock for the digital filter 128. In the preferred embodiment, the filter clock is provided in a multiple of the chip clock, such as four times or eight times the clock speed of the chip. The controller 107 provides a sample number or index 1 to an input 131 of the digital filter 128. The input chip sequences are preferably oversampled by a factor of N, preferably N being 4. That is, each input chip is sampled N times. The sample number 1 indicates which of the N samples is being provided to the digital filter 128. The digital-to-analog converter 130 converts the filtered signal from the digital form to the analog form, and provides the filtered analog signals to the first analog filter 132 and to the second analog filter 134. The digital-to-analog converter 130 provides analog information in phase to the first analog filter 132, and analog information in quadrature phase to the second analog filter 134. After the analog filtering, the signals in phase and in Quadrature phase are provided to the quadrature modulator for its modulation, power amplification, and upward conversion, up to appropriate radio frequency signal frequencies. The radiofrequency signals are transported to the antenna 102, and transmitted. Figure 2 is a block diagram of a digital filter 200 for use with the communication device 100 of Figure 1. The digital filter 200 is configured to filter an input signal, and to produce a filtered signal. The digital filter 200 includes an input 202 for receiving the input signal, an enabling input 203 for receiving an enabling signal, and a clock input 205. The digital filter 200 further includes a first shift register 204, a second shift recorder 206, a third shift register 208, a multiplexer 210, a selection circuit 212, a combination circuit 214 , and a coefficient storage circuit 216. In the preferred embodiment, the input signal received at input 202 is an input stream that includes samples or input chips in phase and samples or input chips in quadrature phase. Described mathematically, the digital filter 200 implements the following equation: 47 (1) and (i) = S b (i-k) xh (k) A = 0 Here, b (i) is the sequence of the input chip, h (k) is the coefficient of the filter ka, and y (i) is the filter's output sequence. The k filter coefficients are 48 previously defined non-zero values, with a quarter-chip derivation as a separation, as specified in the IS-95 specification. Figure 3 illustrates an example input chip sequence 300 to the digital filter 200. The sequence of the input chip, b (i), can take values of +1, -i, or 0. The chip speed is 1.2288 MHz. Because the derivation separation is one quarter of the chip duration, the input chip sequence is oversampled by a factor of N = 4, meaning that each of the input chips includes an input sample of value and N - 1 = 3 samples of zero value. The value input samples may have one of a previously determined number of values, specifically one of the values +1, -1, or 0. Accordingly, in Figure 3, the input sequence of the chip 300 includes a first sample of value 302 followed by three samples of zero value, sample 304, sample 306, and sample 308. The sequence of input chip 300 further includes a second sample of value 310, followed by three samples of zero value, the sample 312, sample 314, and sample 316. The filter, as implemented in communication device 100 (Figure 1), receives two input chip sequences, one for in-phase data, and one for in-phase data. Quadrature A brute force implementation of the filter defined by equation (1) above would require 48 multipliers plus an adder of 48 inputs for both the in-phase (I) channel and the quadrature-phase (Q) channel. In accordance with the present invention, in order to reduce the complexity of the filter, and to reduce the cost of its components and the dissipation of energy, design simplifications have been made to implement this filter.

First, much of the filter hardware is time-shared between channels I and Q. This reduces the number of logic gates required to implement the filter and the associated power dissipation, at the expense of making the filter work at twice the speed of the filter. clock, or eight times the speed of the chip, or 9.8304 MHz. Second, because the input chip sequence b (i) can only take values of +1, -1, and 0, the filter coefficients are summed, denied, and added, or set to zero. As a result, the logic gates - used to form multipliers of the filter according to the present invention are eliminated. Third, because the input sequence is oversampled by a factor of 4, there will only be twelve terms other than zero at each sampling time. For each new input chip, b¿, four output samples will be generated. u (2) Y (l) - = S bx x h (l + 4i) i = o where 1 = 0, 1, 2, 3, ... represents the sample number during the chip interval. As a result, an adder of twelve entries is required instead of an adder of 48 entries.

Finally, in accordance with the present invention, pairs of input coefficients are precombinated. The pre-combination allows a summer adder to be replaced by a multiplexer and some simple combination logic. As an example, consider the output due to the first two entries that are not zero. The output, y0, will be a constant value, which is either the sum, the difference, the negated sum, or the negated difference of the two filter coefficients: (3) y0 = bjtx (?) + Bth U) = h (0) + h (4) if b0, b¡ = +1, +1 = h (0) + h (4) if b0, bj = +1, -1 = [h (0) + h (4) ] if b0, J j = -i, -i = [h (0) + h (4)] if b0, JbJ = -1, +1 Similar simplifications are made for the other outputs. The precooked coefficients can be stored in a memory, or they can be established as wired connections up to appropriate logical levels, also reducing the number of gates required. As a result of these simplifications, the adder of twelve inputs for the sum of the y (l) samples, can be replaced by a six-input adder plus some multiplexing logic. The pre-combining of the coefficients in this way leads to a reduction in the number of gates and in the area of silicon required, because a multiplexer with constant inputs requires fewer gates than a full adder. Referring again to Figure 2, the first shift register 204 is coupled to the input 202 to receive the input samples in phase, forming a phase-in-sample storage circuit for storing the input samples in phase. In a similar manner, the second shift register 206 is coupled to the input to receive the input samples in the quadrature phase, forming a quadrature phase sample storage circuit for storing the input samples in the quadrature phase. The third shift register 208 forms an enabling signal storage circuit coupled with the enable input 203 for storing the enable signal samples. Each shift register is clocked by a clock signal received at the clock input 205. Accordingly, there is a time correspondence between the enable signal samples stored in the third shift register 208, and the input samples in phase stored in the first shift register 204, and the quadrature phase input samples stored in the second shift register 206. The multiplexer 210 selectively couples one of the first shift register 204 and the second shift register 206, with the selection circuit 212, in response to a control signal received at an I / Q input 211. The control signal is provided by the controller 107 (Figure 1), or by any other suitable source. In this manner, the selection circuit 212 and the combination circuit 214 are shared by the in-phase sample storage circuit and the quadrature phase sample storage circuit to produce the filtered signal. This sharing of the hardware between the phase and quadrature channels substantially reduces the number of gates and silicon area, and the associated current drain required to implement the digital filter 200. The coefficient storage circuit 216 stores a plurality of previously combined coefficients. In the preferred embodiment, the previously combined coefficients are formed from filter coefficients defined by the code division multiple access specification IS-95. However, the previously combined coefficients could be adequately formed from other previously defined coefficients according to the requirements of another filter design. The previously combined coefficients are formed from the filter coefficients in a manner that will be described later. In the preferred embodiment, the coefficient storage circuit 216 is configured to store the filter coefficients, as well as the previously combined coefficients. The coefficient storage circuit 216 can store previously combined coefficients (and filter coefficients) in any suitable manner, including in a memory device. In the preferred embodiment, the coefficient storage circuit comprises wired connections with appropriate logic levels that provide the previously combined stored coefficients. The wiring coefficients minimize the number of gates and the area of silicon required by the coefficient storage circuit 216. The selection circuit 212 is coupled to the input 202 through the first shift register 204 and the second shift register 206 and multiplexer 210 and the coefficient storage circuit 216he. , to select the appropriate pre-combined coefficients from the plurality of previously combined coefficients in response to the input signal received at the input 202. The input samples are stored as input samples in phase in the first shift register 204, and as input samples in the quadrature phase in the second shift recorder 206.

Selection circuit 212 comprises a plurality of selectors, such as selector 220, selector 222, and selector 224. Each selector has a selector input coupled with input 202 to receive one or more input samples. The input values for the selectors are selected from input values stored by the multiplexer 210. The structure and operation of the selectors will be described later in conjunction with FIG. 4. In the preferred embodiment, the selection circuit 212 It comprises six selectors. As indicated in Figure 2, each selector receives as input, two b ± values and two enable values. The selection circuit 212 selects a previously determined group or number of coefficients previously determined from the coefficient storage circuit 216. Refer to Figure 4, a selector 400 includes a multiplexer 402, an operation block 404, and a logic block 406. Log block 406 receives as one input, the one or more input samples' provided to selector 400 from the input. In the preferred embodiment, each input sample b2i and b2i + 1 is a two-bit input consisting of the input sample value b2i and the associated enable signal value. The logic block 406 receives the input samples b2i and b2 ± + 1, and the sample number 1. In response to the input samples, the logic block 406 provides a control signal to the multiplexer 402. The logic block 406 may consist of any appropriate circuitry necessary to perform this function. The inputs of the multiplexer 402 are coupled to the coefficient storage circuit 216 (Figure 2). In response to the control signal, the multiplexer 402 selects a previously combined coefficient at one of the inputs, as indicated in Figure 4, and provides the previously selected combined coefficient selected at the output 408 of the multiplexer 402. In the preferred embodiment, the coefficient storage circuit 216 stores the filter coefficients, as well as the previously combined coefficients. In this embodiment, the multiplexer 402 selects a filter coefficient or a previously combined coefficient, and provides it to the output 408. As noted above, in the preferred embodiment, the previously combined coefficients and the filter coefficients are wired at the inputs of the multiplexer 402. Also, as noted, the preferred input signal is oversampled by a factor of N, such that each of the input samples includes an input sample with value, and Nl value input samples zero. N is preferably 4, but can be any other value. In Figure 4, 1 is provided to the logic block 406, and serves as an index or sample number for the oversampled values. Accordingly, the selection circuit 212, which includes the selector 400, selects the appropriate pre-combined coefficients in response to the stored input samples received from the first shift register 204 and from the second shift register 206 (FIG. 2), and the sample number 1. The number of samples 1 is a time reference indicating the effect of the Nl samples with zero value. The operation block 404 is coupled with the multiplexer 402 to negate, zero, or selectively pass without modifying the previously combined coefficient (or the filter coefficient) provided at the output 408 of the multiplexer, in response to a control signal received at the input 410 of the operation block 404. In the preferred embodiment, each input sample b2i and 2 ± +? is a two-bit input consisting of a bit for the input sample value b ± or b21 + 1, and a bit for the associated enable signal value. The operation block 404 provides a value of zero when the enable signal received in the enable input 203 has a previously determined disablement value. For each sample input or chip set to clock er. the first change register 204 and in the second change register 206, a corresponding enabling sample is set to clock in the third shift register 208. Accordingly, the selector provides one of the filter coefficient, the negative of the filter coefficient, the previously combined coefficients, the negative of the previously combined coefficient, and a value of zero to the combination circuit. This embodiment and the enabling signal are used when the input signal comprises input samples of trinary value having values of +1, -1, and 0. In an alternative embodiment, the input signal comprises input samples of binary value. that have values of +1 and -1. The operation block provides one of the previously combined coefficient and a negative of the coefficient previously combined to the combination circuit 214 (Figure 2). Since the previously combined coefficient is a sum, or a difference, or a negated or different sum or two of filter coefficients, the provision of the operation block 404 reduces the number of values that must be stored in the coefficient storage circuit 216. Only the sums and differences should be stored, and the denial is made through the operation block 404. The operation block 404 may consist of any circuitry necessary to implement the function described. Figure 5 illustrates the multiplexing logic of the filter for two modes of the digital filter 200. In the preferred embodiment, described herein as "Option • A1", the digital filter 200 provides a full transmission filter functionality, which includes a operation in appropriate burst mode. During the upward ramp and the downward ramp of the transmitter section 106 (Figure 1), a cord of zero values will be inserted into the filter. As a result, it is necessary to extract the individual filter coefficients. Therefore, in this preferred embodiment, the individual filter coefficients are stored in the coefficient storage circuit 216. The selector provides one of a filter coefficient, a negative of the filter coefficient, a previously combined coefficient, a negative of a previously combined coefficient, and a value of zero, in response to the input samples. Because the operation according to the IS-95 code division multiple access standard is of a burst nature, this is preferred. mode for a filter used in a communication device, such as communication device 100, operated in accordance with the code division multiple access standard. The filter multiplexing logic required for this mode is illustrated in Figure 5 in the column of the table labeled "Option 'A'".

In an alternative embodiment, an additional size reduction of the digital filter according to the present is provided at the expense of operation in degraded burst mode. The filter multiplexing logic required for this mode is illustrated in Figure 5, in the column of the table labeled "Option 'B'". As shown there, this mode uses only the sum, the difference, and the constants of zero. The individual filter coefficients are not used, and therefore, no storage is required in the coefficient storage circuit 216. Unless this mode has the same continuous state operation as Option 'A' of the preferred mode, the response Transient of Option B is slightly degraded in relation to the transient response of Option A. Figure 6 illustrates the impulse response of two filter modes in accordance with the present invention. A first impulse response 602 illustrates the ideal impulse response, which is the impulse response provided by the preferred mode of the filter in accordance with Option A. A second impulse response 604 illustrates a degraded impulse response provided by the alternative mode of the filter according to Option B. The second impulse response 04 exhibits a slight transient error. This transient error is minimized by the multiplexing logic illustrated in the Table of Figure 5, and is reduced by the analog filters 132, 134, which follow. to the digital filter 128 according to the present invention, in a communication device 100 (Figure 1). This alternative mode is appropriate for systems that use digital filters that are not time-division multiplexed, or that can tolerate up-ramp and slightly-down-ramp operation. Referring again to Figure 2, the combination of each multiplexer 402 from each selector 400, forms a plurality of multiplexers, each multiplexer selecting a 'previously combined coefficient of a previously determined number, such as six previously combined coefficients, each multiplexer having one input coupled to a wired connection of the coefficient storage circuit 216, and an input of the selector coupled to the sample storage circuit in phase and to the sample storage circuit in quadrature phase, to receive the stored phase input samples and the input samples stored in the quadrature phase. The combination of each operation block 404 from each selector 400 forms a plurality of operation blocks, each operation block being coupled with a respective multiplexer to selectively negate the previously combined coefficient in response to the stored phase input samples and the samples of entry in stored quadrature phase. The combining circuit 214 is coupled to the selection circuit 212 to combine the appropriate pre-combined coefficients, in order to produce a filtered signal at the output of the filter 230. The combining circuit 214 is preferably a six-input adder, but it can be any suitable circuit to combine a group of previously combined coefficients to produce the filtered signal. As can be seen from the above, the present invention provides a digital filter and a method suitable for use in communication applications in burst mode. The digital filter provides a substantially reduced gate count and substantially reduced energy dissipation levels over previous implementations. These benefits are provided by the pre-combination of filter coefficients to eliminate digital adder circuits, and to use smaller size adders in conjunction with simple multiplexers. These benefits are also provided by sharing the filter hardware between in-phase and quadrature channels. By capitalizing on the aspects of the input data samples, the complexity of the filter circuit is also reduced. For example, because the sequence of the input chip is limited to values of +1, -1, and 0, the multipliers are eliminated in favor of simpler multiplexers and adders. Also, because the input sequence is oversampled by a factor of 4, the design hardware is removed to include only non-zero filter terms. Although particular embodiments of the present invention have been shown and described, modifications can be made. Accordingly, in the appended claims, it is intended to cover all changes and modifications that fall within the true spirit and scope of the invention.

Claims (11)

NOVELTY OF THE INVENTION Having described the above invention, it is considered as a novelty, and therefore, the content of the following is claimed as property: CLAIMS

1. A digital filter (200) for filtering an input signal, and for producing a filtered signal, characterized by the digital filter by: an input (202) for receiving the input signal (300); a coefficient storage circuit (216) for storing a plurality of previously combined coefficients; a selection circuit (212) coupled with the input and with the coefficient storage circuit, to select the appropriate previously combined coefficients from the plurality of previously combined coefficients in response to the input signal; and a combination circuit (214) coupled with the selection circuit, to combine the appropriate previously combined coefficients, in order to produce the filtered signal.

2. A digital filter according to claim 1, characterized in that the input signal (300) includes input samples that have a value of a previously determined number of values, and further characterized in that the selection circuit comprises a plurality of selectors (220, 222, 224), each selector having a selector input coupled with the input to receive one or more input samples, each selector including a multiplexer (402) that selects a previously combined coefficient in response to the one or more entry samples.

3. A digital filter according to claim 2, further characterized in that each selector further comprises an operation block (404) coupled with the multiplexer, to selectively negate the previously combined coefficient, in response to the one or more samples of input, providing the operation block one of the previously combined coefficient and a negative of the previously combined coefficient to the combination circuit.

4. A digital filter according to claim 3, characterized in that the input signal (300) is oversampled by a factor of N, each of the input samples including an input sample with value (302), and Nl samples with zero value (304, 306, 308), further characterized by the digital filter by an input sample storage circuit (204, 206); for storing only the input samples with value as stored input samples, and wherein the selection circuit selects the appropriate previously combined coefficients in response to the stored input samples, and a time reference indicating an effect of the Nl samples with zero value.

5. A digital filter according to claim 3, further characterized by an enabling input (203) for receiving an enabling signal, each selector further including an enabling input for receiving the enabling signal, providing the block of operation one of the previously combined coefficient, the negative of the previously combined coefficient, and a value of zero to the combination circuit.

6. A digital filter according to claim 5, further characterized in that the coefficient storage circuit is configured to store the filter coefficients, forming the plurality of previously combined coefficients from the filter coefficients, providing each selector one of a filter coefficient, a negative of the filter coefficient, a previously combined coefficient, a negative of a previously combined coefficient, and a value of zero, in response to the one or more input samples.

7. A digital filter according to claim 1, characterized in that the input signal includes phase input samples and input samples in quadrature phase, further characterized by the digital filter by: a sample storage circuit in phase (204) coupled between the input and the selection circuit, for storing the input samples in phase; and a quadrature phase sample storage circuit (206) coupled between the input and the selection circuit, for storing the input samples in the quadrature phase.

8. A digital filter according to claim 7, further characterized in that the selection circuit and the combination circuit are shared by the in-phase sample storage circuit and the quadrature phase sample storage circuit, to produce the filtered signal.

9. A digital filter according to claim 1, further characterized in that the coefficient storage circuit comprises wired connections with appropriate logic levels.

10. A method for filtering a digital signal according to the filter coefficients previously determined, characterized by: storing the previously combined coefficients, forming the previously combined coefficients from the previously determined filter coefficients; receive an input stream corresponding to the digital signal; select a group of previously combined coefficients in response to the inflow; and combining the group of coefficients previously combined to produce a filtered signal. A method for filtering a digital signal according to claim 10, characterized in that the step of receiving an input stream includes receiving a sequence of input data samples, further characterized by the method of: storing the coefficients of the filter previously determined; receiving a sequence of input enable samples, each of the input enable samples corresponding to a sample of input data; wherein the step of selecting comprises the steps of: when an input enablement sample has a value corresponding to a first value, providing one of a previously combined coefficient and a previously defined filter coefficient; and when the input enable sample corresponds to a second value, provide a value of zero.