MXPA97005024A - A circuit formulator of deviac signal impulses - Google Patents

Abstract

The present invention relates to an arrangement for reproducing a composite or synchronous suppression signal (COMPOSY) includes a vertical deflection circuit (11) having a supply booster stage (11f). A first pulse voltage (VBST) on a vertical scale is derived from an output signal from the boost stage. The vertical scale, the first pulse voltage is coupled to a base terminal of a follower emitter (A1) by means of a voltage divider to produce an input edge of an output pulse voltage (VBLANK) of the follower emitter. The first vertical scale pulse voltage is also coupled via an R-C network (C1, R6) to a regenerative switch (Q2, Q3). The regenerative switch is coupled to the base terminal of the follower emitter to produce an output edge (TEVBLANK) of the output pulse voltage of the follower emitter. The trailing edge occurs after a predetermined interval (TW) has elapsed from the input edge. The output pulse voltage of the follower emitter is combined with a horizontal scale pulse voltage (HBLANK) to produce the composite synchronous signal. The composite synchronous signal is coupled to a field detector (120b) of an image-in-picture processor (120) of a vid display.

Description

A DEFLECTION SIGNAL PULSE FORMOR CIRCUIT The invention relates to a pulse generator of a video device. U.S. Patent No. 5, 025,496, entitled "ODD FIELD DETECTOR FOR VIDEO SIGNALS" in the name of Canfield, discloses a field detector of an image-in-picture (PIP) display processor of a video display. The field detector is used to distinguish between even and odd image fields in the video signal. The need to distinguish between even and odd fields arises due to the need to ensure adequate entanglement and to avoid instability of the small image of the PIP arrangement. In the Canfield patent, the field detector is sensitive to a suppression or synchronization signal that includes the horizontal and vertical synchronization signals on the same signal line. In the detector, the time difference between the trailing edge of the vertical synchronous signal portion of the synchronous signal composed of a given field and the input edge of the immediately following horizontal synchronous signal portion is measured. The time difference measured in a field is compared to the time difference measured in the next field. From the comparison, the type of field, even or odd, is determined. Advantageously, by measuring the relatively short time interval from the trailing edge of the vertical synchronous signal portion to the input portion of the immediately following horizontal synchronous signal portion allows to use a time difference counter having some steps . The Canfield patent provision can be included in an integrated circuit (IC). The composite synchronous signal is generated outside the IC by the combination in an individual terminal or connector of the vertical and horizontal synchronous signals separated from the IC using a diode-OR arrangement. Advantageously, by using the signal terminal to provide the composite synchronous signal to the IC, the IC connector count is kept smaller than if the horizontal and vertical synchronous signals were provided by separate terminals or connectors. Typically, a vertical counting circuit that is included in a deviation IC can be used to generate a control signal on the vertical scale. The control signal may be coupled in the deflection IC to a sawtooth generator. The sawtooth signal can be developed in a bypass IC output terminal. The sawtooth signal is applied to a vertical deflection amplifier to generate a vertical deflection current. In order to reduce the connector count of the I C deviation, the control signal may not be provided in a dedicated or terminal connector of the deviation IC. It may be desirable to generate the composite synchronous signal for the display processor PI P such that the vertical synchronous signal portion of the composite synchronous signal is synchronized to the control signal of the vertical counting circuit. An example of a booster supply circuit of a vertical amplifier is described in U.S. Patent No. 5,229,692, in the name of Wilber, entitled "VERTI CA L DEF LECTION ARRANG EM E NT WITH S-CORR ECTION. In a disadvantageous manner, the output edge of the pulse voltage that can be generated by the reinforcing supply circuit can be subjected to instability or field-to-voltage variations. This is because the pulse of the reinforcing supply circuit can be affected by a horizontal scale signal that can be coupled in a parasitic way to the vertical amplifier, in contrast, the input edge of the impulse voltage of the amplifier circuit. The reinforcing supply occurs in the vicinity of the vertical retrace and generally does not suffer from excessive variations or instability. It may be desirable to derive from the The reinforcing supply means associated with the deflection amplifier is the synchronous vertical signal portion of the composite synchronous signal that can be combined with a horizontal synchronous signal to produce a composite synchronous signal. Said composite synchronous signal can be used, for example, in the aforementioned Canfield arrangement.

According to an inventive feature, the impulse voltage of the reinforcing supply circuit is reformed so that the output edge synchronization is determined primarily by the synchronization of the input edge and, therefore, becomes substantially less subject. to the variation introduced in the vertical deflection amplifier. A signal generator of a video display apparatus, which modalizes an aspect of the invention, includes a vertical deflection amplifier to generate a deflection current in a deflection winding. A first impulse voltage is generated during a vertical retrace interval. A pulse-forming circuit is responsive to the first pulse voltage to produce a second pulse voltage having a predetermined output edge in accordance with the first pulse voltage and occurring before an output edge of the first pulse voltage. The second pulse voltage is coupled to a utilization circuit to provide the timing information from the output edge of the second pulse voltage. Figure 1, which includes Figures 1a and 1b, illustrates a pulseformer, which modalizes an inventive feature. A vertical deflection circuit 1 1 of Figure 1 a may be similar to that described in the Wilber Patent. A synchronization signal SYNC is coupled to a conventional vertical synchronization generator 10 which may include a conventional vertical counting circuit, not shown. The SYNC signal is produced by a video detector, not shown, of a television receiver that processes a baseband television signal, which conforms, for example, to the NTSC standard. The generator 10 generates a pulse control signal VR ESET on the vertical scale which is coupled to a conventional vertical sawtooth generator 100. The generator 100 generates a pair of sawtooth signals VRAMP2 and VRAMP 1. The signals VRAMP1 and VRAMP2 are complementary signals that change in the opposite directions during each vertical trace interval. The circuit 1 1 is a coupled offset circuit C. D. controlled by the signals VRAMP1 and VRAMP2. In the case 1 1, a deflection winding Ly provides a vertical deflection in a CRT cathode ray tube (22). The winding Ly is coupled in series with a deviation current sampling resistor R80. The winding Ly and the resistor R80 form a series arrangement which is coupled between an output terminal 1 1 b of an amplifier 1 1 a and a junction terminal 1 1 c of a power supply decoupling capacitor Cb. The amplifier 1 1 a and the reinforcing stage 1 1 f are included in an integrated circuit (IC) TDA 8172. A voltage C. D. applied to the terminal 1 1 c, is equal to approximately one half of a supply voltage V +, which is referenced later. A connection terminal 1 1 d, coupled between the winding Ly and the resistor R80, is coupled by means of a feedback resistor R60 to an inverting input terminal of the amplifier 1 1 a. The terminal 1 1 c of the resistor R80 is coupled by means of the resistor R30 to a non-inverting input terminal of the amplifier 11a. In this way, a negative feedback voltage that develops through the resistor R80 is applied to the input terminals of the amplifier 11a. The complementary sawtooth signals VRAMP1 and VRAMP2 are coupled by means of the resistors R40 and R50, respectively, to the inverter and noninverting input terminals, respectively, of the amplifier 11a to control the bypass current i, shown in the Figure 1a. Due to the rapid change in a retrace portion RETRACE in each of the signals VRAMP1 and VRAMP2, the deflection amplifier 11a stops operating in a linear feedback mode and a voltage VB is applied in the supply terminal connector 6 to the winding of deviation Ly. A retrace voltage V11b is produced. A switch 11f1 of the boost stage 11f causes a capacitor 11g to be coupled in series with a boost capacitor 11e. The capacitor 11e is charged by means of an X diode and a switch 11 f 2 from the supply voltage V + + 26V, during the vertical trace. A voltage supply, developed through the filter capacitor 11g, is added with a voltage developed through the boost capacitor 11e to form the boost voltage VB, during the vertical retrace. The voltage VB is decoupled from the supply voltage V + + 26V by means of the diode X, when the reinforcing voltage VB is formed. The booster voltage VB, approximately equal to twice the value of the voltage V +, is applied to the transistor output stage, not shown, of the amplifier 1 1 a. A vertical scale impulse voltage VBST having an input edge LEVBST is developed at connector 3 of the TDA IC 8172 and at a capacitor terminal 1 1 e which is remote from the X diode. The input edge LEVBST coincides with the start of the vertical retrace. An output edge TEVBST of the pulse voltage VBST occurs in a closeness of a time when the amplifier 1 1 resumes the operation in linear mode. The trailing edge TEVBST can be subjected to field-to-field variations due to, for example, parasitic coupling of a horizontal scale signal produced in a horizontal output stage 130 of Figure 1 b. The field-to-field variations of the TEVBST output edge may be more significant than those of the LEVBST input edge. A pulse forming circuit 1 10, which modalizes an inventive feature, includes a voltage divider formed by a resistor R 1 and a resistor R2, coupled in series. The pulse voltage is coupled by means of a junction terminal 1 10a, between the resistors R 1 and R 2 and a resistor R 3 to a base of a follower emitting transistor Q 1. The transistor Q 1 has a emitter resistor R5 and a collector resistor R4. Consequently, an input edge of a transmitter voltage VBLANK that develops in the emitter of the transistor Q 1 substantially coincides with the input edge LEVBST.

The pulse voltage VBST is also coupled by a capacitor C1 to the base electrode of a parallel transistor or level-set transistor Q2. The transistor Q2 has a transmitter coupled to a junction terminal 110a and a collector coupled to a coupled load resistor R7. A resistor R6 is coupled to the base of transistor Q2. Resistor R6 and capacitor C1 form a differentiator, network R-C. A transistor Q3 has a collector electrode coupled to the base electrode of transistor Q2 and a base electrode coupled to the collector of transistor Q2. The transistors Q2 and Q3 form a regenerative switch when the transistor Q2 is turned on. During a TW interval, which immediately follows the input edge LEVBST, the base voltage of transistor Q2 is more positive than its emitter voltage. Therefore, transistor Q2 is off and has no effect on the pulse voltage VBLANK. Therefore, during the TW interval, the voltage VBLANK is determined by the magnitude of the voltage VBST and by the voltage divider that is formed by the resistors R1 and R2. During the TW interval, the capacitor C1 is charged by means of the resistor R6 and the base voltage of the transistor Q2 gradually decreases, in accordance with the time constant of the resistor R6 and the capacitor C1. At the end of the TW interval, when capacitor C1 is charged to a sufficient level to develop a sufficiently low base voltage of transistor Q2, transistor Q2 is turned off. Consequently, transistor Q3 is turned on and the base voltage of transistor Q2 decreases and becomes close to OV. Therefore, the transistor emitter voltage Q2 in the terminal 1 10a becomes sufficiently small to produce a transistor saturation voltage in the emitter of the transistor Q 1. Advantageously, the pulse voltage VBLAN K has an edge of TEVBLANK output, which follows the interval TW, which has a length that is independent on the synchronization of the output edge TEVBST. Therefore, advantageously, any field-to-field variation of the trailing edge TEVBST that can be caused by parasitic coupling from a horizontal deflection circuit 130 that will not affect the trailing edge TEVBLAN K. Generators 10 and 100 they can be included in an integrated circuit (IC) 100a that generates the signals VRAMP 1 and VRAMP2. The signals VRAMP 1 and VRAMP2 are derived from the VRESET signal. Therefore, the need to use the VRESET signal directly to generate the VBLANK signal is avoided. Therefore, the dedicated connector that outputs the VRESET signal from IC 100a is not required. Therefore, advantageously, the number of connectors required for the IC 100a is less than if the VRESET signal had to be issued separately from the IC 100a. A diode D1 couples the pulse voltage VBLANK to an input terminal 120a of a PIP display processor 120. A pulse voltage HBLANK, on the horizontal scale, produced in the horizontal deflection circuit 130, in a conventional manner, not shown , is coupled by means of a diode D2 to the input terminal 120a of the display processor PI P 120. Therefore, the diodes D 1 and D2 form a diode-OR configuration to produce a COMPOSY composite synchronous signal. The COM POSY composite synchronous signal is coupled in the processor 120 to a field detector 120b which may be similar to that described in, for example, the Canfield patent.

Claims (16)

1. A pulse former of a video display apparatus, comprising: a parallel transistor switch (Q2); a source of a first pulse voltage (VBST) at a frequency related to a vertical deflection frequency; a differentiator (C1, R6) responsive to the first pulse voltage to generate a second pulse voltage (base voltage of Q2) coupled to a control terminal (base) of the parallel transistor switch in accordance with the second pulse voltage so that an exit edge of the second impulse voltage occurs before an exit edge (TEVBST) of the first impulse voltage; characterized by a first impedance (R1) coupled to said source of the first pulse voltage and to a main current conducting terminal (EMITTER) of the parallel transistor switch to generate a third pulse voltage (VBLANK) having an output edge which is determined in accordance with the trailing edge of the second pulse voltage, the third pulse voltage being coupled to a video display processor (120) to provide the timing information of the first pulse voltage from the trailing edge of the third impulse voltage.

2. A pulse former according to claim 1, characterized in that an input edge of the third pulse voltage (VBLANK) is determined in accordance with an input edge (LEVBST) of the first pulse voltage (VBST).

3. A pulse former according to claim 1, characterized in that the differentiator (C1, R6) comprises a network R-C.

A pulse former in accordance with claim 1, characterized in that each of the first signal path (E1) between the source of the first pulse voltage (VBST) and the control terminal of the transistor switch (Q2) and a second signal path (R1) between the source of the first pulse voltage and the main current conducting terminal of the transistor switch includes exclusively passive elements.

5. A pulse former according to claim 1, further characterized by a second transistor switch (Q3) coupled to the first transistor switch (Q2) to form a regenerative switch therebetween.

6. A pulse former in accordance with claim 1, further characterized by a second impedance (R2) coupled to the first impedance (R1) to form a voltage divider to develop a portion of the first pulse voltage (VBST) in the main current conducting terminal (EMITTER) having a peak amplitude that is different from a peak amplitude of the second pulse voltage (AT BASE OF Q2); and the parallel transistor switch (Q2) which is deactivated insofar as a difference between the portion of the first pulse voltage and the second pulse voltage is within a scale of values and is enabled when the difference is outside said scale. of values.

7. A pulse former according to claim 1, characterized in that the video display processor (120) comprises an image-in-image display processor.

8. A pulse former according to claim 1, further characterized by a source (130) of a fourth pulse voltage (H BLA NK) at a frequency related to a frequency of horizontal deflection, the third (VBLAN K) and Fourth impulse voltages combine to form a composite suppression signal (COMPOSY).

9. A pulse former according to claim 1, characterized in that the source of the first pulse voltage (VBST) comprises a power supply booster stage (1 1 f) of a vertical deflection amplifier (1 1). ), the first impulse voltage being generated in the reinforcing stage during a vertical retrace interval.

10. A signal generator of a video display apparatus, comprising: a vertical deflection output stage (11) to generate a bypass current (iy) in a bypass winding (Ly) and to generate a first voltage of impulse (VBST) during a delay interval; characterized by a pulse forming circuit (110) responsive to the first pulse voltage to produce a second pulse voltage (VBLANK) having an output edge determined in accordance with the first pulse voltage and occurring before an output edge (TEVBST) of the first pulse voltage, the second pulse voltage which is coupled to a utilization circuit (120) to provide the timing information from the output edge of the second pulse voltage.

11. A signal generator according to claim 10, characterized in that the output stage (11) comprises a power supply booster stage (11f) coupled to a deviation amplifier (11a) and wherein the first voltage of Impulse (VBST) is generated in the reinforcing stage.

12. A signal generator according to claim 10, characterized in that the utilization circuit (120) comprises an image-in-picture display processor.

A signal generator according to claim 10, further characterized by a source (130) of a third pulse voltage (HBLANK) at a frequency related to a horizontal deflection frequency, the third pulse voltage and the second voltage Pulse (VBLAN K) are combined to form a composite suppression signal (COMPOSY).

14. A pulse former of a video display apparatus, comprising: a power supply booster stage (1 1 f) of a vertical deflection amplifier (1 1 a) to produce a first pulse voltage (VBST) during a vertical retrace interval; and first (Q2) and second (Q3) transistors coupled to form a regenerative switch, the regenerative switch being sensitive to the first drive voltage to generate a second drive voltage (VBLAN K) having a narrower pulse width than that of the first voltage of pulse, the second pulse voltage being coupled to a utilization circuit (120) to provide the synchronization information thereof.

15. A pulse former according to claim 14, further characterized by a voltage divider (R1, R2) responsive to the first pulse voltage (VBST) and coupled to a main current conducting terminal of the first transistor (Q2). ) to develop a portion of the first impulse voltage in the main current conducting terminal; and, a differentiator (C 1, R 6) responsive to the first pulse voltage to generate a third pulse voltage at the control terminal (BASE) of the first transistor (Q 2).

16. A pulse former according to claim 15, characterized in that during a first interval (TW), when a difference between the portion of the first pulse voltage (at terminal 110a) and the third pulse voltage (at the base of Q2) is within the scale of values, the regenerative switch is off and for a second interval, when the difference is outside said scale, the regenerative switch in parallel to the portion of the first pulse voltage to decrease one pulse width of the portion of the first impulse voltage, in accordance with the third impulse voltage.