MXPA97003444A - Absorbe material - Google Patents

Abstract

The present invention provides a superabsorbent material comprising a combination of (1) a cationic superabsorbent, in which from 20% to 100% of the functional groups are in basic form, and (2) a cationic exchanger, in which 50 100% of the functional groups are in formazide. The combination is particularly effective as a superabsorbent, for solutions containing electrolytes, such as menstruation and ori

Description

APPARATUS AND METHOD FOR MAKING AMPLIFICATION OF ERROR CORRECTED ON ON RADIO FREQUENCY SYSTEM Field of the Invention This invention relates generally to amplifiers for use in radio frequency (RF) systems, and more particularly to corrected error amplifiers for use in a system of RF. Background of the Invention In radio frequency system applications (RF), such as cellular and microwave communication system applications, where multiple carrier input signals are fed to an RF power amplifier, the inherent non-linear characteristics of the amplifier at high power levels generally cause the output of the amplifier contains undesirable intermodulation (I) products. These IM products can cause undesirable interference and interference over the frequency range of the operational amplifier. In addition, IM products may exceed transmission standards for RF equipment. A conventional method of reducing IM products uses a "spectral analysis" approach and is described in U.S. Patent No. 4,879,519. The "spectral analysis" approach includes exploring the output of the amplifier using a receiver tuned to the frequency of the candidate IM products. The IM level for a candidate IM product is read by the browser, and a linearizer is adjusted to minimize the product of I. The procedure of reading the IM product level and adjusting it to minimize the IM product is repeated until each of the IM products has a low level at a predetermined acceptable level. Although this conventional method reduces the IM products, the method requires the browser to search the IM products in an interative manner and therefore has a low convergence interval due to the time required to scan and find the IM products. In addition, this method requires sophisticated spectral analysis equipment which adds significant cost to the amplifier. According to the above there is a need for a method and apparatus for amplifying multiple carrier input signals with a faster convergence time and reducing the cost while still reducing the IM products in an RF system. SUMMARY OF THE INVENTION According to one aspect of the present invention, there is provided an apparatus and method for performing the amplification of the corrected error in a radio frequency system. The apparatus is a corrected error amplifier circuit that includes a first stage of pilot modulation and a second stage of pilot modulation. The first pilot modulation stage creates a first amplified signal having an error component and a first error signal indicative of the error component. The second pilot modulation stage receives the first amplified signal and the error signal and generates a reduced error amplified signal. Preferably, the first pilot modulation stage comprises a pilot modulation circuit and an amplifier responsive to the pilot modulation circuit. The pilot modulation circuit preferably includes a phase and gain control circuit and a pilot modulator coupled to the phase and gain control circuit. In a preferred embodiment, the pilot modulator is driven by a pilot phase source and a pilot gain source. The second pilot modulation stage preferably includes an error insertion coupler, a second pilot modulator responsive to the error insertion coupler, and a main amplifier responsive to the second pilot modulator. The error insertion coupler receives the first amplified signal and the error signal, and the main amplifier generates the reduced error output signal. According to another aspect of the invention, the error correction amplifier circuit includes an amplifier, a pilot phase source, a pilot gain source, a pilot modulator coupler for the amplifier, and a first on / off switch. The on / off switch selectively couples the pilot modulator and at least one of the pilot sources. Preferably the first on / off switch is used to perform DC offset compensation. The method of performing the corrected error amplification includes a method of aligning the error correction amplifier circuit. According to a preferred embodiment the method includes the steps of providing a first amplifier having inherent distortion characteristics, providing a second amplifier having substantially similar distortion characteristics to the first amplifier, establishing a first phase and gain control circuit in response to a power level detected by a carrier detector which responds to the first amplifier, and establishes a second phase and gain control circuit in response to the output of a pilot detector that responds to the second amplifier to produce a signal of error that is out of phase of the output of the first amplifier. The invention itself, together with its proposed advantages will be better understood with reference to the following detailed description, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block circuit diagram illustrating a preferred embodiment of an error correction amplifier circuit according to the present invention. Figure 2 is a block circuit diagram illustrating a second preferred embodiment of an error correction amplifier circuit according to the present invention. Figure 3 is a block circuit diagram illustrating a third preferred embodiment of an error correction amplifier circuit. Figure 4 is a block circuit diagram illustrating a fourth preferred embodiment of an error correction amplifier circuit. DETAILED DESCRIPTION OF THE PREFERRED MODALITIES Referring to FIG. 1, a preferred embodiment of a corrected error amplifier circuit is illustrated. The error correction amplifier circuit 100 includes a first pilot modulation stage 101 and a second pilot modulation stage 103. The first pilot modulation stage 101 includes a first pilot modulator 106, a first gain and phase control circuit 108, a comparison amplifier 110, a first delay line 112, a carrier cancellation combiner 114, a carrier detector 116, a second phase and gain control circuit 118, a second delay line 120, and an amplifier error 122. The first pilot modulation stage 101 also includes a two-way splitter 104 which receives an input signal from an input node 102. The second pilot modulation stage 103 includes an error insertion coupler 136, a second pilot modulator 138, a main amplifier 152, an output sampler 156, and envelope detectors 162 and 164. The second stage of pilot modulation 103 also inc it includes a pilot gain detector 166, a phase pilot detector 168, a pilot phase source 140, and a pilot gain source 142. The second pilot modulation stage 103 preferably also includes DC compensation on / off switches 144. , 146, 148 and 150. In addition to the first and second pilot modulation stages, the amplifier circuit 100 also includes a controller 170 coupled to the first and second pilot modulation stages 101, 103. During the operation an input signal is received in the input node 102 and is fed to the two-way divider 104. The divider 104 provides a first signal fed to the first pilot modulator 106, and a second signal that is substantially identical to the first signal that is fed to the first control circuit phase and gain 108. In the first pilot modulator 106, an amplitude modulator is operated by the pilot gain source 142, and a phase modulator is operated by the phase pilot source 140. The output from the first pilot modulator 106 is fed to the comparison amplifier 110. The distortion products produced by the associated amplifier 110 are isolated by the carrier cancellation combiner 114, amplified by the error amplifier 122, and reinserted by the error insertion coupler 136 such that the signal at the output of the error insertion coupler 136 has distortion products which are preferably equal in amplitude relative to the carriers, but out of phase of the distortion products present in the output of the associated amplifier 110. This preferred configuration is designed to cancel the distortion produced by the main amplifier. 152, assuming that its distortion characteristics are substantially idé The first phase and gain control circuit 108 is controlled by the controller 170 and produces an output signal that is delayed by the first delay line 112 and then fed to the second port of the combiner. carrier cancellation 114. The associated amplifier 110 produces an amplified signal 124 which in turn is fed to the first port of the combiner 114. The combiner 114 produces a first output signal 128 in a third port and a second output signal 130 in a fourth port. The first output signal 128 has an error component which is generally caused by the IM products from the amplification within the amplifier 110. The second output signal 130 has an error component which is representative of the products of I produced by the amplifier 110 and a residual carrier signal component. The carrier detector 116 receives the second output signal 130 and detects the residual carrier signal component in the output signal 128 that has not been removed by the combiner 114. The first phase and gain control circuit 108 is set by the controller 170 in order to minimize the residual carrier signal component. The second phase and gain control circuit 118 receives the second output signal 130 and responds to the control signals from the controller 170. The second phase and gain control circuit 118, in response to control information from of the controller 170, produces a signal 132 which is indicative of the error component in the first output signal 128. The signal 132 is then amplified by means of the error amplifier 122 to produce an error signal 134. The output signal 128 is delays by means of the second delay line 120 to produce a first amplified signal 129. The first amplified signal 129 has an error component due to the distortion characteristics of the amplifier 110. The error insertion coupler 136 receives the first amplified signal 129 and the error signal 134 and produces a combined signal. In the preferred embodiment the controller 170 includes a microprocessor, such as a Motorola processor 68030, which is programmed to control the second phase and gain control circuit 118 so that after passing through the error insertion coupler 136, the error signal 134 has an amplitude two times greater than the amplitude of the error component in the first amplified signal 129. In addition the error signal 134 is out of phase, preferably 180 ° out of phase, of the error component in the first amplified signal 129. The second pilot modulator circuit 138 receives the combined signal from the error insertion coupler 136 and applies a pilot modulation signal from the phase pilot source 140 and the pilot gain source 142 to produce a signal of pilot modulated output 151. The output signal 151 from the second pilot modulator 138 is amplified by the main amplifier 152 to create an amplified output signal 154. The output amplified signal 154 is sampled by the output sampler 156 and then provided as an amplified reduced error signal 158 at the output of the corrected error amplifier circuit 100. A sampled signal from the output sampler 156 is divided into two paths by the two-way divider 160. A first path is fed to the envelope detector 162 and a second path is fed to the envelope detector 164. The first path includes the phase pilot detector 168 and the second path includes the gain pilot detector 166. The phase pilot detector 168 and the gain pilot detector 166 receive each one an input from the pilot phase and gain sources 140 and 142 respectively . The phase and gain pilot detectors 168 and 166, each provide a control signal containing detected pilot phase and gain signal information for use by the controller 170. The controller 170 responds to the detected signal information from the pilot detectors 166 and 168 to reduce the products of IM in the output signal 158 when adjusting the second phase / gain control circuit 118. An additional feature of the circuit 100 is to be provided with the on / off switches 144, 146, 148, 150 of the controller operated in all lines of pilot signal going to the pilot modulators 106 and 138. The controller 170 has the capability to "nullify" any displacement of CDs in the pilot detectors 166, 168 by sampling their outputs when the modulation inputs to the pilot modulators 106, 138 have been turned off by the appropriate on / off switch. The controller 170 then subtracts a measured signal of residual CD displacement from the outputs of the pilot detector when the pilot modulation is turned on again. Of course the same effect could also be achieved by placing the CD compensation switches 144, 146, 148, 150 in the lines between the outputs of the detector of the envelope and the inputs of the pilot detector, or providing a means for "grounding" "the outputs of the pilot detector that are connected to the outputs of the detector of the envelope. Figure 2 illustrates another preferred embodiment of an amplifier circuit 200 having a preamplifier 208. The amplifier circuit 200 has been slightly modified in comparison to the amplifier circuit 100 of Figure 1 and only the differences will be described. Between the input 102 and the two-way divider 104 of FIG. 1, a third pilot modulator 202 driven by the first and second pilot control lines 206 and 204 from the pilot phase and gain sources 140 and 142 is coupled to the preamplifier 208. The preamplifier 208 is preferably selected to have substantially similar distortion characteristics as those of the associated amplifier 110. In this way the controller 170 can compensate for distortion in the third amplifier 208 based on the output of the pilot detectors 166 and 168 as described above with respect to Figure 1. A person of ordinary skill in the art will appreciate and understand that many additional amplifiers can be added to the amplifier circuits shown in Figure 1, such as the preamplifier 208 of Figure 2. Although they can use multiple amplifiers, it is important to note that each amplifier is preferably coupled with a a pilot modulator field, such as the pilot modulator 202 in FIG. 2. In addition, in the preferred embodiment each amplifier has substantially similar distortion characteristics. When each of the amplifiers has substantially similar distortion characteristics, the controller 170 can more accurately determine the correct amplitude and phase of the error signal 134 inserted in the error coupler 136. However, even if the amplifiers have different distortion characteristics, the controller 170 can be programmed to adjust the different phase and gain control circuits connected to each of the amplifiers to compensate for these variations. Another aspect of the present invention provides a method for automatically adjusting the phase and gain controls 108 and 118 so that the amplitude and phase of the error signal 134 cancels the distortion produced by the main amplifier 152. In the method of preferred alignment the first phase and gain control 108 is set to minimize the power of the carrier present in the second output signal 130. This may be an automatic adaptive process, as indicated in Figure 1, when the controller 170 continuously updates the settings of the first phase / gain control 108 in order to minimize the power detected by the carrier detector 116. Carrier cancellation can also be just a simple one-time adjustment. The above approach may be preferred in some applications since this system tolerates small amounts of carrier power in the second output signal 130, provided that the error amplifier 122 is large enough to handle the resulting signal without the contribution of any significant distortion of one's own. Those skilled in the art will appreciate that the step of adjusting the first phase and gain control 108 is used primarily to compensate for deviations in the gain and phase offset of the compensation amplifier 110. If this problem is not too severe, it is stage can be omitted without negatively impacting the performance of the system. The phase adjuster in the second phase and gain control 118 is then adjusted to minimize the output of the phase pilot detector 168. Likewise the gain adjuster in the second phase and gain control 118 is adjusted to minimize the output of the gain pilot detector 166. The above steps can then be repeated until no further improvements are observed in the pilot cancellation. The output of the second pilot modulator 138 is then established to "simulate" the distortion produced by the main amplifier 152. The second pilot modulator 138 allows the circuit 100 to align itself so that the modulation sidebands produced by the first modulator pilot 106 appear at the output of the error insertion coupler 136 with the same amplitude relative to the carriers, but 180 ° out of phase of the modulation sidebands present at the output of the first pilot modulator 106. These modulation sidebands preferably they will "cancel" themselves at the output of the second pilot modulator 138 by the modulation sidebands produced in the second pilot modulator 138. In the preferred embodiment, the components of the pilot modulator and the amplifier are selected to approximate the following conditions theoretically ideal: 1. All pilot modulators do not produce IMD for them. mos. 2. All pilot modulators have identical modulation characteristics. 3. All pilot modulators proceed immediately to their respective amplifiers in the signal path. 4. The gain pilot signal has the same magnitude and phase in each modulator. 5. The phase pilot signal has the same magnitude and phase in each modulator. 6. Both the main amplifier and the associated amplifier have identical distortion characteristics. The foregoing theoretical considerations enhance the importance of designing the system in such a way that each pilot modulator simulates exactly the distortion characteristics of its associated amplifier. In practice, it is unlikely that both the main amplifier 152 and the associated amplifier 110 have identical distortion characteristics. This is not a problem, since the difference is reasonably small and repeatable (or at least stable against time and temperature). In this case there are slight differences in the pilot signals supplied to each pilot modulator and the pilot gain amplitudes are adjusted to compensate for differences in gain compression between the two amplifiers. For example, the gain pilot signal supplied to the second pilot modulator 138 may be increased if the main amplifier 152 has more gain compression than the associated amplifier 110. Similarly, the phase pilot amplitudes may be adjusted to compensate for differences in amplitude for the amplitude. phase modulation conversion. This pilot amplitude adjustment is preferably carried out only once, either as part of the amplifier design process, as part of the final tuning procedure performed in each amplifier design process, or as part of the final tuning procedure carried out performed in the factory on each amplifier. Referring now to Figure 3, a preferred alternative embodiment is illustrated. This mode is preferred over the system of FIG. 1 in some applications, such as applications where the associated amplifier is directed to the same power level of the main amplifier. This approach can give better error cancellation than the two previous modes because the two amplifiers of the same power level can have the distortion characteristics compared more closely than the two amplifiers of different power levels. However, in order to operate efficiently, the power outputs of the associated amplifier 110 must be summed in phase with the output of the main amplifier 152, so that both amplifiers contribute equally to the output of the system 258. The system shown in figure 3 it provides a means to carry out this sum of power by first adding a three-way splitter 302 to create a third input signal path including the third delay line 304 and the third gain and phase control 306 for driving the second pilot modulator 138. The error insertion coupler 136 is placed next to the third input signal path and is connected between the third gain and phase control 306 and the second pilot modulator 138. The output 129 from the second delay line 120 is fed into an output combiner 308 so that it can be added to the output of the main amplifier 154. During the design of the initial system, the delay of the third delay line 304 was chosen to compare the delay from the input divider 302 to the output of the error amplifier 122. During the alignment process, the third phase control was adjusted and gain 306 in order to minimize the signal from a dump port detector 310, thereby minimizing wasted power at dump port 312 connected to output combiner 308. This forces the main and associated amplifiers 110, 152 to operate substantially at almost the same level of phase power (the power levels will be truly identical if there is no loss of power in the carrier cancellation combiner and the second delay line). The adjustment of the third phase and gain control 306 is normally made between the phase and gain control settings, first 108 and second 118. Another preferred embodiment is provided in Figure 4. This system is similar to Figure 3, in FIG. It is used in situations when both main and associated amplifiers have almost the same power output capacity. The main difference is that in Figure 4 the second signal path (error amplifier and associated blocks) is dispensed with in Figure 3, but at the expense of a more complicated alignment procedure, as indicated below. 1. The first stage is to realign the system as a conventional type 2 feed-in-progress cycle. This can be carried out by switching off the second pilot modulator, followed by the alignment procedure described in the copending US Patent Application Serial No. 08/282298. 2. Turn on the second pilot modulator again. 3. Repeat the following stages in sequence. 3a. Adjust the first and second gain controls together and in the same direction to nullify the detected gain pilot signal. 3b. Adjust the first phase control, if necessary, to nullify the detected phase pilot signal. 3c. Adjust the second gain and phase controls to minimize the energy supplied to the emptying load. It should be noted that step 3b is only needed to compensate for incidental phase shift in the gain adjusters and amplitude modulation (AM) / phase modulation (PM) conversion in the amplifier stages. If these problems are not so severe, stage 3b may be omitted without impacting the completion of the final system (postalization). This is because, theoretically, the gain balance is the only difference between a feed cycle in straight forward type 2, and one that uses predistortion for the correction of additional error. Those skilled in the art will understand that the method and apparatus described above is operative to amplify multi-carrier input signals to produce an amplified output and reduce the IM products.

Furthermore, preferred embodiments advantageously perform this desirable function without using expensive spectral analysis equipment and without a slowly converging interative process. The advantages and additional modifications of the apparatus and method described above will readily occur to those skilled in the art. Accordingly, the invention, in its broader aspects, is not limited to the specific details, representative apparatuses and illustrative examples shown and described above. Various modifications and variations may be made to the above specification without departing from the scope or spirit of the present invention and it is intended that the present invention cover all modifications and variations provided that are within the scope of the following claims and their equivalents.

Claims (10)

1. NOVELTY OF THE INVENTION Having described the present invention, it is considered as a novelty and therefore the content of the following claims is claimed as property: 1. A corrected error amplifier circuit for use in a radiofrequency system comprising: a first step of pilot modulation that creates a first amplified signal having an error component and an error signal indicative of the error component; and a second pilot modulation stage that receives the first amplified signal and the error signal and generates a reduced amplified error signal.
2. 2. The amplifier circuit according to claim 1, characterized in that said first pilot modulation stage comprises a circuit of pilot modulation and an amplifier that responds to the pilot modulation circuit.
3. The amplifier circuit according to claim 1, characterized in that said first pilot modulation stage comprises: a signal splitter that receives an input signal and generates a first and second input signals; a pilot modulator coupled to said signal divider and receiving the first input signal; a phase and gain control circuit coupled to said signal divider and receiving the second input signal: an amplifier responsive to the pilot modulator; and a coupler responsive to said amplifier and responsive to said phase and gain control circuit, said coupler generating said first amplified signal.
4. The amplifier circuit according to claim 3, characterized in that said first pilot modulation stage further comprises a second phase and gain control circuit in communication with said coupler and an error amplifier coupled to the second gain and gain control circuit. phase and that generates said error signal.
5. The amplifier circuit according to claim 3, characterized in that said phase and gain control circuit is in communication with a programmable controller.
6. The amplifier circuit according to claim 1, characterized in that the second step of pilot modulation comprises: an error insertion coupler receiving said first amplified signal and said error signal; a second pilot modulator that responds to said error insertion coupler; and a main amplifier that responds to said second pilot modulator, said main amplifier generating said amplified reduced error signal.
7. 7. The amplifier circuit according to claim 1, characterized in that said radiofrequency system comprises a cellular system and a microwave system.
8. 8. A method for aligning an error correction amplifier circuit for use in a radio frequency system comprising the steps of: providing a first amplifier having the inherent distortion characteristics; providing a second amplifier having distortion characteristics substantially similar to those of the first amplifier; establishing a first phase and gain control circuit in response to a power level detected by a carrier detector which responds to the first amplifier; and establishing a second phase and gain control circuit in response to an output of a pilot detector which responds to the second amplifier to produce an error signal that is out of phase of the output of the first amplifier.
9. 9. An error correction radiofrequency amplifier circuit comprising: an amplifier, - a pilot phase source; a pilot source of profit; a pilot modulator coupled to the amplifier; and a first on / off switch that selectively couples the pilot modulator and the phase pilot source.
10. 10. The amplifier circuit according to claim 9, further comprising a second on / off switch that selectively couples the pilot modulator and the pilot gain source.