MXPA97003335A - Automatic gain control circuit for unreceptor digi - Google Patents

Automatic gain control circuit for unreceptor digi

Info

Publication number
MXPA97003335A
MXPA97003335A MXPA/A/1997/003335A MX9703335A MXPA97003335A MX PA97003335 A MXPA97003335 A MX PA97003335A MX 9703335 A MX9703335 A MX 9703335A MX PA97003335 A MXPA97003335 A MX PA97003335A
Authority
MX
Mexico
Prior art keywords
symbols
receiver
data
pilot
data symbols
Prior art date
Application number
MXPA/A/1997/003335A
Other languages
Spanish (es)
Other versions
MX9703335A (en
Inventor
W Citta Richard
J Sgrignoli Gary
Original Assignee
Zenith Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/335,603 external-priority patent/US5565932A/en
Application filed by Zenith Electronics Corp filed Critical Zenith Electronics Corp
Publication of MX9703335A publication Critical patent/MX9703335A/en
Publication of MXPA97003335A publication Critical patent/MXPA97003335A/en

Links

Abstract

The present invention relates to a method for operating a digital data receiver to receive a digital signal including a pilot and a plurality of multiple level data symbols that are displayed at a constant symbol rate, the method is characterized in that it comprises: convert the received data symbols to corresponding digital values, eliminate the effects of the pilot on the digital values, sample the data symbols for a predetermined time to determine an average data symbol value, compare the determined average data symbol value with an average reference data symbol value, and adjust the gain of the receiver with a comparison function

Description

CIROJITO OF AUTOHATICO GAIN CONTROL FOR A DIGITAL RECEIVER The present invention relates generally to digital data receivers and particularly to an AGC system for a digital television signal receiver. Recently, numerous systems have been proposed to transmit and receive television signals in digital form. The television signal may comprise, for example, a compressed broadband HDTV signal or one or more compressed NTSC signals. The two most widely promoted modulation techniques for effecting such transmissions are quadrature amplitude modulation (QAM) and residual sideband modulation (VSB). U.S. Patent No. 5,087,975 describes a VSB system for transmitting a television signal in the form of si boluses of M successive levels on a standard 6 MHz television channel, with a relatively small pilot, which is of the low power level, in the lower edge of the channel. Although the number of levels M, which is the VSB mode characterizing the symbol levels may vary, the speed of the symbol is preferably fixed, such as at a rate of 684 H (approximately 10.76 megabytes per second) where H is the frequency of horizontal exploration NTSC. The number of symbol levels used in any particular arrangement is largely a function of the signal-to-noise ratio that REF: 24574 characterizes the transmission medium with a small number of symbol levels that are used in situations where the ratio of signal to noise is low, that is, in noisy environments. For a system capable of providing a relatively benign environment, a system that accommodates symbol levels of 16, 8, 4 and 2 provides flexibility for more satisfactory conditions. For terrestrial or air emissions where the environment is less benign, a VSB mode of 8 (ie, level 8 data symbols) is appropriate. It should be appreciated that lower values of M can provide improved signal-to-noise operation at the expense of a reduced transmission bit rate. For example, assuming a speed of 10.76 megabytes per second, a level two VSB signal (one bit per symbol) provides a transmission bit rate of 10 * 76 megabits per second while a level four VSB signal (two bits per second). symbol) provides a transmission bit rate of 21.52 megabits per second. The proper operation of a digital receiver, such as a television receiver, requires that the received carrier signal be acquired relatively quickly and the gain of the RF and IF sections of the receiver appropriately adjusted. The acquisition of the carrier in the QAM receivers is relatively difficult due to the absence of some type of pilot. Although the use of a pilot in the aforementioned VSB system greatly facilitates the acquisition of the carrier, difficulties are nevertheless encountered due to the relatively low level of the pilot and limited traction in the range of the synchronous demodulators used in those receivers. . We have previously developed systems, as shown in International Publications Nos. WO95 / 8508 and O95 / 8509, to increase the traction of FPLL and to deal with the biphasic stability of the frequency and the closed phase circuit in the synchronous demodulator. This invention is directed towards a novel AGC system for use in a digital television receiver where the signal includes a pilot. A basic object of the invention is to provide a novel AGC system for a digital data receiver. Another object of the invention is to provide a gain adjustment control system for a digital data receiver showing the levels of the data symbols. These and other objects and advantages of the invention will become apparent upon reading the following description in conjunction with the drawings, in which: Figure 1 is a partial block diagram of a television receiver constructed in accordance with the invention; and Figure 2 is a partial diagram of another version of a television receiver constructed in accordance with the invention. As mentioned, the transmitted signal VSB preferably includes a small pilot at the lower limit of the 6 MHz television channel and may comprise level 2, 4, 8 or 16 symbols (or a combination thereof). The symbols are preferably arranged in successive data fields, each data comprising 313 data segments. Each data segment comprises 832 symbols including four level two symbols representing synchronous data segments and the first data segment of each field comprises a sequence of level two symbols representing a frame synchronization code. In the preferred embodiment, the data symbols are level 8, although symbols having different levels according to the invention may also be used. The pilot can be conveniently developed at the transmitter by introducing a deviation (ie, a constant CD level) for the symbol values. In the receiver, the deviation generates a constant CD which is used to recover the carrier. Referring to Figure 1, the RF signals are converted to IF signals by a tuner 10. The RF signals can be received via an antenna 12 for terrestrial signals or via a cable input 14 for cable signals. It should be appreciated that the different elements of the receiver are generally under the control of the microprocessor, although this is not illustrated in order to simplify. The IF output of the tuner 10 is supplied to a SAW filter of IF 16 and consequently to an IF amplifier 18. The output of the IF amplifier 18 is supplied to a synchronous demodulator 20 which in turn feeds an analog converter to digital (A / D) 22 in which the amplitudes of the received symbols are converted to corresponding digital values. An A / D 22 supplies a data recovery circuit 24 in which the data symbols are retrieved, a symbol clock recovery circuit 26, wherein the synchronization signals are developed based on the synchronization information and a filter linear (such as a characteristic filter on a back comb) or a CD removal circuit 28 where the CD is removed. The CD, which will be claimed, represents the pilot and uniformly affects all the symbol values in the form of a deviation. The output of the removal circuit CD 28 is supplied to an absolute value circuit 30 which provides an output representing the magnitude of the symbols. The absolute value circuit 30 is used to rectify the values of the received symbols since they can assume negative as well as positive levels. For example, the levels for VSB mode 8 may comprise -7, -5, -3, -1, +1, +3, +5 and +7. The absolute value circuit 30 supplies its output to a sampling device 32, which is controlled by a division counter by four 34. The symbol clock recovery circuit 26 provides a synchronization signal to the A / D converter 22, the division counter by four 34 and an accumulator and a divider circuit 36 which is provided with the output of the sampling circuit 32. The synchronization signal preferably comprises a clock signal at the speed of the symbol. A cable / terrestrial control input is provided to the accumulator and divider circuit 36 for the purposes to be described. The outputs of the accumulator and the divider circuit 36 comprise the average value of the sampled data symbols over a predetermined time interval and is supplied to the positive input of an adder 38. The negative input of the adder 38 is supplied from a reference source 40, which applies a reference signal representing the known average value of the symbols. This is based on the symbols that are random and the knowledge of the level of the symbol, that is, the VSB mode. For VSB = 8, with the rectified symbol level being +1, +3, +5, +7 (and the pilot having been removed by circuit 28), the average symbol value = 4. The average symbol value of reference is subtracted from the determined average symbol value and the difference represents that both the actual data levels are above or below the reference. The output or result of the comparison is supplied to a logic circuit AGC 42 which in turn controls the AGC of the tuner 10 and the amplifier IF 18. During the initial operation, the AGC 42 logic circuit operates the tuner and the circuits of IF at a maximum gain. This is to help in the acquisition of the carrier due to the low level pilot that is involved in the signal. Sampling circuit 32 shows every Nesimo symbol and provides that value to the accumulator and divider circuit 36. It should be remembered that the symbol values have been rectified by the absolute value circuit 30 and that the pilot (CD deviation) has been removed by the circuit 28. The circuit 36 accumulates the symbol values for a fixed number of Y values and sampled and divides that amount by the fixed number Y to provide an average Y value derived from a received data symbol. This average data symbol value is compared to the average reference value and the AGC is adjusted to reduce the IF tuner gain of the maximum based on this comparison. In practice, N is equal to 4 and the number of symbols that accumulate (Y) covers seven symbol segments for a terrestrial signal. For a cable signal that can be subjected to a high level sweep signal for testing purposes, the sample is taken over a different period to minimize the effects of such a high level sweep signal. Accordingly, for cable inputs, the accumulated and divided relationships will be different and this is controlled by the cable / terrestrial control input to the accumulator and the divider circuit 36. The circuit 28 in Figure 1 is identified either as a filter linear or as a CD removal circuit. The main function of the circuit 28 is the removal of CDs, that is to say eliminating the effects of the pilot on the values of the symbols that were determined. In US Patents Nos. 5,086,340 and 5,087,975, the effects of operating a digital television receiver in the vicinity of a co-channel NTSC signal are described. In particular, a linear filter (rear comb characteristic circuit) is inserted into the received data stream to eliminate most of the interference from the NTSC co-channel signal. The linear filter has the effect of also removing any CD and accordingly the present invention can conveniently be provided to retrieve the digital data symbols from the output of a linear filter that could eliminate the need for a separate CD removal circuit.
In Figure 2, the arrangement of the circuit of Figure 2 substantially doubled with the exception of the addition of a synchronous filter 23 and a synchronous correlation filter 25 between A / D 22 and the symbol recovery circuit 26. In the U.S. Patent No. 5,416,524, the synchronization recovery arrangement is described by virtue of a pair of filters having appropriately designed characteristics such that a filter produces a discriminator characteristic curve in response to the synchronous character in the transmitted signal and the other filter produces a peak characteristic in response to the synchronic character. In that arrangement, the synchronous correlation filter 25 has the feature of also removing CD. Consequently, the deviation of the pilot signal could be compensated automatically for that filter array. In this arrangement (Figure 2), the absolute value circuit 30 is connected to the output of the synchronous correlation filter 25. In other aspects, Figure 2 is the same as Figure 1 as indicated by similar numerical references denoting similar elements. The operation of the circuit arrangement of Figure 2 is identical to that of Figure 1. What has been described is a novel technique for a digital television signal that includes a pilot. It should be recognized that numerous changes in the described embodiment of the invention will be apparent to those skilled in the art and that the invention is limited only as defined in the claims. It is noted that in relation to this date, the best method known to the applicant to carry out the invention, is that which is clear from the present description of the invention. Having described the invention as above, property is claimed as contained in the following:

Claims (15)

1. A method of operating a digital data receiver for receiving a digital signal including a pilot and a plurality of multi-level data symbols occurring at a constant symbol rate, characterized in that it includes the steps of converting the received data symbols at corresponding digital values, eliminating the effects of the pilot on the digital values, sampling the data symbols for a predetermined time to determine an average data symbol value, comparing the determined average data symbol value with a data symbol value reference average, and adjust the gain of the receiver as a function of the comparison.
2. The method according to claim 1, characterized in that the sampling is performed every N data symbols and where the average is performed on Y data symbols.
3. The method according to claim 1 or 2, characterized in that it includes rectifying the digital values.
4. The receiver according to claim 2, characterized in that the digital signal is formatted in repetitive segments of a fixed number of symbols and where Y covers a number of such segments.
5. The method according to claim 4, characterized in that the receiver has a cable signal input and a terrestrial signal input and where Y is different for received cable signals.
6. The method according to claim 4, characterized in that the pilot is represented by a CD component and wherein the removal step removes the CD component.
7. The method according to claim 4, characterized in that the receiver includes a linear filter for removing the co-channel interference, the linear filter has a CD response of zero, and wherein the elimination step comprises sampling the linear filter symbols.
8. A gain adjustment control circuit (AGC) for a data receiver that receives a digital television signal that includes a pilot and a plurality of multi-level data symbols that occur at a constant symbol rate, the circuit is characterized because it includes a converter to change the received data symbols to digital values, a CD removal circuit to remove the effects of the pilot on the digital values, a sampling device arranged to receive the data symbols, circuit means that averaging the symbol value to determine an average received data symbol value for such symbols received by operating the sampling device for a predetermined period, comparing circuit means for comparing the determined average data symbol value with a value of average reference data symbol, and control circuit means to adjust the ga nance of the receiver based on such comparison.
9. The AGC circuit according to claim 8, characterized in that each N data symbols are sampled and where the predetermined time covers AND data symbols.
10. The AGC circuit according to claim 8, characterized in that the digital signal is formatted in repetitive segments of a fixed number of symbols and where Y covers a number of such segments.
11. The AGC circuit according to claim 9 or 10, characterized in that the receiver has a cable signal input and a terrestrial signal input and where Y is different for received cable signals.
12. The AGC circuit according to claim 8, 9 or 10, characterized in that it includes rectifier circuit means for rectifying the digital values.
13. The AGC circuit according to claim 8, 9 or 10, characterized in that it includes a controllable gain stage, the control means are capable of operating the gain controllable stage at a maximum during the initial reception of a digital signal.
14. The AGC circuit according to claim 8, 9 or 10, characterized in that the pilot is represented by a CD component and wherein the CD removal circuit blocks such CD component:
15. The AGC circuit according to claim 8, 9 or 10, characterized in that it includes a linear filter to remove the co-channel interference, the linear filter has a zero response to CD, and where the sampling device is coupled to receive the signal from the linear filter.
MXPA/A/1997/003335A 1994-11-08 1997-05-07 Automatic gain control circuit for unreceptor digi MXPA97003335A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/335,603 US5565932A (en) 1994-11-08 1994-11-08 AGC system with pilot using digital data reference
US08335603 1994-11-08
PCT/US1995/013875 WO1996014700A2 (en) 1994-11-08 1995-10-26 Agc circuit for a digital receiver

Publications (2)

Publication Number Publication Date
MX9703335A MX9703335A (en) 1997-07-31
MXPA97003335A true MXPA97003335A (en) 1997-12-01

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