MXPA97002784A - Apparatus for detecting and responding to series arcs in ac electrical systems - Google Patents

Abstract

Series arcs in an ac circuit are discriminated from other phenomenon by analyzing the timing between pulses in a second derivative of the current signal. A first timer starts timing upon detection of a first pulse in the second derivative of current signal. Time out of the first timer starts a second timer which times a second interval or window during which a series arcing fault will generate a second pulse of opposite polarity to the first pulse. Detection of the first pulse followed by a second pulse of opposite polarity during the window sets a flip-flop to record the event. When a predetermined number of events are counted by a counter within a given time-period set by a third timer, an output signal indicating an arcing fault is generated. If the second pulse is generated before the window opens, or a third pulse is generated before the window opens, or a third pulse occurs during the window, the flip-flop cannot be set so that other events such as the switching of a dimmer do n ot generate a false output signal.

Description

APPARATUS TO DETECT AND RESPOND TO ARCOS IN SERIES IN ELECTRICAL SYSTEMS CORRIENT1 BACKGROUND OF THE INVENTION Field of the Invention This invention relates to detection and interruption of arcs in series in an AC electrical system. Information Background The faults by arcing in AC electric systems are of two types: arcs in parallel and arcs in series. Parallel arcing faults are line-to-line faults or line-to-ground faults that can occur, for example, when conductor insulation becomes gnawed or penetrated. Such parallel arcing faults can withdraw a considerable current but usually below the typical circuit breaker's draw current. They also tend to be intermittent because the repulsion forces generated by the arc current tend to temporarily separate the conductors and extinguish the arc. In this way, parallel arcs are often referred to as sizzling arcs. Failures by series arcing, on the other hand, occur in a single driver's path, such as where a driver has been cut or is in a loose or poor connection. The current in a series arc depends on the load, but may be in the milliampere range. Methods and devices previously disclosed to detect line-to-line or line-to-ground arcs have proven successful. However, lower level arcs in series with a load may go beyond the capabilities of these techniques. There are two obstacles to merely increasing the sensitivity of previous techniques. At increased sensitivities, there may be more charges and combinations of charges that produce false triggers. Additionally, at lower currents, the current waveform differs from that produced at higher currents, mainly because since the current level will be too low to fly the arc, the current will be more continuous, except for discontinuities at junctions in zero current. Previous attempts to detect serial arcs have focused mainly on analyzing the high frequency content of the arc current. Such techniques typically involve analyzing various merit figures of this high frequency content. There are several problems with this approach. First, numerous loads, such as for example computers, have capacitive filters at their inputs, while others, such as motors or audio equipment with transformer inputs present an inductive impedance to the electrical system. Such charges filter the high frequency content of the arc current. Furthermore, many of these arc detectors that analyze the high frequency content of the arc current require a microprocessor, which increases the cost prohibitively for extensive use. Accordingly, there is a need for improved apparatus and method for detecting faults by arcing in series. There is an additional need for such improved apparatus and method for detecting series arcing faults that can be used in alternating current circuits that energize any of the common types of loads, including loads with capacitive filter inputs, transformers and motor loads. . There is an additional need for such series arc detection that can detect such arcs anywhere in the protected circuit portion. There is a further need for such failure detection by series arcing that operates over a wide dynamic range of fault currents. There is also a need to provide such an improved apparatus and method for detecting arcing faults, which are economical for extensive use. Compendium of the Invention These needs and others are met by the invention, which is based on the discovery that a series arc generates a recognizable distortion, predictable of the arc current. During each half cycle, when the voltage drops below the arc voltage, the current will drop to zero and remain at zero until the voltage rises again over the arc voltage in the next half cycle. Since the arc voltage typically remains constant, the discontinuities in the alternating current waveform will be repeated regularly at each zero crossing. These discontinuities produce pulses in the second derivative of the current, which are of opposite polarity. The sequence of the polarity of the pulses is inverted for crosses at zero in both directions. The two pulses at each crossing at zero will be separated in time by the length of the discontinuity of the crossing at zero. This time is a function of the arc voltage, the line voltage and the line frequency, but it is not a linear function of the current level. In this way, the technique can be used to detect faults by arcing over a wide range of current amplitudes. According to the invention, sensor means are provided for detecting the current in the alternating current circuit and generating a second derivative signal representative of the second derivative of the current. As discussed above, this signal will have pairs of pulses of opposite polarity spaced in time. In this way, means are provided to generate an output signal based on the timing between the pulses of the second derivative signal. More particularly, an output signal indicative of an arcing fault is generated if a second pulse appears in the second derivative of the current signal within a predetermined duration interval starting a predetermined time after the first pulse and is of polarity opposite to the first pulse. There are two known charges that can mimic to some extent the serial arc waveform. These are a light dimmer for lamps and a power source using a full wave rectifier and a capacitor input filter, as can be used, for example, in a television receiver. It can be expected that the energy source has a longer discontinuity than a serial arc, except for a very short period of time when the power source is turned on. Therefore, according to the preferred embodiment of the invention, means are provided to generate an output signal indicative of an arc only when the pattern of a pair of arcs of opposite polarity with the prescribed timing between pulses occurs repeatedly. . The second derivative signal of the current generated by a lamp dimmer has a triple pulse of alternating polarities at each zero crossing. The spacing of the first and second pulses is a function of the reading of the light reducer, and therefore may be within the expected timing range for the arc in series. However, the first and second pulses will always be very close to each other. Therefore, the apparatus according to the invention includes means that prevent the generation of an output signal indicative of an arc if a third pulse follows the second pulse within the predetermined duration interval. In addition, an additional pulse that occurs after the first pulse but before the interval also blocks the generation of an output signal. The invention may include means that detect the polarity sequence of crosses at zero in only one direction, or crosses at zero in both directions. In the latter case, means can be provided that generate a final output signal only if the output signals are generated by means that respond to the crosses at zero in both directions. BRIEF DESCRIPTION OF THE DRAWINGS A full understanding of the invention can be gained from the following description of the preferred embodiments, when read in conjunction with the accompanying drawings, in which: Figures 1A, B and C illustrate current waveforms, the first current derivative and the second current drift, respectively, generated by an arc in series in an electrical system. Figures 2A, B and C similarly illustrate current waveforms, the first current derivative and the second current derivative generated by a light reducer energized by an AC electrical system.

Figures 3A and B are a schematic circuit diagram of a series arc detector according to the invention. Figure 4 is a schematic block diagram of a modification of a portion of the circuit of Figures 3A and B according to another embodiment of the invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 1 illustrates waveforms associated with a series arc in an AC electrical system. The trace 1 in Figure 1A illustrates the current. When the voltage in the ac system falls below the arcing voltage (typically around 20 to 30 volts in a 120 volt system), the current is interrupted as in 3 in Figure 1A. The current remains at 0 until the voltage rises above the arcing voltage in the next half cycle and the arc is struck again. In this way, in point 5, following the restoration of the arc, the current is restored. The first derivative of the arcing current 1 shown in FIG. 1A is illustrated in FIG. IB as the trace 7. As can be seen, there are substantial steps 9 and 11 when the current is interrupted and when it is restored again. Figure 1C illustrates the second derivative 13 of the arcing current. The second derivative signal 13 exhibits a pair 15 of pulses 17 and 19 that result from the discontinuities in the current at the interruption of the arc and the restoration of the arc. It can be seen that these pulses 17 and 19 are of opposite polarity. As can also be seen, the polarity sequence depends on the direction of the zero crossing. In other words, the polarity sequence is inverted in successive half cycles. As mentioned before, a charge that can generate waveforms having similarity to those generated by a series arc is a light reducer. A light reducer delays the switching on of a switching device during each half cycle of the AC voltage in order to control the energy delivered to the load. Typically, the retro-phase angle is selectable to provide a range of energy readings. This delayed switching produces the waveforms illustrated in Figures 2A, B and C. Figure 2A illustrates the current waveform of light reducer 21. As can be seen, the current is turned off at 23 at the end of a half cycle and remains at zero until the light reducer switch is again activated at 25, causing the current to rapidly increase to point 27, where it becomes sinusoidal. Figure 2B illustrates the first derivative 29 of the light reducer stream. As can be seen, it has a discontinuity at 31, where its value goes to zero and a peak at 33. Figure 2C illustrates the second derivative waveform 35 of the light reducer current. As can be seen, this second derivative of the light reducer current has a small pulse 37, where the current fails at 0 and then remains at 0, and a pair of pulses 39 that include a first pulse 41 when the first current is restores and increases rapidly, and a second pulse 43 where the current enters into transition to a sinusoidal waveform. As illustrated, the pulses 41 and 43 are of opposite polarity. It can also be seen that the pulses 37 and 41 are of opposite polarity. The technique for serial arc detection of the invention takes advantage of the fact that the second pulse 19 in the second derivative of the current resulting from a failure by arcing in series follows the first pulse 17 by a predictable interval of time and It is of opposite polarity. Therefore, such a pulse can be detected by looking for a second pulse in the second derivative current of the AC electrical system that occurs within a time window that begins a selected time after a first pulse and is of opposite polarity to the first pulse. . Referring to Figure 2C, it can be seen that the light reducer generates a pair of pulses 37 and 41 that are separated in time and are of opposite polarity. Pulses 41 and 43 also constitute a pair of pulses of opposite polarity but are always in rapid succession. However, it is possible for the timing between the pulses 37 and 41 to fall within the established window to detect the pulses 17 and 19. In order to discriminate the failure by in-formation of serial arcs of a reducer, the present invention seeks the third pulse 43, which rapidly follows the second pulse 41 in the second derivative of the current of the light reducer. Nor does it ignore the conditions in which the second pulse follows the first pulse too quickly. Figures 3A and B illustrate an exemplary embodiment of the arcing fault detector 101 according to the invention for detecting faults by arcing in series in an AC electrical system 103 having a conductor 105 which can be the line or neutral conductor. A sensor circuit 107 detects the second derivative of the current flowing in the conductor 105. This sensor circuit 107 includes a current transformer 109, which generates a first derivative of the current signal, di / dt, by the use of a core of material such as pulverized iron, which has low mu and a high level of saturation of flow. This first derivative of the current signal, di / dt, is limited in bandwidth by the bandwidth limiter 111 comprising a shielding capacitor 113 and the resistor 115. A differentiator 117 in the form of a series capacitor 119 and the resistor 121 generates a second derivative of the current signal i2 / dt. Additional limitation of bandwidth is provided by circuit 123, which includes an operational amplifier 125 with the feedback resistor 127 and the feedback capacitor 129. The Zener diodes 131 prevent saturation of the operation amplifier 125 by large pulses in the di2 / dt signal. Additional noise attenuation of 60 Hz is provided by the capacitor 133. The suppression of radio frequency noise is provided by the capacitor 135 through the inputs to the operation amplifier 125. Since the pulses in the di2 / dt signal can have a wide dynamic range, a amplifier stage 137 comprising the operation amplifier 139 with the feedback resistor 141, and the input resistor 143. Again, Zener diodes 145 back to back prevent the operation amplifier 139 from being saturated by large pulses and the capacitor 147 provides suppression of radio frequency noise. Sensor circuit 107 also includes differential comparators 149 and 151, which compare the output of amplifier stage 137 with the reference voltages of 6.5 and 19.5 volts, respectively. Since a +13 volt polarization is applied to the operation amplifiers 125 and 139, the signal applied to the non-inverting input of the comparator 49 and the inverting input of the comparator 51 is 13 volts when the signal di2 / dt is zero. Under these conditions, the outputs of the comparators 149 and 151 are high and the MINUSBAR OUT signal at the output of the comparator 149 is pulled up to 13 volts by the resistor 153. Similarly, the output signal PLUSBAR OUT of the comparator 151 is pulled at 13 volts through the resistor 155. A positive pulse on the di2 / dt signal at the output of the operation amplifier 139 that is above an absolute threshold of 6.5 volts causes the PLUSBAR OUT signal to go low. A negative pulse of more than 6.5 volts absolute causes the MINUSBAR OUT signal to go low. In this way, the PLUSBAR OUT and MINUSBAR OUT signals are normally high, but they go low momentarily in response to a positive pulse and a negative pulse, respectively, in the di2 / dt signal. Figure 3B illustrates a signal generating circuit 157, which generates an output signal indicative of an arc in response to a preselected polarity sequence and timing between the pulses in di2 / dt. The PLUSBAR signal is applied to the input B of a first monostable 159. The negative or trailing edge of the PLUSBAR signal initiates the timing by the monostable 159 of the first timing interval. This causes the Q output of the monostable 159 to go high. When the monostable 159 expires, its output Q goes low, triggering a monostable second 161 to start the timing of the second timing interval. This is the interval of timing in which a second pulse of opposite polarity will appear in the case of a failure by arcing in series. An output signal generator 162 includes a flip-flop R-S 163, which has the output QBAR of the second monostable 161 connected to its reset input R.

Since the QBAR output of the monostable 161 is normally high, except during the second timing interval, the Q output of the R-S flip-flop will normally be low. The input S of the flip-flop RS 163 is connected to a negative logic circuit NAND 165 having as input the output QBAR of the second monostable 161 and the signal MINUSBAR applied through a delay circuit 167, which includes a resistor in series 169 and the shielding capacitor 171. The negative logic element NAND 165 is only able to be enabled by the QBAR output of the second monostable 161 during the second timing interval. A negative pulse on the di2 / dt signal (MINIUSBAR goes low) during this second timing interval will cause the S input to the R-S 163 flip-flop to go high, setting the Q output of the flip-flop to a high state. The delay 167 prevents the flip-flop 163 from being set until it is determined that a third pulse does not occur during the second interval. This condition is detected by the circuits, which include one having as input the PLUSBAR signal and like the other input the QBAR output of the second monostable 161. In this way, during the second interval, the output of the negative logic element NAND 173 will normally be zero. This output of the negative logic element NAND 173 serves as an input to a ÑOR element 175, which has as a second the output of a negative logic circuit NAND 77 which, as will be explained, is low during the second interval. In this way, normally during a second interval the output of a ÑOR 175 circuit will be high, which keeps the RBAR inputs high to the first and second monostable 159 and 161. If the PLUSBAR signal goes low during the second interval, indicating a second pulse during the second interval or a third pulse after the timing has started, the output of the negative logic circuit NAND 173 goes high, which causes the output of the ÑOR 175 circuit to go low, thereby resetting both monostable 159 and 161. When the second monostable 161 is reset, its QBAR signal goes high to reset the RS 163 flip-flop and disable the NAND 165 negative logic circuit to prevent the MINUSBAR signal from setting the RS flip-flop after the time delay 167 expires. The NAND 177 negative logic circuit terminates the timing if the second pulse, MINUSBAR, occurs too early, ie during the first in Terval During this first interval, the negative logic circuit 177 is enabled by the QBAR signal of the first monostable 159. Normally, the MINUSBAR signal is high during the first interval, thereby causing the output of the NAND negative logic circuit 177 to be low. However, if the MINUSBAR signal goes low, indicating a second pulse in the di2 / dt signal, the output of the NAND negative logic circuit 177 goes high, thereby resetting the monostable 159 and 161 via the ÑOR 175 circuit.

When the Q output of the RS 163 flip-flop goes high, meaning the detection of a positive pulse followed by a negative pulse within a time interval (the second time interval) starting a predetermined time (the first interval of time). time) after the first pulse, a third monostable 179 that is part of the output signal generator 162 begins to count a time interval. This output of the flip-flop RS 163 also sets a digital timer 181 to the clock. Each time the flip-flop RS 163 generates a pulse during the time interval set by the monostable 179, the counter 181 is incremented. When the monostable 179 expires, its QBAR output goes high to reset the counter 181. A selected output 183 of the outputs of the counter 181 provides the output signal 184 indicative of an arcing fault. The count of selected outputs indicates the number of events in which a positive pulse was followed by a negative pulse during a time interval set by the monostable 179. The circuit of figures 2A and 2B only counts events in which a positive pulse in the signal di2 / dt it is followed by a negative pulse within a given time interval. In this way, it only counts those events that occur during crosses in zero from negative to positive, or once per cycle. By inverting the PLUSBAR and MINUSBAR entries in Figure 2B, the events that occur at crossings at zero in the opposite direction can be detected. Again, this would only count one event per cycle of the alternating current cycle. In order to increase the reliability of the series arcing detector, the pulses of opposite polarity in the di2 / dt signal during each half cycle can be detected. This can be achieved by duplicating the circuit of Figure 2B with the inverted PLUSBAR and MINUSBAR inputs with the outputs of the respective RS flip-flops connected to a common timer 179 and the digital counter 181. A simpler arrangement is to provide an inverter circuit 185, as shown in Figure 3. This inverter circuit 185 includes four CMOS switches 187, 189, 191 and 193. The switch 187 connects the PLUSBAR signals to an output A, while the switch 189 connects the same signal to the output. B. Similarly, the switch 191 connects the MINUSBAR signal to the A output while the switch 193 connects it to the B output. The switches 187 and 193 are closed simultaneously by a high output on the Qx output of the counter 81. so that when this count is high, the PLUSBAR signal is connected to the A output and the MINUSBAR signal is connected to the B output. An inverter 195 turns on switches 189 and 191 for invert go the PLUSBAR and MINUSBAR signals in alternating accounts of the counter. Since these outputs A and B are connected to the inputs A and B of the signal generator circuit 157 in FIG. 3B, it can be seen that the events occurring at both zero crossings of the alternating current are detected. In this case, the count in the digital counter 181 during the interval determined by the monostable 179 would be twice that described in the first case, where only the events occurring in crosses at zero in one direction were counted. The series arc detector of this invention can be used by itself to provide an indication of a series arc. It can also be incorporated into a circuit breaker to provide a trigger signal in response to the arc in series. Further, it can be used in conjunction with a parallel arcing fault detector such as that described in U.S. Patent No. 5,224,006. Although specific embodiments of the invention have been described in detail, those skilled in the art will appreciate that various modifications and alternatives to such details can be developed in light of the overall teachings of the disclosure. Accordingly, the particular arrangements described are intended to be illustrative only and not limitative of the scope of the invention, to which the full scope of the appended claims and any and all equivalents thereof must be given.

Claims (17)

1. Apparatus for detecting a failure by arcing in series in an alternating current circuit, said apparatus comprising: sensor means detecting a second derivative of the alternating current in said alternating current circuit to generate a second derivative signal containing pulses in response to discontinuities in said alternating current such as said failure by arcing in series; and signal generating means that generate an output signal indicative of said failure by forming arcs in series in response to predetermined timing between said pulses in said second derivative signal. The apparatus of claim 1, wherein said sensor means generates from said second derivative signal a signal containing pairs of pulses with a second pulse occurring during a predetermined duration interval starting a predetermined time after a first pulse, and wherein said signal generating means comprises means generating said output signal only when said second pulse occurs within said second interval after said first pulse. The apparatus of claim 2, wherein said signal generating means comprises means preventing the generation of said output signal if an additional pulse occurs in said second derivative signal in said interval. The apparatus of claim 3, wherein said means preventing generation of said output includes means delaying said means generating said output signal until additional means determines that an additional signal has not occurred in said interval. The apparatus of claim 3, wherein said signal generating means further includes means preventing the generation of said output signal if said second pulse occurs before said interval. The apparatus of claim 2, wherein said signal generating means comprises means preventing the generation of said output signal if said second pulse occurs before said interval. The apparatus of claim 2, wherein said sensor means generating said second derivative signal with pulses, generate first and second pulses of opposite polarity in response to a failure by arcing in series, and wherein said means generating said The output signal comprises means that only generate an output signal when said second pulse occurs within said interval and is of opposite polarity to said first pulse. The apparatus of claim 7, wherein said means generates said output signal only when said first pulse is of a first polarity and said second pulse is of opposite polarity. The apparatus of claim 7, wherein said signal generating means includes means that prevent said means generating said output signal from generating said output signal when an additional pulse of any polarity occurs after said first pulse and before said pulse. interval The apparatus of claim 7, wherein said signal generating means comprises first means that generates a first event signal when said first pulse is of first polarity and said second pulse is of a second polarity, opposite said first polarity and occurs within said interval, and second means generating a second event signal when said first pulse is of said second polarity and said second pulse of said first polarity occurs within said interval and wherein said output means generates an output signal only when a predetermined number of said first and second event signals occur within a given period of time. The apparatus of claim 7, wherein said means generating said output signal includes means that generate an account of said first and second event signals and means generating said output signal only when said account reaches a predetermined number within a given period of time. 1

2. The apparatus of claim 1, wherein said means generating signals includes means that generate an account of the times that said second pulse occurs during said interval after said first pulse, and means that generate said output signal only when said account reaches a predetermined count within a period of time. of time given. 1

3. A method of detecting faults by arcing in series in an alternating current circuit, comprising the steps of: generating a second derivative signal representative of a second derivative of the current flowing in said alternating current circuit and having pulses in response to discontinuities in said current such as failure by arcing; measuring the time between pulses in said second derivative signal; and generating an output signal indicative of a failure by arcing in response to predetermined timing between said pulses. The method of claim 13, wherein said step of generating an output signal comprises generating said output signal only when said second pulse occurs during a predetermined duration interval starting within a predetermined period of time after a first pulse. . The method of claim 14, wherein said step of generating said output signal comprises generating said output signal only when said second pulse is of polarity opposite said first pulse. The method of claim 14, wherein said steps of generating said output signal includes not generating an output signal if a third pulse occurs during said interval. The method of claim 14, wherein said step of generating said output signal includes not generating said output signal when said second pulse occurs after said first pulse but before said interval.