MXPA96005108A

MXPA96005108A - Method and apparatus for automatic control deganance in a digi receiver

Info

Publication number: MXPA96005108A
Application number: MXPA/A/1996/005108A
Authority: MX
Inventors: B Wilson Nathaniel; E Peterzell Paul; J Black Peter
Original assignee: Qualcomm Incorporated
Priority date: 1994-04-28
Filing date: 1996-10-25
Publication date: 1997-08-01

Abstract

The present invention relates to an automatic gain control apparatus comprising an adjustable gain amplifier, the adjustable gain amplifier has an input port for receiving an input signal, a control port for receiving a gain control signal , and an output port for providing an output signal, the automatic gain control apparatus comprises: a means for generating a received power signal based on the power of the output signal, a saturation integrating means for comparing, in response to an integration capacitor signal, the received power signal to a reference signal and to generate the gain control signal, and a decision means to create the integration capacitor signal in response to the value of the control signal of gain, the value of the received power signal and the value of the reference signal

Description

METHOD AND APPARATUS FOR THE AUTOMATIC CONTROL OF GAIN IN A DIGITAL RECEIVER BACKGROUND OF THE INVENTION I_i. Field of the Invention The present invention relates in general to automatic gain control circuits. In particular, the invention relates to a novel method and apparatus for providing automatic gain control within a digital receiver.

II. Description of the Related Art In analog receivers, such as those used in narrowband FM cellular communication systems, FM demodulators are used to extract coded information in the phase of an incident waveform. Existing FM demodulators typically include an analog frequency discriminator preceded by an analog limiter, the limiter serves to restrict the power of the input signal to a constant level. In this way, the maximum signal-to-noise ratio is maintained, at the input to the frequency discriminator, over the full dynamic range of the FM input signal. However, this technique of analog signal processing generally involves intense filtering of the signal, and P1327 / 96 MX is often implemented using a large number of discrete components. In addition, it has been shown that improved performance can be obtained using a linear digital waveform demodulator instead of an analog demodulation. Unfortunately, conventional demodulation techniques are not normally applicable to digital receivers, since the descrambling of the received signal would result in corruption of the data derived therefrom. A digital receiver for receiving a digitally modulated information signal would, in general, include a variable gain amplifier with a gain adjusted by a control signal. The process for adjusting the gain of a received signal using a control signal is called automatic gain control (AGC-Automatic Gain).

"" Control) . In digital receivers, the AGC process typically involves the measurement of an output power of the variable gain amplifier. The measured value is compared to a value that represents the desired signal strength and a control signal for the variable gain amplifier is generated. The error value is then used to control the gain of the amplifier in order to adjust the intensity of the signal to match the desired signal strength. To perform digital demodulation with an optimal ratio P1327 / 96 MX to noise, the automatic gain control is used to maintain the magnitude of the baseband waveforms close to the full dynamic range of the analog-to-baseband digital converters. However, in general, this requires that automatic gain control be provided, especially the full dynamic range of the received signal strength. In a cellular environment, a digital receiver can receive a signal that experiences rapid and wide variations in signal strength. In digital receivers, such as those used in code division multiple access mobile cellular telephony (CDMA), it is necessary to control the power of the demodulated signal for an adequate signal processing. However, in digital receivers that are going to be both compatible CDMA and conventional compatible FM, ie CDMA / FM dual mode receivers, it is necessary to provide power control to take both broadband CDMA signals and FM band signals. narrow The control processes are complicated by the different dynamic intervals associated with the received signal strength FM and CDMA. That is, the magnitude of received FM signals can vary in a dynamic range greater than 100 dB, while CDMA systems typically result in a range P1327 / 96 MX ^ more limited, ie approximately 80 dB. The provisions of the separate AGC circuitry for each mode increase the complexity of the hardware and the costs of the receivers. In consecuense, it is desired to provide AGC circuitry capable of operating both on FM signals in a wide, narrow band dynamic range, as well as on broadband CDMA signals, or of more limited dynamic range. It is also desirable to provide digital AGC in low cost receivers using analog to digital (A / D) converters with limited dynamic range. Again, since FM signals within cellular systems can vary more than 100 dB and relatively cheap 8-bit A / D converters are limited to a dynamic range of approximately 48 dB, a cost-effective AGC implementation could be able to control the gain of the portion of the receiver that precedes the A / D converters so as not to exceed the dynamic range of the A / D converter. The alternative is to use expensive A / D converters that have a much higher dynamic range, thus increasing the cost of the receiver, or increasing the AGC range of the analog portion of the radius, which is very difficult and quite expensive. It is therefore an object of the present invention to provide a novel AGC circuit and P1327 / 96 MX that incorporates the desired characteristics mentioned above, and where, as described below, other advantages are also obtained in relation to conventional AGC techniques.

SUMMARY OF THE INVENTION The present invention is an apparatus and method of automatic gain control, novel, for "" "Controlling the signal strength of a received RF signal over a wide dynamic range In a prefe implementation, the automatic gain control apparatus can be adjusted to provide a desired control response to different fading characteristics of the received RF signal In applications where the signal of interest is either a broadband signal, for example a CDMA signal containing digital information, or a narrowband signal, for example an FM signal containing analog information, the The apparatus of the present invention is capable of providing the necessary gain control In accordance with the present invention an automatic gain controller (AGC) for a dual-mode receiver is disclosed.The AGC apparatus includes an adjustable gain amplifier having a input gate to receive an input signal, a control gate for P1327 / 96 MX ', x \ cibir a gain control signal and an output port to receive an output signal. The AGC apparatus further comprises means for generating a received power signal based on the power of the output signal. A saturation integrator compares the received power signal with a reference signal and produces the gain control signal by integrating or restricting the integration based on the values of the received power signal, the reference signal, and the control signals of the receiver. gain.

BRIEF DESCRIPTION OF THE DRAWINGS The particularities, objects and advantages of the invention will become more evident from the following description that is established below and in relation to the accompanying drawings, in which the identical reference numbers identify in a coponding equal parts throughout all the drawings, wherein: Figure 1 illustrates a block diagram of an exemplary application of the automatic gain control apparatus (AGC) of the present invention; Figure 2 illustrates in an illustrative manner the gain of an AGC amplifier as a function of the gain control voltage, - Figure 3 shows an exemplary embodiment of the P1327 / 96 MX "automatic gain control" of the present invention, which includes a control loop implemented in an analog form; Figures 4A and 4B illustratively depict the power and voltage transfer characteristics, respectively, associated with an implementation of a signal limiter included within the gain control apparatus of the invention. "* • Figure 5 illustrates an exemplary implementation of the decision logic that is used to govern the operation of an integration control switch; Figures 6A to 6C are timing diagrams illustrating the operation of the AGC apparatus of the invention; Figure 7 shows a prefe embodiment of the AGC apparatus of the invention that includes a digital embodiment of the control loop; and Figure 8 illustrates an exemplary implementation of a digital saturation accumulator included within the integrator of Figure 7.

DETAILED DESCRIPTION OF THE PREFE MODALITIES In a digital receiver, such as that used in a portable, code division multiple access (CDMA) cellular communications device, it is necessary to P1327 / 96 MX - Adjust the power of the processed signal to a constant level. In a cellular environment, a receiver can receive a signal that experiences rapid and wide variations in signal strength. In order to properly process the digital data contained within the received signal, the signal strength must be controlled inside the receiver. In a dual mode digital receiver, for example, a digital receiver capable of processing both CDMA signals and standard FM signals, the dynamic range of the received signal will vary as a function of the selected operating mode. Accordingly, the automatic gain control apparatus for a digital receiver that is revealed is capable, in each of the operating modes, of compenng for the variation in the power of the received signal, in any environment. Figure 1 illustrates a block diagram of an exemplary application of the automatic gain control apparatus of the present invention. In Figure 1, the automatic gain control apparatus is implemented in the transceiver of a portable cell phone 10 CDMA. The telephone 10 can be dual mode, ie compatible with CDMA and with conventional FM. The automatic gain control apparatus of the present invention is capable of providing power control of broadband CDMA signals and narrowband FM signals. The P1327 / 96 MX r- "^ patibility of this circuitry to operate on the two broadband and narrowband signals, provides cost, component and energy savings for the receiver.The telephone 10 includes the antenna 12 to receive RF signals , including CDMA or FM communication signals, transmitted from a base station Antenna 12 couples the received signals to the duplexer 14 that provides the received signals to the receiving portion of the telephone 10.

* ** Duplexer 14 also receives CDMA or FM communication signals from a transmitter portion of telephone 10 to couple them to antenna 12 and transmit them to a base station. The received signals are output from the duplexer 14 to the downconverter 16, where the RF signals are decreased in frequency and are provided as corresponding intermediate frequency (IF) signals. The IF signals output from the down converter 16 are provided to the gain amplifier 18 IF. The IF signals are amplified at a gain level determined by an AGC signal (VAGC) which is also provided to the amplifier 18. The amplifier 18 is capable of providing linear gain control in a high dynamic range, for example greater than 8. dB, based on a VAGC. The amplifier 18 can also be of the design described, P1327 / 96 MX '' temple, in the patent of the United States of America No. 5,099,204 entitled "LINEAR GAIN CONTROL AMPLIFIER" and assigned to the same assignee of this invention. In the aforementioned United States Patent No. 5,099,204, a compensation circuit is employed to achieve a desired dynamic range of linear control. In particular implementations, this control can be provided by the circuit of '"amplification in the absence of the assistance of a compensation circuit, such implementations include, for example, those in which the various stages of amplification are arranged in cascade, Similarly, the availability of a high-voltage power source can eliminate the need for a compensation circuit.The IF signals controlled in gain are , emitted from the amplifier 18 to a second converter for frequency reduction, down converter 20, wherein the IF signals are converted to a lower sequence range and are provided as signals of corresponding quadrature baseband IBB and QBB . In the embodiment shown in Figure 1, the baseband signals in the CDMA mode of operation are the I and Q samples of the encoded digital data that are issued for demodulation and additional phase correlation. In a mode receiver P1327 / 96 MX 1, the downconverter 20 also converts the FM signals into a lower frequency in order to provide baseband FM and phase quadrature FM signals, which are additionally demodulated in phase / frequency forming an audio output signal . The detector 25 measures the intensity of the signals emitted by the down converter 20 and generates a signal of indication of received signal strength (RSSI) '' .responding. The RSSI signal, together with an AGC reference signal (AGC_REF) supplied by a controller (not shown) is provided to a saturation integrator network 22. The AGC_REF signal corresponds to a desired signal intensity level for the band signals base. The controller also provides lower reference signals AGC limit (AGC_L0W) and upper limit _AGC (AGC_HIGH) to the saturation integrator 22. The signals AGC_HIGH and AGC_L0W correspond to limits on the magnitude of a gain control signal (VAG) provided to a control port of the amplifier 18 by the saturation integrator 22. FIG. 2 illustrates illustratively the gain of the amplifier 18 as a function of the voltage of the amplifier. gain control. Referring to Figure 2, it is noted that the gain of the amplifier 18 is normally narrowed in a non-linear manner to relatively P1327 / 96 MX racks for control voltages that exceed AGC_HIGH and lower than AGC_LOW. In general, it is desired to restrict the value of VAGC within the linear range between AGC_HIGH and AGC_LOW, so that the corresponding time constant of the control loop is within an acceptable range. Deviations from the loop time constant with respect to the acceptable range could result in significant loop control errors. In accordance with the invention, the amplifier 18 is restricted to operating within a linear gain region by the saturation integrator 22, in order to avoid degtion in performance, introduced by these control errors in the loop. As described below, the saturation integrator 22 functions to integrate the difference between the RSSI and AGC_REF signals, when VAGC is between AGC_HIGH and AGC_L0W. When the saturation integrator 22 is not performing an integration operation, the gain control signal VAGG is kept constant either at AGC_HIGH or AGC_LOW, thus improving the response of the control loop, as described above. In a preferred embodiment of the invention, the decision logic within the saturation integrator 22 considers the value of RSSI and AGC_REF, in conjunction with the magnitude of VAG with respect to AGC_HIGH and AGC_LOW.

P1327 / 96 MX Referring again to Figure 1, the saturation integrator 22 receives the RSSI signal coming from the receiver 25, together with the AGC_REF signal coming from the controller. In order to provide precise power control, it is generally necessary that the difference between the RSSI signal and the AGC_REF signal be minimized. The saturation integrator 22 is used to provide this function in the AGC loop. Diverging the difference to 0. For example, if the signal gain is too high, the RSSI signal will also be high compared to AGC_REF. Until these signals are of equivalent magnitude, the output signal VAGC of the integrator will continue to decrease the gain of the amplifier 18. It should be understood that the RSSI measurement can be made at various points in the processing of the received signal. Although Figure 1 illustrates that the measurement is made after conversion for the decrease of the frequency in the down converter 20, the measurement can be made at any point in the signal processing chain after the IF amplifier 18. The RSSI measurement of preference will be made subsequent to the termination of the signal filtering, thus minimizing the parasitic interference power measured. By using analog power control techniques, both P1327 / 96 MX i ^ broadband signals as for narrow band signals, the same power control circuitry can be used in both modes of operation. In relation to a transmitting portion 30 of the portable telephone of Figure 1, the transmit power is also controlled. The VAG signal is used again to provide instantaneous control of the transmission power in the CDMA mode. The signal VAGG is provided to the transmitting portion 30 along with several other control signals that come from the controller (not shown). Referring now to Figure 3, an exemplary embodiment of the automatic gain control apparatus of the invention is shown, which includes a partially analog implementation of the maturation integrator 22. In Figure 3, the saturation integrator includes an amplifier integrator 40 operational (op amp) that has a feedback network configured so that the integrator 40 functions as an integrator. In particular, the integrator 40 receives the signal AGC_REF through the recorder 42, and its non-inverting input, to which the capacitor 43 also connects. When the switch 44 is closed in response to the control information provided by the logic of decision 46 of the integrator, an RSSI signal is issued by the RSSI detector P1327 / 96 MX jW, and is received by the integrator 40 through the receiver 50. When the switch 44 is held in an open position in response to the control information that comes from the decision logic 46 of the integrator, a capacitor 52 it serves to maintain the output (VAGC) of the integrator 40, relatively constant in either AGC_HIGH or AGC_L0W. This prevents saturation of the amplifier 18 when the magnitude of the IF input signal departs from? Ia. predefined dynamic range. Referring again to Figure 3, a mode of a switching or interruption arrangement is shown, which uses the RF switches 49 and 55. The RF switches 49 and 55 couple the IFC bandpass filter 51 to the IF amplifier 18 during CDMA mode, as shown by the setting of the switches in - Figure 3. In the FM mode, the position of the RF switches 49 and 55 changes to couple the filter 53 of the IF bandpass FM and the limiter 54 to the amplifier IF 18. The IF bandpass filter FM 53, to reject interference outside the channel, defines the bandwidth of the FM signals provided through the limiter 54 to the amplifier 18. For example, in FM mode operation , the IF FM 53 filter is designed to have a passband that expands in approximately one cellular channel (eg 30 kHz) and a stop band that extends P1327 / 96 MX * significantly beyond (eg +/- 60 kHz) of the IF center sequence. During CDMA mode operation the IF CDMA filter 51 is designed to reject interference out of channel and defines the bandwidth of the < CDMA signals provided to the amplifier 18. For example during the CDMA mode, the IF CDMA bandpass filter 51 can provide a passband commensurate with the chip rate of the baseband portion of the. ceptor (for example 1.26 Mhz) and provide a predefined rejection bandwidth (for example 1.8 Mhz). In an alternative embodiment, the limiter 54 could be in the common path before the IF amplifier 18. The indicator 54 attenuates the high power RF signals, which are mainly received during the operation of the FM mode. FM signals can exceed the maximum power of the signals found during operation in CDMA mode. In a preferred embodiment, the limiter 54 limits the input power to the amplifier 18 to be within the dynamic range, for example, 80 dB, characteristic of the CDMA operation. The limiter 54 allows the control range of the automatic gain control loop (AGC) of Figure 3 to be designed based on the expected CDMA dynamic range, thus eliminating the need to provide separately calibrated AGC control loops for the operation of FM and CDMA mode.

P1327 / 96 MX Figures 4A and 4B depict illustratively the voltage and power transfer characteristics, respectively, associated with an exemplary implementation of the manager 54. Referring to Figures 4A and 4B, the limiter 54 does not attenuate the signals that they have voltage magnitudes less than a predefined maximum voltage Vm. The saturated power can be quantified as PgAt = Vm / 2RL, where R denotes the "• 'input load impedance of the amplifier 18. For input powers higher than PSAT» the power of the output signal produced by the indicator 54 is it remains constant at approximately PSAT by disengaging the peak signal voltage towards the voltage Vm. The PSAT value will be selected based on the maximum expected CDMA input power level. Accordingly, the high power sinusoidal IF input signals (Pin > P = AT) > The output waveform produced by the limiter 54 is truncated to a fixed amplitude but has a fundamental frequency identical to the sequence of the IF input frequency and the phase information originally inherent in it is restored by the low pass filtering performed by the low pass filter 56. The low pass filter 56, included within the down converter 20, is designed to have a P1327 / 96 MX cutting frequency greater than the frequency of the IF signal emitted by the amplifier 18 in any of the CDMA or FM modes. As mentioned before, the low pass filter 56 is designed to attenuate harmonics of the IF signal emitted by the amplifier 18 prior to the frequency reduction conversion to the baseband components in phase (I) and quadrature phase (Q ). The high power waveforms decrested by the limiter 54 create undesirable harmonics. The low pass filter IF 56 removes the unwanted harmonics so that they do not become a baseband together with the desired IF signal information. In an exemplary embodiment the type, order and bandpass edge of the filter 56 are selected to attenuate the baseband distortion products arising from the IF harmonics inherent in the amplified IF signal produced by the amplifier 18. The filtered IF signal is provided to a first input of a mixer 60, while the other input of mixer 60 receives a locally generated reference signal from oscillator 64. Mixer 60 mixes the filtered IF signal with the reference signal to produce the band components base I and Q on the output lines 70 and 72, respectively. The mixer 60 is designed to map a frequency that is deviated from the central IF sequence by a predefined margin, i.e.

P1327 / 96 MX 3e between 3 to 300 Hz, towards the baseband DC frequency. This DC offset range allows the automatic gain control loop of Figure 3 to distinguish between an unmodulated FM signal (i.e., a continuous wave (CW) signal from an input DC bypass error.) Specifically, the mixer 60 preferably will operate to produce an output sequence of approximately 100 Hz in response to an input CW signal in the middle band IF sequence In this way the input DC offset errors which tend to corrupt the RSSI power measurements are they are removed by a DC notch filter 66 without attenuating the CW signal information. Referring again to Figure 3, the output lines 70 and 72 are respectively connected to the low-pass filter networks I76 and 78. The filter networks 76 and 78 preferably each will be implemented in order to provide the low pass filter transfer functions that exhibit cutoff frequency of 13 kHz and 630 kHz, respectively. During the operation of FM and CDMA mode. In filters 76 and 78 of the exemplary mode, each includes a pair of filters, one of which is used during operation of the CDMA mode and the other during operation of the FM mode. The individual filters included within networks 76 and 78 are switched to the band I and Q signal paths P1327 / 96 MX Dase, respectively, according to the selected mode of operation. In the preferred embodiment, the system controller includes means for switching the included filters within the filter networks according to the selected operating mode. After filtering by the baseband filter networks 76 and 78 and by the notch filter DC 76, the resulting baseband I and Q signals are provided to the RSSI detector 48 the RSSI detector 48 provides an output RSSI signal indicative of the measured signal power (in dB). The difference is that the RSSI signal output by the RSSI receiver 48 and AGC_REF is integrated into the saturation integrator 22 in order to produce the control voltage VAGC. Referring again to Figure 3, the I and Q outputs of the baseband filter networks 76 and 78 are also provided to the analog to digital converters I and Q, (A / D) 86 and 88, respectively. The A / D converters 86 and 88 operate to quantize the baseband I and Q signals for digital demodulation in the selected operating mode, i.e. either CDMA or FM. In the preferred embodiment, the dynamic range of the A / D converters 86 and 88 is selected to be sufficient to adjust the signals that exceed the control range of the AGC apparatus of the IF amplifier 18. As shown in FIG.

P1327 / 96 MX noted above in relation to Figures 2 and 3, the decision logic 46 within the saturation integrator 22 restricts the control voltage VAGC within the range of AGC_LOW < VAGC < AGC_HIGH. This prevents the amplifier 18 from saturating in a non-linear operating region. Consistently, A / D converters 86 and 88 are designed to quantize the input signals, without distortion, regardless of whether the integrator 40 is saturated.

'* The preferred mode, each of the A / D converters 86 and 88 provide 6 to 8 bits of the dynamic range. The dynamic range is sufficient to not provide degradation in the signal to noise ratio of the input to the converters 86 and 88, compared to the signal-to-noise ratio of the quantized digital output of the 86 and 88 converters for any RF input level . For example, when VAGC reaches AGC_LOW and the input signal continues to increase, limiter 54 restricts the attitude of the IF signal. In this way, the input signal level of the A / D converters 86 and 88 can yield to the level indicated by AGC_REF, only for a fixed amount.

Therefore, the A / D converters 86 and 88 will continue to accurately quantify the baseband signals at the increased level. Similarly, the dynamic range of A / D converters 86 and 88 is sufficient to avoid P1327 / 96 MX ^ provide degradation of the signal-to-noise ratio at low levels of RF input signal. For example, when VAGC reaches AGCJHIGH and switch 44 is opened, if the input RF signal continues to fall, the baseband signal level at the input of A / D converters 86 and 88 falls below the level indicated by AGC_REF . The decreased level of the input to the A / D converters 86 and 88 does not use the full dynamic range of the device, that is, some of the output bits of the A / D converters 86 and 88 are not used. 6X decreased use of full dynamic range of converters A / D 86 and 88 inherently degrade the noise figures of A / D converters 86 and 88, compared to the use of full dynamic range. However, the signal to noise ratio of the input to the converters _t_ A / D 86 and 88 also falls because the RF signal level approaches the background of the phone's thermal noise.

Due to the low signal-to-noise ratios of the input to A / D converters 86 and 88, the signal to noise ratio of the output to A / D converters 86 and 88 is not effected by the noise figure of the converters. A / D 86 and 88. Therefore, the signal to noise ratio of the output of the A / D converters 86 and 88 is not significantly affected by the decreased use of the full dynamic range of the A / D converters 86 and 88.

P1327 / 96 MX < ^ _. In this form, the AGC apparatus of the invention enables a limited-range AGC control loop to be used in demodulating the signals that expand in a dynamic range substantially larger than the control range of the IF amplifier. 5 illustrates an exemplary implementation of the operational decision logic 46 for controlling the position of the switch 44. As shown in the Figure . the signals AGC_HIGH and VGG are presented to the logic comparator 104. When VAG exceeds the AGCJEIGH level, the output of the comparator 104 becomes a logical level one (1) (1). The output of the comparator 104 is passed through a logic AND gate with the output of the jogger 110, which is at a logical level 1 due to the closed position of the switch 44. The output of the pump 110 is retarded through of the delay element 114 to prevent effective parasitic switching of the position of the switch 44. The gate Y (AND) 108 and the delay element 114 operate to prevent the switch 44 from being opened until after a fixed period of time that follows its closure. The output of gate Y (AND) 108 undergoes a transition from low to high thus restoring the output of jogger 110 to a level of logical 0 and producing a level of logical 0, and the output of gate Y (AND) 130 and the switch P1327 / 96 MX K ^ Srtura 44. When the switch 44 is opened, the RSSI signal and the AGCJEF signal are no longer forced to go through the loop to be equivalent. In the case where AGC_HIGH has been exceeded and the loop is opened, the RSSI signal indicates a smaller signal to AGC_REF and the output of the logic comparator 102 becomes a logical level 0. When the RSSI signal exceeds the level of AGC_REF, the output of the comparator 102 is transitioned to high and the output of the AND gate (AND) 106 is also transitioned to high, thus adjusting the output of the jogger 110 to the level of logic 1 and closing the switch 44. The delay element 112 and the gate Y (AND) 106 function similarly to delay 114 and the gate Y (AND) 108, and prevent the closure of the switch 44 until it has been opened for a period of predefined time An analogous sequence of logic operations is executed when the level of the RF input signal exceeds the AGC range. When VAGC falls below the AGC_LOW level, the output of comparator 118 becomes a logic level 1. The output of the comparator 118 is passed through the logic gate AND (AND) together with the output of the jogger 124, which is at a level of a logical 1, when the switch 44 closes. The output of gate Y (AND) 122 then transitions from low to high, thus restoring the output of jogger 124 to level 0 P1327 / 96 MX. This causes a logic level 0 to appear at the gate (Y) AND 130 output, which results in the opening of the switch 44. When the switch 44 is opened, the RSSI signal is no longer forced by the loop to be equal to AGC_REF. When the loop is opening in this way, the RSSI signal will be greater than AGC_REF and the output of the logic comparator 116 will be at a logical level 0. When the RSSI signal becomes smaller AGC_REF, the outputs of the stacker 116 and the gate Y (AND) 120 transition to high. The transition adjusts the output of the jogger 124 to logic level 1 and closes the switch 44. The delay elements 126 and 128 and the AND gates (AND) 120 and 122 operate in a manner similar to delay 114 and gate Y (AND) 108 , and serve to prevent rapid switching of the switch 44 between the open, .. and closed positions. The logic output of gate Y (AND) 130 can be considered a trained integration signal and printed on an interruption control line 124 connected to switch 44. In the preferred embodiment switch 44 closes in response to the printing of a 1 logic on the control line 124, and it is opened when a logical 0 is printed on it. The decision logic 46 of the integrator is controlled in this way when the difference between the RSSI and AGCJREF signals are P1327 / 96 MX J ^ degrades by the operational amplifier integrator 40. In this form the decision logic 46 of the integrator and the integrator 40 cooperate to provide the VAGC. The operation of the AGC apparatus of Figure 3 can be described in greater detail in relation to the timing diagrams of Figures 6A-6C. In particular, Figures 6A and 6B illustrate, respectively, the time variation in the power of an exemplary RF signal and the corresponding (open or closed) date of the switch 44 within the saturation integrator 22. Figure 6C shows the value corresponding to the gain control voltage (VAGC) generated by the integrator of the operational amplifier 40 in response to the RF input signal of FIGS. 6A. As indicated by Figures 6A and 6C, on a - first integration interval (trj <t < t?) the power of the RF input signal is confined to the control interval AGC of the AGC loop, and consequently AGC_LOW < VAGC < AGC_HIGH (Figure 6C). At time t = t1 # the decision logic of the integrator 46 determines that VAGC has reached AGC_LOW, and consequently opens the switch 44. The switch 44 remains open over the time interval t! < t < t2, during which the time integrator 40 prevents the difference between RSSI and AGC_REF from being integrated. During this time the input of A / D converters 86 and 88 is restricted P1327 / 96 MX the RF input signal power becomes, once again, less than the upper bounce of the loop control range, which results in the switch 44 being closed by the decision logic 46 of the integrator and VAGC exceeds AGC_LOW. The switch 44 is then closed in a second integration interval (t2 <t <t3) until the control voltage VAG reaches AGC_HIGH, at which time the titerer 44 will be replaced by the division logic 46 of the integrator . During this time the input of A / D converters 86 and 88 varies in response to changes to the RF input signal level. In a similar way the switch 44 is closed by the division logic 46 of the integrator at times t4, tg and te in order to start the third, fourth and fifth integration intervals. Referring now to Figure 7, a preferred embodiment of the AGC loop of the invention is shown wherein a digital embodiment of the saturation integrator 22 is included. In the embodiment of Figure 7, the digital high pass filter 150, instead of the analog DC notch filter 66, is used to remove the inherent DC deviation in the baseband I and Q samples produced by the A / D converters 86 and 88. The cutoff frequency of the filter 150 is selected to make substantially less than the frequency deviation P1327 / 96 MX 'produced inside the mixer 60. An alternate implementation of the DC deviation withdrawal can be achieved by the following: (i) separately determining the averages of the baseband I and Q signal samples, - and (ii) subtracting the resulting DC component of each I and Q component before further processing. The digital RSSI detector 154 will typically include **? query box containing logarithmic power values injected as a function of the magnitudes of baseband I and Q samples. The digital RSSI detector 154 approximates the logarithmic power, ie 10 LO (I 2 + Q2), determining the value of LOG (MAX { ABS (I), ABS (Q).}.) And the value of a correction term. The MAX operation. { ABS (I), ABS (Q)} ) produces an output value equivalent to the magnitude of the largest component of a given I / Q sample pair. In a particular implementation this output value serves as an index in a query box of the logarithmic power. The output derived from the query table is then added to a correction term approximately equivalent to the difference between LOG (I2 + Q2), and LOG (MAX { ABS (I), ABS (Q).}.). The received power estimate, ie the RSSI signal produced by the RSSI detector 154 is supplied P1327 / 96 MX, i digital subtractor 158 together with the signal AGC_REF. The resulting error signal is then scaled according to a desired loop time constant t¿ by the digital scaling multiplier 162. The loop time constant t¿ is selected according to the expected fading characteristics of the input signal RF The time constraints of the relatively short loop (fastest loop response) will generally be selected to enable tracking of signals exhibiting abrupt fading characteristics. In a preferred embodiment the scaler multiplier 162 can be programmed to multiply the error signal of the subtractor 158 by a first loop time constant in response to the decay RSSI signals, and multiply by a second loop time constant when the value of the RSSI signal is increasing. This allows greater flexibility in the design of the AGC loop response based on the fading characteristics of the operational environment and decreases the over-elongation of the loop. Referring again to Figure 7, the scaled error signal generated by the scaler multiplier 162 is provided to saturate the accumulator 166. The saturation accumulator 166 operates to P1327 / 96 MX - accumulate values of the scaled error signal in an aggregate error signal until the aggregate error signal reaches either AGC_HIGH or AGC_LOW. The value of the aggregate error signal is then maintained at AGC_HIGH or AGC_LOW until the scaled error signal is received, and after being combined with the existing aggregate error signal, results in an aggregate error signal within the range defined by AGC_HIGH or AGC_LOW. - Figure 8 illustrates an exemplary implementation of saturation accumulator 166. As indicated in Figure 8, the scaled error signal that provides a first input of a digital adder 170. The scaled error signal is added within the digital adder 170 to the aggregate error signal produced by the unsaturation accumulator 166, where the aggregate error signal is stored in the first register 174. The value of AGC_HIGH and AGCJLOW provided by the system controller (not shown) is stored within the second recorder 178. The signal demisters, minimum and maximum, 182 and 184, coupled to the second register 178, restrict the value of the digital signal provided to the first register 174 within the range defined by AGC_HIGH and AGC_LOW. The digital implementation of the high-pass filter 150, and the RSSI 154 detector and the saturation integrator P1327 / 96 MX 9 illustrated in Figures 7 and 8, offer several advantages relative to the corresponding analog embodiments. For example, the digital components used therein are not susceptible to displacement by temperature and allow the integration time constant to be adjusted in accordance with the expected signal fading conditions in order to facilitate the acquisition of the loop signal. In addition, the filter- • tegrator implemented in the digital form occupies a significantly smaller volume than a corresponding array of discrete capacitive and restrictive components. It is also anticipated that the use of the digital RSSI detector and the digital saturation integrator will result in improved accuracy. In particular, during the period in which the value of VAG is required to be maintained either in AGC_HIGH or AGC_LOW, the capacitive discharge and the like, associated with the analog components, will generally result in the value of VAGC "falling" from the desired level over a period of time. The digital implementation of the unsaturation integrator shown in Figures 7 and 8 does not exhibit the "drop" signal characteristic of the analog integrators. Referring again to Figure 7, the P1327 / 96 The aggregate error MX stored within the recorder 174 of the saturation accumulator 166 is provided to the analog digital converter (DAC) 190. In a preferred mode of DAC 190 resolution it will be sufficient to provide an analog AGC stage size of output less than 1 dB. Alternatively, a pulsed-pulse-modulated (PDM) or pulse-width modulated (PWM) pulse output sequence of logic levels of 0.1 is "routed in response to the aggregate error signal." PDM signaling is explained in U.S. Patent Application No. 08 / 011,618 entitled "Multibit To Single Bit Digital Signal Converter", and assigned to the assignee of the present invention The average value of the output pulse frequency corresponds to the output voltage desired analog output The analog output provided by DAC 190 is passed through the low pass filter 194 before being applied to the gain control port of the IF amplifier 18. The low pass filter 194 is designed to attenuate any parasitic output produced by DAC 190. The prior description of the preferred embodiments is provided to enable any person with ordinary skill in the field to make or use the present invention. different types of these modalities may be evident for P1327 / 96 MX Ruellos with expertise in this field, and the generic principles that are defined here can be applied to other modalities without the use of the inventive faculty. In this way, the present invention is not intended to be limited to the modalities shown here, but is governed by the broader scope consistent with the novel principles and particularities disclosed herein.

P1327 / 96 MX

Claims

~ NOVELTY OF THE INVENTION Having described the present invention, it is considered as a novelty and, therefore, the content of the following CLAIMS is claimed as property; 1. An automatic gain control apparatus comprising an adjustable gain amplifier, the adjustable gain amplifier has a port "^ and input to receive an input signal, a control port for receiving a gain control signal , and an output port for providing an output signal, the automatic gain control apparatus comprises: a means for generating a received power signal based on the power of the output signal, - a saturation integrating means for comparing , in response to an integration capacitor signal, the received power signal to a reference signal and to generate the gain control signal, and a decision means to create the integration capacitor signal in response to the signal value of Gain control, the value of the received power signal and the value of the reference signal 2. The automatic gain control apparatus according to the claim n 1, wherein the signal integration capacitora incapacitates the integrator saturation medium P1327 / 96 MX, the value of the gain control signal remains below a predefined first threshold and when the gain control signal exceeds a second predefined threshold. The automatic gain control apparatus according to claim 2, wherein when the gain control signal remains below the first predefined threshold, the integration training signal incapacitates the saturation integrating means until the value of the signal of received power is less than that of the reference signal. The automatic gain control apparatus according to claim 2, wherein when the gain control signal exceeds the second predefined threshold, the integration training signal incapacitates the saturation integrating means until the value of the power signal received is greater than the reference signal. 5. The automatic gain control apparatus according to claim 1, further comprising an analog-to-digital converter operably coupled to the output port of the adjustable gain amplifier, the analog converter operates in a predefined dynamic range, to generate digital samples of the exit sign. 6. The automatic gain control device P1327 / 96 MX . ' according to claim 1, further comprising: a down converter having an input port connected to the output port of the adjustable gain amplifier for downconverting the frequency of the output signal; a limiting means for restricting the variation of power in the input signal to a dynamic range of input; and an analog-to-digital converter operatively coupled to an output of the down converter, the analog-to-digital converter operates in a predefined dynamic range to generate digital samples of the decreased frequency output signal; wherein when the magnitude of the input signal falls within the dynamic range of input, the corresponding magnitude of the output signal falls within the predefined dynamic range. The automatic gain control apparatus according to claim 1, further comprising means for converting the output signal into a baseband sequence by decreasing the frequency in order to produce a baseband signal, the means for frequency reduction conversion comprises means for defining the frequency at a predefined center frequency of the output signal up to a baseband frequency biased in a P1327 / 96 MX "is the default DC voltage, thus enabling DC deviation errors within the output signal so that they can be distinguished from continuous wave signals within the output signal. gain according to claim 7, wherein the downconversion means comprises a DC sample filter for attenuating the signals having a frequency lower than a baseband frequency, of the baseband signals. 9. A method for automatic gain control using an adjustable gain amplifier, the adjustable gain amplifier has an input port to receive an input signal, a control port to receive a gain control signal and a gain port. output to provide an output signal, the automatic gain control method comprises the steps of: generating a received power signal based on the power of the output signal; integrating, in response to an integration capacitor signal, the difference between the received power signal and a reference signal, and generating the gain control signal; and provide the integration capacitor signal based on the values of the received power, the signal P1327 / 96 MX ^ e reference and the gain control signal. The method of automatic gain control according to claim 9, wherein the step of providing the integrating capacitor signal comprises the steps of: incapacitating the integrating capacitor signal while the value of the gain control signal is less than first predefined threshold; and capacitating the integrating capacitor signal if the value of the received power signal is less than that of the reference signal. The method of automatic gain control according to claim 9, wherein the step of providing the integration training signal comprises the step of: incapacitating the integrating capacitor signal while the value of the gain control signal exceeds one second predefined threshold; and capacitating the integration capacitor signal if the value of the received power signal is greater than that of the reference signal. The method of automatic gain control according to claim 9, further comprising the step of generating digital samples of the output signal so that when the magnitude of the output signal falls within a predefined dynamic range, the digital samples P1327 / 96 MX r * ^ on of magnitudes proportional to the magnitude of the output signal. The method of automatic gain control according to claim 12, further comprising the step of restricting the variation of power in the input signal to a dynamic range of input, thus resulting in restricting the variation of power in the output signal to stay within the predefined dynamic range. The method of automatic gain control according to claim 12, wherein the step of generating the received power signal comprises the step of accumulating the digital samples to produce the received power signal. The method of automatic gain control according to claim 14, wherein the step of integrating comprises the steps of: subtracting the received power signal from the reference signal to provide an error signal; scaling the error signal according to a loop time constant, and accumulating the escalated error signal in response to the integrating capacitor signal. 16. A dual-mode digital receiver for processing signals from CDMA and FM cellular communication systems, the digital receiver has a P1327 / 96 'MX an automatic gain control amplifier comprising an adjustable gain amplifier, wherein the adjustable gain amplifier comprises an input port for receiving an input signal, a control port for receiving a gain control signal , and an output port for providing an output signal, the automatic gain control apparatus comprises: a selection means for selecting a CDMA gain control mode and for selecting an FM gain control mode; first means for filtering the output signal during the selection of the CDMA gain control mode and the second means for filtering the output signal during the selection of the FM gain control mode; means for generating a received power signal based on the power of the output signal, - a means for integrating the received power signal compared to a reference signal and producing the gain control signal, - and a means to enable the medium for integration based on the values of reference signal, received power signal and gain control signal. 17. An automatic gain control device that includes an adjustable gain amplifier, the adjustable gain amplifier has a port of P1327 / 96 MX input to receive an input signal, a control port to receive a gain control signal, and an output port to provide an output signal, the automatic gain control apparatus comprises: a means to generate a signal of power received based on the power of the output signal, - a saturation integrating means for comparing the signal of the received power with the reference signal for generating an error signal in response to a comparison result, the saturation integrating means includes means for providing the gain control signal by accumulating the error signal exclusively on one or more integration intervals, and a decision means for defining the one or more integration intervals based on values of the gain and error control signal. 18. The automatic gain control circuit according to claim 17, wherein the means for generating the received power signal comprises means for accumulating the digital samples in order to produce the received power signal. 19. The automatic gain control apparatus according to claim 18, wherein the saturation integrating means further comprises: means for subtracting the received power signal from the reference signal in order to provide P1327 / 96 MX "* to error signal, a means for scaling the error signal in accordance with a loop time constant, - and a means for accumulating the escalated error signal in response to the integration training signal. An automatic gain control apparatus that includes an adjustable gain amplifier, the adjustable gain amplifier has an input port for receiving an input signal, a control port for receiving a gain control signal, and a output to provide an output signal, the automatic gain control apparatus comprises: a means for generating a received power signal based on the power of the output signal, - and a saturation integrating means for comparing the power signal received with a reference signal and to generate an error signal in response to a result of the comparison, the saturation integrating means includes a means for providing the Gain control signal by selectively integrating the error signal based on the values of error signals and gain control. 21. The automatic gain control apparatus according to claim 20, wherein the saturation integrating means includes first means for capacitating P1327 / 96 MX selectively the error signal to be integrated only while the magnitude of the gain control signal is less than a first predefined threshold, and a second means to selectively train the error signal to be integrated only while that the magnitude of the gain control signal exceeds a second predefined threshold. 22. The automatic gain control circuit according to claim 20, further including an analog-to-digital converter operably coupled to the output port of the adjustable gain amplifier, the analog to digital converter operates in a predefined dynamic range in order to to generate digital samples of the output signal. 23. The automatic gain control circuit according to claim 21, further including: a down converter having an input port connected to the output port of the adjustable gain amplifier for frequency converting the output signal, - a limiting means for restricting the variation of power in the output signal to a dynamic range of input; and an analog-to-digital converter operatively coupled to an output of the down converter, the analog-to-digital converter operates, in a predefined dynamic range, to generate the digital samples P1327 / 96 MX "e the output signal of decreased frequency, where the magnitude of the input signal is within the dynamic range of input and the corresponding magnitude of the output signal is within the predefined dynamic range. of automatic gain control according to claim 22, wherein the saturation integrating means includes: a means for accumulating the digital samples in a digital control signal, and a digital-to-analog converter means for converting the digital control signal into the digital control signal. Gain control signal 25. A method for automatic gain control using an adjustable gain amplifier, the adjustable gain amplifier has an input port to receive an input signal, a control port to receive a control signal of gain, and an output port to provide an output signal, the automatic gain control method comprises the steps of: generating a received power signal based on the power of the output signal, - comparing the received power signal with a reference signal and generating an error signal in P1327 / 96 MX '"Response to a result of the comparison, and provide the gain control signal by selectively integrating the error signal according to the values of the error and gain control signals 26. The automatic control method of gain according to claim 25, wherein the step of providing the gain control signal includes the steps of: integrating the error signal over a first interval only while the magnitude of the gain control signal is less than a predefined first threshold, - integrating the signal of error over a second interval only while the magnitude of the gain control signal exceeds a second predefined threshold. 27. The method of automatic gain control according to claim 25, further including the step of generating digital samples of the output signal, so that when the magnitude of the output signal falls within a predefined range, the digital samples they are of magnitudes proportional to the magnitude of the output signal. 28. The method of automatic gain control according to claim 27, further including the step of restricting the variation in the input signal to a dynamic range of input, thus giving as a result that P1327 / 96 MX "- restricts the variation of power in the output signal to be within a predefined dynamic range 29. The method of automatic gain control according to claim 27, which also includes the steps of: accumulating the samples digital signal in a digital control signal, and converting the digital control signal into a gain control signal 30. The automatic gain control method according to claim 29, further including the step of scaling the digital samples according to the loop time constant, the loop time constant is related to the response of the automatic gain control apparatus to the magnitude variation of the input signal 31. The automatic gain control apparatus according to claim 24 , wherein the saturation integrating means further includes a means for scaling the digital samples according to a loop time constant, the constant of Loop time is related to the response of the automatic gain control apparatus to the variation in magnitude of the input signal. 32. The automatic gain control apparatus according to claim 22, wherein the saturation integrating means includes a means for selectively integrating the P1327 / 96 MX "" Error signal when the magnitude of the gain control signal is between the upper and lower thresholds, the saturation integrating means includes a means to prevent the integration of the error signal in another form, - in wherein the adjustable gain amplifier functions to provide a predetermined range of gain in response to gain control signals having magnitudes between the upper and lower "" thresholds 33. The automatic gain control apparatus according to claim 20, which further includes a means for decreasing the frequency of the output signal at a baseband frequency in order to produce a baseband signal, the means for decreasing the frequency includes a means for decreasing the frequency of a predefined central frequency of the signal output to a baseband frequency deviation in a predetermined range from the baseband DC frequency, whereby the DC deviation errors are capacitated within the output signal to distinguish themselves from the continuous wave signals within the output signal. 34. The automatic gain control apparatus according to claim 33, wherein the means for decreasing the frequency includes a DC sample filter for removing the signals at the baseband DC frequency, P1327 / 96 MX - * ^ e the baseband signals. 35. A dual-mode digital receiver for processing signals from CDMA and FM cellular communication systems, the digital receiver has an automatic gain control device that includes an adjustable gain amplifier, where the gain amplifier is adjustable it includes an input port for receiving an input signal, a control port for receiving a gain control signal, and an output port for providing an output signal, the automatic gain control apparatus comprising: a selection means to select a CDMA gain control mode and to select an FM gain control mode; a first means for filtering the output signal during the selection of the CDMA gain control mode and a second means for filtering the output signal during the selection of the FM gain control mode; means for generating a received power signal based on the power of the output signal; and means for comparing the received power signal with a reference signal and for generating an error signal in response to a comparison result; an integrating saturation medium for P1327 / 96 MX • Provide the gain control signal by selectively integrating the error signal based on the values of the error signals and the gain control signals. 36. An automatic gain control apparatus that includes an adjustable gain amplifier, the adjustable gain amplifier has an input port for receiving an input signal, a control port for receiving a gain control signal, and an --- output port to provide an output signal, the automatic gain control apparatus comprises: a means for generating a received power signal based on the power of the output signal, - a saturation integrator having a first input to receive a reference signal and a second input to which the received power signal is switchably connected, the saturation integrator is positioned to selectively integrate the received power signal in order to generate the control signal of gain within a predefined control range. 37. The automatic gain control circuit according to claim 36, further including an analog-to-digital converter operably coupled to the output port of the adjustable gain amplifier, the analog to digital converter operates over a predefined dynamic range to generate digital samples. of the P1327 / 96 MX '' output signal. 38. The automatic gain control circuit according to claim 37, further including a limiting means for restricting the variation in power of the input signal to a dynamic input range, - where, when the magnitude of the input signal is within the dynamic range of input, the corresponding magnitude of the output signal lies within the predefined dynamic range. 39. A method for automatic gain control using an adjustable gain amplifier, the adjustable gain amplifier has an input port to receive an input signal, a control port to receive a gain control signal, and a port of output to provide an output signal, the method of automatic gain control comprises the steps of: generating a received power signal based on the power of the output signal; selectively integrating the received power signal in order to provide a gain control signal within a predefined control range, wherein the selective integration of the received power signal is made based on the magnitude of the gain control signal and on the magnitude of the received power signal. P1327 / 96 MX