MXPA96004850A - Method and device for controlling a memo - Google Patents

Abstract

The present invention relates to a method and a circuit device intended for insertion of control and storage of digital information (A) in a memory (51) and recovery of memory information. The method and circuit device ensure that the digital information (A ') is read correctly from the memory in the form of a number of coordinate bit positions, and the digital information is used to control one or more functions (f). The information intended to be inserted into a memory that provides an address that belongs to the memory. The first control sum carrier bit positions are calculated (53a) from the bit positions of the digital information and their values reaching the memory in accordance with a selected evaluation function (f (x)). the bit positions of the digital information (A) are stored in an address within the memory (51), and the first bit positions carrying the checksum are stored in a direction within a control memory (55). The second bit positions carrying the checksum are calculated when the bit positions of the digital information stored in the address in the memory (51) are read, according to the second selected evaluation function (62). The bit positions of the reading information and its values are accepting as correct and a circuit (60) is activated through a signal in a conductor (57), if the next comparison (63) between the first and second positions of bit checksum carriers shows that they are identical

Description

r "METHOD AND DEVICE FOR MONITORING A MEMORY" TECHNICAL FIELD The present invention relates mainly to a method for controlling the insertion, storage and retrieval of digital information in a memory so that not only is digital information stored correctly, but also the correct reading 10 of the memory, before reading the information in the form of a number of coordinate bit positions, which is used to control one or more of the different functions. The digital information, inserted into the memory, comprises a selected number of bit positions, of 15 preferably a data packet or a data cell. The number of bit positions is suggested by '-... more specific way that is divided between them and in this way is structured in a selected number of information-carrying bit positions, a number 20 selected from address carrier bit positions and a selected number of bit positions carrying the checksum, wherein the number of bit positions within the different preference categories is selected to vary.

The information related to the bit position that has been read, is able to be used to influence and control the different internal functions of the switch. These functions must be activated and carried out by means of a computer used for these objects. When the checksum carrier bit positions are used, they are capable of representing a selected evaluation of the information carrying bit positions. Means belonging to or preceding a memory are placed to be able to provide a received information, intended to be inserted into the memory, an address belonging to the memory or to evaluate a steerable memory location or positions. The invention comprises secondly a circuit arrangement intended for this control under the aforementioned conditions. The method and the confoarity circuit arrangement with the invention is intended more specifically to control the retrieval of information, coordinated in data packets or data cells, from a memory so that the information read from a memory and that corresponds to a specific address is correct. Within this telecommunication system and switching unit, which pertains to the invention, the required exchange of information is carried out by coordinating the digital information-carrying signals into data packets or standardized data cells, with an address field or related to the address and a field carrying information or related to the content of the information or bit games. Within the related applications, the following description is intended to classify both bit positions within the field related to the address and the field related to the information to understand and be named as bit positions "carriers of information", even though within In these fields, checksum carrier bit assumptions that can be used by the invention must be found.

DESCRIPTION OF THE PREVIOUS TECHNIQUE KNOWN WITH ANTICIPATION Telecommunication systems that use data packets for required exchange of signals are previously known in different designs.

For the exchange of signals required, one of these systems uses a number of bit positions, coordinated in structured sets of bits which in turn are structured and coordinated in the data packets. Within a known ATM system these structured data packets are called "data cells" but then the term "data packets" will be used more generally considering that the invention can be advantageously used within a system of data. ATM. Data packets (data cells) of this class, especially standardized data packets, are characterized in such a way that certain bit positions are coordinated in sets of bits that represent an address field or address-related field (referred to as "Heading") and that include, among other things, a virtual address, also called a channel number. Other bit positions are structured in a set of bits that represent a field carrying information related to the user or related to the information content (designated "Cost-Effective Charge") and which includes the user's data information. It is also known above that, in order to obtain certain hardware functions within a computer unit in an optimal way, only the data packets or data cells usable internally of the switch are used. In addition to the bit positions and bit sets in a normalized data packet, additional structured bit positions are used as a "tag". Label fields or bit positions related to the tag and bit sets can be added to an input data packet, and the tag field is used within a computing unit in order to direct the data packet towards an exit link 10 with the guidance of the bit positions and their digital values. It has also been previously known to use different kinds of memory within a telecommunication system and a switching unit. The memories 15 which store the digital information for a relatively short period of time, is often designated as -? ^ Buffers. It is evident to a person skilled in the art that there is a great need for memories 20 intermediate and queue management of data packets with different bit positions and structures. A first flow of digital information in the form of data packets varies and has a medium flow rate somewhat lower than a second flow of digital information giving 25 understand that a flow of information to a buffer can, over short periods of time, be greater or less than a corresponding flow of the same memory. The average flow toward the memory is selected to be somewhat lower than the average flow out of the memory. Previously, various methods and devices used to ensure that digital information inserted into and stored within a memory are capable of being read correctly from the 10 memory. A well-known method for this object is to let the digital information include structured bit positions with a selected number of information-carrying bit positions, a selected number of 15 address carrier bit positions and / or a selected number of summa carrier bit positions , -Z control. The checksum carrier bit positions represent a selected evaluation of the selected number of information-carrying bit positions 20 through, for example, a calculation or evaluation of parity bits or a "checksum" that is formed through a selected polynomial. The checksum carrying bit positions carry a "checksum" that represents either 25 the parity bits formed or a calculated checksum independently of the selected control method. A parity control and a device for memory related to an integrated circuit are previously known through the publication of European Patent Number EP-A2-0 449 052 which describes a parity control of directional signals. Parity is controlled before a digitized word is stored within a memory. An integrated circuit with a record of 10 input to receive an address bit number, a set of memories for storing the information in a number of steerable storage positions, a control unit for evaluating at least one of the steerable storage positions corresponding to The address bits and a unit to control the parity of the address bits are used for these / "objects." This publication therefore describes a memory circuit within a parity control before 20 that the digitized word be stored in the memory circuit. European Patent Publication Number EP-A1-0 554 964 illustrates a storage and transfer circuit and a method for maintaining the integrity of the 25 data during a storage sequence. A calculation of a first partial control sum from a selected data field within a frame and a unit for storing the control sum are, of course, described. A unit is oriented in a parallel relationship to a serial generation device in order to evaluate a second partial control sum comprising only the data field. A unit compares the first and second partial checksums and the units that can be activated to a comparison change the new checksum calculated as soon as the two partial checksums are not identical, before it completes a serial conversion. The construction of an ATM cell, with cyclic redundancy check (CRC) bits at the end of the cell, is described in European Patent Publication r * - EP-A1-0 531 599. These ATM cells can be advantageously used in accordance with this invention. European Patent Publication Number 20 EP-A1-0 545 575 also presents a data packet with a field that controls the termination of the error. A memory system in which it is possible to evaluate a data error is shown and described in European Patent Publication Number EP-A2-0 084 460.

Address errors are discovered by forming a parity information through the address by inserting it into the control fields that belong to each position of the memory. A signal, indicating the current present state of the function in the memory module, is generated in each memory module and transferred to a data processing system to be compared with a current state of a signal indicating the function to In order to ensure that the memory module and memory control in the process receive the same order. The publication of the American Patent Number US-A-4 872 172 shows a circuit in which a data bus transfers a data word. The data word includes eight bits with data information and one parity bit and is stored within a buffer temporarily before it is transferred to be processed in a logic circuit. Each data word (data bit and parity) that is stored in the buffer register is processed in a parity calculation circuit. A parity control circuit generates a signal that represents a parity error and the parity after the data is not correct. The data word and the parity bit that have been transferred to an output bus are transferred back to another parity control circuit that generates an error signal for the control bus when a parity error is discovered. The IBM Technical Exposure Bulletin, volume 24, number IB, page 794 (June 1981), describes a method for ensuring that the information stored within a memory is capable of being read correctly. A parity bit, which belongs to a data byte, is generated for each data byte or word comprising a number of bit positions. The value of a parity bit is determined by the number of bits with the value "1", both in the data word and in the address value in the address register of the memory. An additional parity bit is generated during the reading of the data word from the memory, and this is 15 calculates taking into account the number of bit positions or the number of a bit both in the reading of the word of 'data as in the initiation of address. This additional parity bit, therefore, is compared to the previously stored parity bit and an error signal is generated if there is a difference. U.S. Patent Publication No. US-A-4 809 278 describes a system for ensuring that information stored in a memory is capable of being read correctly.

Parity bits are generated for each palabara that is stored in a directed position. The number of parity bits may be selected to be the same as the number of input connections of each storage integrated circuit used in a storage structure. A first and a second set of exclusive gate circuits-0 generates a first and second sets of parity data for each read / write cycle that selects the same memory location. A help memory for parity bits receives the first parity data set for storage in positions corresponding to similar positions in each integrated memory circuit so that the same address data reads the first set of parity data bits that correspond to each address in the structured memory. These parity data are the input signals to a second set of exclusive-0 gate circuits intended to form a second set. The American Patent Number Publication US-A-4 692 893 shows and describes a data buffer circuit which is capable of being addressed for reading and writing using an address with n bit positions and with a steerable read register and a steerable write register, presenting both n + 1 bit positions. The extra bit position is used as a parity control. The n + l-th bit in the counters for reading and writing respectively, is used to ensure that the respective counters are placed "at the same time". European Patent Publication Number EP Al 463 210 describes a circuit designed to control the storage in and the address of a memory. At least one write address register and at least one read address register are used. Each of the check bits of the data word is uniquely-0 related to a bit at the address position where the word is to be written before the data word is written into the memory array. The check bits are related to exclusive-0 with the bits of the address position again during the reading of the word in order to regenerate their original values so that the parity of the data word can be controlled.

EXPOSURE OF THE PRESENT INVENTION TECHNICAL PROBLEMS Taking into account the prior art, as described above, it should be considered as a technical problem to be able to obtain the advantages that can be obtained using a method and a circuit device to ensure that the digital information that has been inserted in and stored inside a memory, it reads 10 of the memory before the read information, in the form of a number of coordinate bit positions, is used to control one or more functions. The digital information inserted in the memory must comprise bit positions, structured with a number 15 of information-carg bit positions. A first number of control sum carrier bit positions "'' 'must be calculated from the bit positions of the digital information arriving at the memory and its value (" 1"or" 0") according to a selected evaluation. 20 bit of the digital information must be stored in one direction within a main memory, such as the first bit positions carg the checksum while both the first bit-sum carrier positions and the direction of the Main memory are stored in a direction within a control memory. There is a technical problem in being able to create a method and a circuit device that can reliably assess whether the information (data packet) that is read from a main memory is correct or not, regardless of whether the information whether or not it comprises bit positions carg control sum. There is also a technical problem that when the digital information bit positions stored in the address in the main memory are read, a second number of control sum carrier bit positions is calculated according to the selected evaluation so that the bit positions of the read information and its values are accepted as correct if a next comparison between the first stored in the control memory and the second one formed by the read information of control memory, shows bit positions carg sum of control that are identical. . It is a further technical problem to be able to obtain the advantages that are provided as a corresponding selected evaluation of the information carg bit positions that is carried out while reading information from the main memory to form a selected number of second positions. of checksum carriers and then create the conditions required to compare the first control summary bit positions stored in the control memory, with the second 5-bit checksum carrier positions calculated in this manner, to In order to accept the information read as correct and if there is a match, even when other media are connected indicating a lack of concordance. There is also a technical problem to be able 10 to understand the importance of and the conditions required to be able to accept a reading information as correct, despite indications to the contrary. It must also be considered as a problem 15 technical being able to understand that the selected evaluation comprises either a parity check or '"a check sum formed of a selected polynomial with a higher probability of correct evaluation in the last application 20 It should also be a technical problem to be able to understand the simplified procedure that is provided if the control memory comprises a FIFO memory , or a number of coordinated FIFO memories, or a previously known construction and / or function.

There is also a technical problem in being able to understand that the invention of preference can be used with larger memories, such as FIFO memories connected in parallel or other sets of memories, wherein the means provided to or preceding the memory are capable of classifying each information, destined to be inserted, into one, or several available categories. It should also be considered as a technical problem to be able to understand the advantages with and the possibilities that are created as the bit positions of the digital information and its value are allowed to represent a classification of the information within the data packet. In addition to this, it should be considered as a technical problem to understand the simplification that is obtained due to the circumstances that an address position available in the main memory is evaluated through a means provided to, or preceding the main memory. There is a technical understanding to be able to select the main memory and the control memory so that they are of equal construction, with the position of a data packet, or a part of it, in the main memory and the position of a sum of control, which belongs to the data packet, and the address in the main memory in the control memory, so that it is equal and / or able to be read simultaneously. It should be a technical problem that in addition to this, it is possible to understand the importance of allowing a control memory to comprise a register or a FIFO memory in which the selected information related to the respective digital information structured in a data packet is stored or stored. a data cell, the information selected comprising at least the first bit positions carrying the checksum, and / or the address of the data packet and / or the position in the memory. There is also a technical problem to be able to understand the additional advantages that are obtained as the information related to the classification and / or the order of priority in which within the selected category of the respective data packet is stored in the register or memory of control. There is also a technical problem to be able to understand the importance of, and the advantages that are provided as an information or data packet within a certain category that is read in turn (FIFO) through an adapted reading circuit.

SOLUTION With the intention of solving one or more of the aforementioned technical problems, the present invention is based on a method and a circuit device for controlling that the digital information that is inserted into and stored within the memory is read correctly from the memory, before the read information in the form of a number of coordinate bit positions, is used to control one or more functions. The invention is based on the fact that the digital information, inserted in the memory, comprises selected bit positions and their digital values of "0" or "1". Means are provided to provide the received information intended to be inserted into the memory, an address belonging to the memory. The method and the circuit device according to the present invention carry out a calculation of a first set of bit positions carrying control sum from the bit positions of the digital information coming to the memory, and their values of compliance with a selected evaluation. At least, the bit positions of the digital information and the first bit positions carrying the checksum are stored in a direction within the main memory. The first bit sum carrier positions together with the selected address within the main memory are stored in a direction within a control memory. When the bit positions of the digital information stored in the address in the main memory and which are read by pointing to a selected address in the control memory and reading the digital information stored within the address indicated in the control memory, it is calculated a second set of checksum carrier bit positions based on the read information in the memory 10 principal according to the selected evaluation. The bit positions of the read information and their values are accepted as correct if they are identical one in comparison next between the first bit positions carrying checksum read from the memory of 15 control, and the second bit positions carrying calculated checksum. In accordance with the present invention, the digital information inserted in a memory comprises a selected number of bit positions, preferably a 20 data pack or a data cell. The number of bit positions is divided and structured into a selected number of information carrier bit positions, a selected number of address carrier bit positions, and a selected number of 25 bit positions carrying control sum. The number of bit positions within the different preference categories is variable. The bit position related information that is read is used to influence and control the various flashlight functions of the switch. The functions are activated and carried out by a computer used for these same objects. The checksum carrier bit positions are used to represent a selected evaluation of the information carrying bit positions. The present invention also provides a correspondingly selected evaluation of the information carrying bit positions carried out during the reading of the information from a main memory to form a selected number of second control sum carrier bit positions in order to form a second amount of control. The first control sum carrier bit positions and their values are compared with the second checksum carrier bit positions and their values. The reading information in principle is accepted as correct if there is a match. In accordance with the present invention, the selected evaluation of the selected information carrier bit positions and the control sum comprises a parity check or, as an alternative, a checksum formed of a selected polynomial.

The present invention further provides means for the main memory to be a freely steerable memory, and the control memory can be a FIFO memory or the function of a number of coordinated FIFO memories can be provided thereto. In accordance with the present invention, means are placed which precede or belong to the main memory to provide the received information, intended to be inserted into the memory, an address belonging to the memory or to evaluate a steerable memory position or positions. These means are able to classify the information destined to be inserted in one or more of the available categories. The bit positions of the digital information and their values can represent a classification of the information. The present invention further provides a control memory comprising a register in which the selected information related to the respective data packet such as the first checksum carrying bit positions and the address of the data packet and / or is stored. the position in the main memory. The information related to the classification of the respective data packet is also stored in the control memory.

The information or a data packet, within a certain category, is read in turn through a reading circuit. If there is a match between the first position 5 read from the control memory and the second calculated position of the carrier bit positions, control is added, but there is a lack of a match between the additional bit positions, which belong to the data packet. , the reading information or the data packet 10 are still accepted as correct.

ADVANTAGE The advantages that are mainly provided 15 by the method of the invention and the circuit device according to the present invention, is that the f '^ present has the conditions that have been created, so that, in a simple way, it is controlled that a digital information that is inserted and stored inside a memory The main memory is read correctly from memory, while a control memory is used. The digital information and the number of first bit positions carrying checksum are stored in the main memory and the address in the main memory, and the carrier bit positions 25 checksum are stored in the control memory.

The control is carried out by comparing the value of a first set of control bit sum carrier positions of the information stored within the control memory reading, with the second of the checksum carrier bit positions calculated in the same way of the information-carrying bit positions read from the main memory and that, if there is a match, the reading information is accepted as correct.

The primary characteristic features of a method, in accordance with the present invention, are pointed out in the characterization clauses of claim 1, and the primary characteristic features of a circuit device, in accordance with the present invention, are indicated in the clause of characterization of claim 14. ~ BRIEF DESCRIPTION OF THE DRAWINGS Preferred embodiments of a circuit device and a method in accordance with the present invention will now be described in greater detail and in a few variations with reference to the accompanying drawings, in which: Figure 1 illustrates an intensively simplified telecommunication system, using ATM technology; Figure 2 illustrates a normalized data cell, used in the exchange of signals between a caller and a switching unit; Figure 3 illustrates an intensively schematic receiver circuit for an input data cell related to the caller and normalized to be transformed into a data cell used internally of the switch with a supplementary tag; Figure 4 illustrates more specifically this data cell supplemented with the tag; Figure 5 illustrates a first embodiment of a circuit device according to the present invention, intensively simplified and schematically block; Figure 6 illustrates a second embodiment of a circuit device in accordance with the present invention; intensively simplified and schematically block; Figure 7 illustrates a third embodiment of a circuit device, a classification circuit device in accordance with the present invention; intensively simplified and schematically block; and Figure 8 ilsutra, a fourth embodiment of a circuit device, a classification circuit device, in accordance with the present invention, intensively simplified and schematically block.

DESCRIPTION OF THE PREFERRED MODALITY An intensively simplified telecommunication system known as an ATM system is illustrated with reference to Figure 1. The telecommunication system uses, for its function and signal exchange, the data with the carrier bit positions of 15 information (the positions of the bits in a bit matrix and the logical value of "0" or "1" of the bit) that, like / • ^ bit sets, are coordinated in data packets or "data cells" . For a person skilled in the art, it is It is evident that the exchange of signals can be carried out in both directions but the following description, for the sake of simplicity, will only illustrate the signal exchange connection between a transmitter 3, which belongs to a transmitting terminal 1, and a receiver 3a , that belongs 25 to a receiver terminal 2.

The exchange of signals between terminals 1 and 2 is carried out through the data cells, structured with respect to their bit positions, the logical value of the individual bits, and the selected coordination towards sets of bits, in order that it matches a valid standard protocol for the ATM system. The transmitter 3 has co-operation, through a line or connection 4, with a receiving unit 5 A related to the line that, through a line or 10 connection 6, is connected to an input circuit 7. The input circuit 7 in turn is through a line or connection 8, in co-operation with a number of connection terminals 9 belonging to an ATM selector 10. The ATM selector 10 is equipped with two connection planes 15 redundant or connecting cores 11, 12 which, through circuits not shown, have co-operation with the A ~ _ signal receiving unit 3a and terminal 2. The lines 4, 6 and 8 can be provided from one or several connections or physical conductors. For each ATM selector 10, the required exchange of the information signals is carried out through a number of bit positions. A number of bit positions are structured in the field or bit sets in order to form data cells.

The signal system, according to Figure 1, requires a number of previously known devices and functions, which are not illustrated in Figure 1, in order to function, but these will not be mentioned in addition since it has no influence on the function, or complete understanding of the present invention. However, it will be mentioned that the switch unit 10 comprises a control computer 100. The construction and functions of the control computer 100 are very complicated, and the following description is intended to describe only the parts and functions that are directly related to the understanding of the present invention. Figure 2 illustrates this normalized data cell 20, which may be provided with a five-byte section (8-bit word) or field 21 (Header) comprising address information or carrying bit sets, and a section or field 22 48 byte (eight-bit word) (cost-effective load) comprising the bits sets carrying information. Other information may also be coordinated in this data cell 20. Figure 2 is intended to further illustrate the 20 ', 20 and 20"data cells, which appear in the * conductor 4 in a sequential or serial fashion with a field 22' preceding information carrier of the cell 20 ' of data that follows immediately by the field 21 information-address carrier, and the field or piece 21 carrying information of the next data cell 20 and so on. A receiver circuit 31, which belongs to a switch unit within a telecommunication system, is illustrated in FIG. 3 with a receiver or control circuit 30 which may be included in the input circuit 7 or circuit 9. There may be available 10 several of these circuits. The receiver 31, intended to receive the data cells that appear in sequence, comprises or has coercion in the control circuit 30 that can be considered here as part of the input terminal of the 15 unit 7. The data cells transmitted, in a manner r. normalized, it includes all the information related to a requested connection, when the calling unit 1 initiates a call to the called unit 2, and these are 20 cells or data packets will be designated here as a first category (call category). Each call is provided from one of the different available channel numbers used internally in the switch, through internal switch teams including the 25 control computer 100.

The control computer 100 notifies and simultaneously provides the called person 1 with a channel number that will be valid during the next signal exchange with unit 2 to whom it is assigned. 5 flame. (It may also be the case that the calling unit 1 specifies which channel number will be used in the next exchange of signals). A. The control computer 100 notifies the 10 receiver or control circuit 30 of the channel number that is currently valid for the calling unit 1, and a direction information to the position or positions within a memory 32, where the required information is stored and a selection of a number 15 internal channel, which corresponds to this channel number. The known circuits inside the computer The control 100 is used in a manner known per se in order to select, signal and occupy an available channel through the switch unit 10, with guidance in the 20 information content of the data cell of a first category. These circuits in this exemplifying mode will be illustrated as circuits adapted to evaluate, signal and occupy an internal channel of the switch, taking the information in the field 21 related to the Address, the information within the field 22 related to the information of the data cell 20 of a first category, and the momentary load and number of the channels occupied within the unit of the switch that is being taken into account, and designate this channel to a specific channel number. The control memory 32 is formed such that each selected internal channel number, intended to establish a connection through the switch unit, corresponds to an address position 10 specific. The control computer is positioned so as to be able to adopt fields or bit sets of bit positions, and insert them and store them within the targeted position of the memory 32 corresponding to the 15 internal channel number selected for each call and connectable connection. "_. A field of bit positions corresponds to the channel number selected through the switch unit, a field of bit positions corresponds to the 20 internal functions of the switch, and a field of bit positions corresponds to a specifically calculated checksum, such as parity bits or a checksum, which is calculated according to a selected algorithm or polynomial.

The receiving circuit 31, the receiving data cells 20 from the caller 1, continually evaluates, among other things, the bit positions within the game related to the direction of the bits 5 in the data cell. The circuits are activated to transmit the complete data cell to the control computer 100 to a specifically selected channel number (the channel number of a call) since this channel number refers to a call. An available connection is evaluated, when the control computer 100 receives this call, which is provided with an internal channel number of the switch. Usually, the control computer 100 transmits a message to the caller 1 with the notification that 15 a new channel number must be used for the desired connection and the next signal exchange, whereupon the successive data cells will comprise the new channel number. The new channel number, which is provided to the 20 caller 1 is supplied to the receiving 31 circuits together with information related to the * internal channel number When the cells 2 with the new channel number selected by the control computer 100 are received 25 through one of the receiver circuits 31 intended to receive the data cells, there is a frame available within these circuits indicating the corresponding address position in the control memory 32. * The data cells 20 arriving at the receiver circuit 31, with the new channel number 21, can be used in this way to indicate the correct address or position 32a in the control memory 32 where the selected internal connection of the receiver is stored. switch or the manner of connection, and that will be provided to the data cell 20. A label field 33 comprising the information stored under the address 32a that has been previously created and stored in the control memory 32 by the control computer 100 is added to the data packet 20 and / or the channel number 34 of the switch to replace the old channel number 21 of the data cell 20. With reference to Figure 4, the data cell 200 includes a label field 230 (33), a field 210 related to the address (34), a field 210c of control sum carrier bit positions, such as for a parity control or a checksum that is formed through a polynomial selected for the bit positions within the label field 230 and / or the field 210 related to the address.

There is also a field 220 carrying information and a field 220c representing a set of bits carrying the checksum in the form of a parity check or a checksum that is formed through a selected polynomial. Field 220c may comprise a valid checksum for full data cell 200. The number of the bit positions within the field 220 is usually significantly larger than the number of bit positions within the fields 210 and 230. The checksum field 210c may comprise only the tag field 230, and the field Check sum 220c may only comprise the cost-effective field 220. Depending on several requirements, one or more of the checksum fields or no checksum fields can be used. To simplify the following description, only the checksum field 220c will be described even when in accordance with Figures 6 to 8, the checksum field 210c or the checksum field 220c and the bit set formed within Check sum field 220c provides a valid checksum for the remaining full data cell.

The structuring of the data cell, in accordance with Figure 4, further illustrates that each bit position (its position and its digital or logical value) within the fields 230, 210, 210c, 2.20 and 220c is controlled with the bits 200c of parity related to the byte. The parity bits 200c1 selected so that the field 210 related to the address are selected to have an odd parity while the rest are selected for • 's have an even parity. You can also select other 10 parity distributions. From the following description it will be shown that both the checksum 220c and the parity bits 200c can be used in order to establish and evaluate whether the information read is correct or not, and the selection depends 15 of the application that you have on hand. There is a great need for intermediate or similar memory circuits for the storage of data cells within telecommunication facilities. Various types of structured coordinated bit sets of 20 various ways, such as the data cells' can be controlled in accordance with the present invention. The embodiment according to Figure 5 is intended to illustrate a possibility to establish that a reading data cell is correct and that it matches a stored data cell, without the need for the data cell itself to carry a checksum. For the other embodiments, in accordance with Figures 5 to 8, the interest of simplifying assumes that the data cells, with a label field and a control end set, appear on the conductor 52 in Figure 3 and that these , one by one, they must be stored in a buffer circuit or in a device of *: circuit. With reference to Figure 5, a circuit device 50 in schematic block form is illustrated which is constructed in accordance with the present invention. The circuit device 50 is adapted to ensure that digital information inserted into and stored within 15 of a main memory 51 is read correctly from the memory. The received information destined to be inserted in the memory appears in one of the different available conductors 52. The mode of conformity with Figure 5 can 20 provide storage of any kind of structured bit sets. Figure 5 illustrates a set of bits "A" with a label field 230, a direction field 210 and an information carrier field 100, or at least unused, 25 the bit sets related to the checksum.

A set of bits "B" comprises only one field 220 related to the information or information carrier and a field 210 related to the address. A set of bits "C" is intended to illustrate the insertion of a set of bits 210c related to the checksum that is practically not required in this mode. Figure 5, and also the remaining Figures 6 to 8 present a receiver circuit 53, a memory 61 Main, a control memory 55, a storage circuit 61, a calculation circuit (f (x)) 62, a control unit 56, a comparison unit 63, and an output circuit 60 for the data packets or controlled data cells that are found to be correct.

In accordance with Figure 5, the checksum is calculated in a unit 53a during the reception of the / - * "structured bit set, in accordance with the" A - C "modalities or any other form. The checksum is calculated according to the complete bit set 20 or parts of it with a control or calculation of parity through a selected polynomial. The selection of the calculation method can be carried out in a calculation initiating unit 53b. The calculated control sum is stored in the control memory 55 in a storage position corresponding to the storage position of the selected structured bit set, say "A" in the memory 51. Regarding the reading of the bit set 5 stored "A" 'from the main memory 51 to the storage circuit 61, the bits are transferred to a calculation circuit 62 which calculates a control sum in the same way, through the unit 53b. The previously calculated checksum, stored in the memory 10 55 control, it is read at the same time. The reading set of the bits "A" 'is transmitted to an output circuit 60 if a comparison between these two checksums, in a comparison circuit 63, provides a match. 15 The data cell is discarded when there is no match. z- The first mode illustrated in Figure 5, uses "A" data packets with only information-carrying bit positions (230, 210 and 220) and without positions 20 bits of checksum carriers (200c, 200c 'and 210c according to Figure 4). This modality can also be used with the modalities illustrated in Figures 7 and 8. A second modality in accordance with the Figure 6, uses data packets or data cells with 25 control sum control bit positions according to a previously described embodiment with reference to FIG. 4. In the second embodiment, the bit positions and their logical values of a data cell must be controlled before the data cell or the 5 information 200 ', in the form of a set of coordinated bit positions, read from the main memory 51, in order to control one or more functions (f) that can be activated by a computer unit, such as the unit . and 100 computer. In accordance with the second embodiment, the digital information 200, inserted into the main memory 51, is structured with a selected number of information carrying bit positions, illustrated according to the embodiment of Figure 4 as the positions 15 bits within the fields 230, 210, 210c, 220, and a number of first bit positions carrying sum of ~ "Control within field 220c. The selected number of first control sum carrier 220c bit positions represents a selected evaluation of the 20 past information carrier bit positions and comprises parity bits or a checksum generated by a selected polynomial. The means 51b within the memory 51, or the means 53 that precedes the main memory 51, controllable by 25 a computer unit 51c, are adapted to ./ provide an address belonging to a memory for receiving the information 200, which is intended to be inserted into the main memory 51. This address in the memory 51, in the exemplification mode 5, is illustrated with the designation 51a 'and the field 220c. Field 220 and the remaining fields within data cell 200 are illustrated at position 51a 'of the memory. Field 200c is also inserted into memory 51 at position 51a 'of the memory. The memory 51 is prepared from a FIFO memory with a counter or indicator 51b which is intended to indicate a position 51a 'of available address which is the address position that is intended to store the next data cell. FIFO memory 51 is also equipped 15 with a counter 51d or additional indicator intended to indicate the position of the direction of the positions 200 ' ~ t_ of bit related to the data cell which in turn can be fed out of the memory 51 during an activation signal on the conductor 56a. The address positions between these two indicators can now be obtained to receive bit positions related to the data cell and additional coordinates. A control memory 55 is more or less identical 25 to the FIFO memory 51, and the momentary positions of the two indicators within the main memory 51 correspond to the momentary positions of the two indicators within the control memory 55. These are operating synchronously, always indicating the same address positions within the respective memory. The construction of the control memory 55 is not illustrated since it can be considered as identical to the construction of the memory 51 as previously known. When the data cells (200) include bit positions that represent a checksum (for example 220c), this checksum can be read by a unit 53c. It may be that only the read control sum (220c) is stored within the control memory 55, since all the bit positions of the data cell are stored within the main memory 51. This modality will now be described in greater detail. The first control sum carrier bit positions 220c, through the circuit 53c, are read from the bit positions and their values, from the digital information 200 coming to the main memory 51. The bit positions of the digital information 200 are stored in a direction within the main memory 51. Only the first positions are stored 220c of bit control summoning carriers in a corresponding direction within a control memory 55. The second bit positions 220c 'carrying the checksum are calculated in a calculation unit 62 in accordance with the evaluation of the first positions 220c of checksum carrying bits during a bit position reading of the digital information stored in the address in the main memory 51. The first bit positions 220c that come from the first bit positions 220c previously calculated, stored in the memory 55, are read at the same time. The bit positions, and their values, of the read information 200 'are accepted as correct if a next comparison between the first positions 220c' 'and second bit position positions 220c' of checksum carriers show that they are identical. In a second embodiment, with the data cells comprising the checksum carrier bit positions in accordance with Figure 4, the unit 53c can be positioned to read the sum of control sum carrier bit positions 220c and / or the positions of bit 200c, or alternatively only the bit positions 200c or the bit positions 200c '.

An input data cell 200 in this manner will be completely stored in a position 51a 'of the last memory. At the same time the checksum carrier bit positions such as a check sum that have been pointed out and read are stored only in the register 55 at a corresponding address position. As the indicator moves in the memory 51, the indicator in the memory or register 55 moves in the same manner in order to maintain the positions that correspond to one another. The embodiment according to Figure 6 is intended to illustrate a position where the complete data cell 20 is read at 200 'from the memory 51, from the position 51a and stored in the storage circuit 61 at the same time as a corresponding check sum 220c'1 is read from the corresponding address position in the register 55. An address position is activated in the control memory 55 and the control unit 56 will receive the information related to the value of the positions 220c 'of checksum carrier bits according to a calculation selected in unit 62. A check sum position 220c' 'is stored in register 55 when a control unit 56, through a unit 66 and a driver 58, requires a reading of a data cell from the main memory 51. In this way it is possible, within a third unit 63, to compare the first control carrier bit positions 220c '', stored in the control memory 55, with the second calculated checksum carrier bit positions 220c 'and, within unit 63, decide if there is a match between these bit positions. If there is a match, the reading information 200 'can be accepted as correct, and the information or data cell can be transferred through a driver 57 and a unit 60 to control a function (f) in the switch unit. The evaluation selected within the unit 62 and the formation of the bit positions 220c 'control sum carrier in this unit 62 are carried out by a parity control or alternatively through a check sum formed of a selected polynomial. such as the polynomial? lu + x ^ +? 6 + x5 + x +] _. The checksum carrying bit positions 220c can detect single, double and triple faults with this polynomial. The main memory 51 and the preference control memory 55, in their simplest form according to Figure 6, can be prepared from a single FIFO memory. The modality described with reference to Figure 7 can be considered as a development of the mode of compliance 5 with Figure 6. Figure 7 is intended to illustrate a number of FIFO memories that serve as primary memories 51, 751a, 751b, 751c oriented "parallel" with respect to each other, and each one destined to store the 10 data cells of one and the same category. A corresponding number of control registers or memories 55, 755a, 755b, 755c are for the required purposes, each providing its own category. The main memory 51 corresponds to the control register or memory 55, the memory 751a corresponds to the "^, Register 755a and so on, whereby the corresponding memories and registers are synchronously advanced, always pointing to the same position of 20 address. The embodiment illustrated in Figure 7 of the main memory 51, -751c requires that the means 53, which precedes the memory 51, comprise a unit 65, 65a that classifies the information or a data cell, intended for 25 to be inserted, evaluating the content in field 230 of label (or other fields), in one of the different available categories. The initiation of a reading of a designated memory, for example the memory 751b, is carried out at At the same time as an initiation of a reading from a register or control memory indicated for example, the register 755b, in a manner known per se. The embodiment according to Figure 7 provides a memory 51 (51, 751a, 751b, 751c), wherein 10 the data cell of a category are coordinated in a FIFO memory 51 and the register 55 while the data cells of another category are coordinated in another memory 751a FIFO and register 755a, and so on, so there is a risk of a used memory capacity 15 poorly since only one category selected in the memory can be stored previously , - selected. An embodiment in accordance with Figure 8 is illustrated in order to obtain a used memory capacity 20 better and in order to be able to store data cells of equal or different categories more efficiently. The embodiment according to Figure 8 requires a main memory 51 of a further nature 25 is complicated since the position of a respective data cell is determined unanimously, and any available position can be provided to a data cell. The main memory 51 and the register 55 can be "virtual" FIFO memories or buffer circuits. In this case, the selected information destined for each data cell such as the first bit-sum carrier positions 220c and the selected address 51a and / or the data packet position is stored in a register 55 which serves as a control memory. The register is capable, in addition to this, of storing information related to the category of a respective data packet. A reading of information or a data package , A ~ from the main memory 51 is initiated through a reading circuit, within a sixth unit 66, connected to the control unit 56 through the register 20 55. These data packages are read in turn within a given category. It is assumed that a data cell of a first category will be selected and read through the control unit 56.

The current data packet, sorted in order of priority, is evaluated in this way in the register 55 and the register can indicate the position of the related memory in the memory 51. The instruction of the control unit 56 requires a certain category. The memory 51 in Figure 8 provides storage of the data cell within any number of addresses, and means are therefore required to determine which address positions are available. These available address positions are classified in a so-called "available list". Using data cells 200 with a control 200c of parity, it is possible, even when there is no agreement between the first checksum carrier bit positions 220c stored in the control memory and the second bit positions 220c 'computed checksum carriers, of accepting the information of reading or packet of data as correct if there is a match within the seventh unit 67 between the additional bit positions such as 200c, 200c ', which belong to the data packet. An ATM selector, in accordance with the Figure 1, is a switch for so-called data cells with a fixed length. The ATM selector comprises a selector core (11, 12) and selector terminals (7, 9), a selector terminal for each terminal in the selector core. The selector core is duplicated and comprises two planes or units 11, 12, both constantly and independently active to carry out the same work. The two planes 11, 12 are terminated with redundancy at the output terminals of the selector, implying that one of the two identical data cells of each individual data cell from the two planes of the selector core is discarded. The planes of the selector core are not synchronized and the redundancy temperament is carried out by connection and plane, it is possible that the two data cells are used at the same time, one for each respective plane or both to be transmitted. Because of this, buffers are required at the terminals of the data cell selector that arrive from the two planes of the selector core. The exemplary modalities in accordance with Figures 7 or 8 are intended to illustrate this modality. The placement in the buffer in the selector terminal must be intelligent, that is, capable of keeping several queues in order, one queue for each class of cell category or data cell. One of these category classifications are carried out taking into consideration the priority and type (eg signal cells) of the data cells. This can be implemented with another selector terminal using a single large memory 51, retaining a number of sites for the buffer such as that designated 51a by administering an indicator or a register 55 for these sites in the cell buffer. Figure 4 illustrates a complete data cell 200 equipped with parity bits that advantageously can only be used to control bit errors during cell transmission, in parallel form, between two adjacent hardware functions. The internal memory and the FIFO memories that belong to it, comprise the different queues and can be controlled both for bit errors and address errors since the data cell 200 has the structure illustrated in FIG. 4, by the use of a parity combination and a check sum of the cell in field 220c. The parity control ensures that bit errors have not occurred in any single byte, while field 220c is used to control the different types of address errors in the memories, while possible bit errors can be detected.

The selected queue receives an indicator from the "available list" and the data cell is written to a buffer site indicated by the indicator when the intermediate memory 51 in Figure 8 is used to place a data cell. The shape of the data cell is preserved during writing and comprises sixty bytes, with field 220c at the end. The used indicator is written to the current queue together with the field 220c of the cell during the writing of the cell in the buffer. Field 220c as described above, can be used to detect the various address errors that may occur since the field constitutes a unique identification of the cell. It is known that pure address errors of both the temporary and permanent class can occur, due to different reasons, in the memory areas of the FIFO memories. Field 220c 'is calculated when a data cell of intermediate memory 51 is read. The result of this calculation is compared both with field 220c, which was actually part of the cell, and with the field that was stored in the queue with the indicator inside record 55. It is assumed that the data cell is correct or either read correctly if the newly calculated field 220c is identical to the one already in the data cell and that the logic circuit has performed an appropriate function with the least significant address bits, those used in the address within the data cell. If, in addition to this, the newly calculated field 220c is identical to the field that is stored in the queue together with the flag within the record 55, it is clear that the correct data cell has actually been read implying that the logic and the most significant address bits of those used for the address, have carried out the appropriate function and that the indicator has actually pointed in the right direction. A parity control 200c can be used to investigate whether there is a data error or an error in the register 55 if these measurements show that the newly calculated field 220c ', the field 220c stored within the cell and the field stored with the indicator in the record, they are not identical one with respect to the other. The logic in the control unit 56, which manages the indicators in the queues, is continuously controlled by adding the number of the indicators in the different queues, which must always amount to the total number of buffer sites. When the "available list" is complete, the other queues have to be empty.

These errors can occur, for example, if one of the indicators in the FIFO memories "skips" in a faulty manner, which would alter a complete queue. Of course it is within the scope of the invention to use only the parity control of the bit fields 200c and 200c '. If a modality is selected where both the control sum 220c and the bits 200c, 200c 'of parity and *. Of course, it's going to be used and compared, sometimes it's It is necessary to store both of these in register 55, and compare both of these in different units. It will be noted that the area 35 in the memory 32 can retain the control sum carrier bit positions 210c or the check sum carrier bit positions 220c. Block 62a is used to store the parity bits 200c for a complete ATM cell in order to carry out additional control of the read information if there is a mismatch between the other checksum carrier 20 bit positions as It has been described above. It will be understood that the invention should not be restricted to the illustrated exemplary embodiments thereof and that modifications may be made within the scope of the invention illustrated in the following claims.

Claims (26)

1. CLAIMS: 1. A method for controlling that a digital information is inserted into and stored within a main memory (51) is read correctly (60) from the main memory (51), before the information read, as in the form of a number of coordinated bit positions, is used to control one or several functions (f) also using a control memory (55), whereby the The digital information, inserted in the main memory (51) and the control memory (55), comprises coordinated bit positions, whereby means (53) are placed to provide a received information, destined to be inserted in the main memory ( 51), an address 15 belonging to the main memory whereby the first bit positions carrying control sum f-f, (220c) are calculated from the bit positions of the digital information destined to be stored and their value in accordance with the selected evaluation, by means of the Wherein the bit positions (200) of the digital information and the bit positions • first checksum carriers (220c) are stored in a selected address within. the main memory (51), characterized in that the first bit positions carrying sum of The control (220c) and the address selected in the main memory (51) are stored in a selected address within the control memory (55), which a reading of the bit positions of the digital information, stored in the address in the main memory (51) is carried out by pointing to a corresponding address in the control memory (55) and reading the digital information stored within a designated address in the main memory (51), which corresponds to the address in the memory of control (55), and of the information read from the main memory are the calculated second checksum carrier bit positions (220c ') (62), in accordance with the selected evaluation, and that the bit positions of the information read, and its values, are accepted as correct if after the next comparison between the first bit positions carrying checksum (220c ''), read from the control memory (51), and the second computed sum control carrier bit positions (220c ') shows that they are identical. The method according to claim 1, characterized in that the bit positions of the digital information, destined to be stored in the main memory (51), have been structured as a selected number of first information-carrying bit positions (220 , 230, 210), and a selected number of first control sum carrier bit positions (220c), where the latter represent the selected evaluation of the former. 3. The method according to claim 1 or 2, characterized in that the selected evaluation comprises a parity check. 4. The method according to claim 1, 2 or 3, characterized in that the selected evaluation comprises a checksum formed of 10 a polynomial selecting. The method according to claim 1, characterized in that the main memory and the control memory are produced as the same kind of memory. 6. The method according to claim 1, characterized in that the main memory / »- is selected to be a freely steerable memory while the control memory comprises one or more FIFO memories. 7. The method according to claim 1, characterized in that the means that are provided or precede the main memory classifies each information, destined to be inserted in one or several available categories. 8. The method according to claim 1, characterized in that the information is structured in data packets or data cells. 9. The method according to claim 5, characterized in that the bit positions of the digital information and its value are allowed to represent a classification of the information in a category. The method according to claim 10 or 8, characterized in that the position of the available address in the main memory (51) is evaluated through the means (53) that is provided to or, which precedes the main memory ( 51). 11. The method according to claim 1, 9 or 10, characterized in that the control memory (55) comprises a register wherein the selected "information" related to the respective data packet, such as the carrier bit positions. of the first control sum towards the address of the data packet 20 and / or the position in the main memory (51), is stored and in which the information related to the classification of the respective data packet is also stored in the register. 12. The method according to claim 1, characterized in that each information or A data packet within a certain category, is read in turn through a reading circuit (56). 13. The method according to claim 1, characterized in that if there is a 5 agreement between the first control sum carrier bit positions (220c ''), the reading of the control memory (55), and the second calculated checksum carrier bit positions (220c ') but a match is missing between the other bit positions (220c), 0 that belong to the data packet, the read information or the data packet is still accepted as correct. 14. The circuit device for controlling that digital information that is inserted into and stored within a main memory (51) is capable of being correctly read from the main memory but also using a control memory (55), whereby the means (53) belonging to or preceding the main memory is placed to provide information received or intended to be inserted into the main memory (51), an address belonging to the memory whereby the first positions of bit control-sum carriers (220c) can be calculated from the bit positions of the digital information and its value through a first calculation circuit in accordance with a selected evaluation that the bit positions of the digital information can be stored in an address within the memory main (51) characterized in that the first control sum carrier bit positions (220c) calculated in the selected address (51a ') in the main memory (51) are stored in a selected address within the control memory (55) , that the second sum control carrier bit positions (220c ') are calculated, through a second calculation unit (62) according to the selected evaluation, when the bit positions of the digital information that are stored in the address (51a ') in the main memory (51), have been read, and that the bit positions of the read information and its values (200') are accepted as correct if after u A next comparison between the first (220c) and second (220c) bit positions carrying checksum carried out through the comparison circuit, show that they are identical. The circuit device according to claim 14, characterized in that the bit positions of the digital information intended to be stored are structured in a selected number of first information carrying bit positions and a selected number of first carrying bit positions. of sum of control, where the latter represent a selected evaluation of the former. 16. A circuit device according to claim 14 or 15, characterized in that the 5 evaluation selected within the first calculation circuit or unit, is placed to create a parity check. 17. The circuit device according to claim 14 or 15, characterized in that the evaluation selected within the first calculation circuit or unit is placed to create a check sum formed of a selected polynomial. 18. The circuit device according to claim 14, characterized in that the memory The main memory and / or the control memory comprises one or more FIFO memories. / -_ 19. The circuit device according to claim 14, characterized in that the means that is provided or that precedes the main memory 20 comprises a unit that classifies each information destined to be inserted in one or more of the available categories. 20. The circuit device according to claim 14, characterized in that the information is structured in data packets or data cells. 21. The circuit device according to claim 14, characterized in that the 5 bit positions of the digital information and their values represent a classification of the information in a category. 22. The circuit device according to claim 19 or 21, characterized in that a 10 address position available in the main memory is evaluated through means that are provided towards or preceding the main memory. 23. The circuit device according to claim 14, characterized in that the memory The control comprises a register in which the information selected with respect to the respective data packet such "" - as the first bit positions carrying checksum and the address of the data packet and / or the position in the main memory are stored. 24. The circuit device according to claim 23, characterized in that the information related to the classification of the respective data packet can be stored in the register. 25. The compliance circuit device 25 with claim 14, characterized in that each information or data packet within a certain category can be read in turn through a reading circuit belonging thereto. 26. The circuit device according to claim 14, characterized in that the information read or the data packet is accepted as correct even if there is a mismatch within a unit between additional bit positions belonging to the data packet, there is a match between the first and second bit positions carrying checksum. SUMMARY OF THE INVENTION A method and a circuit device intended for control and storage insertion of the digital information (A) into a memory (51) and retrieval of the memory information. The method and circuit device ensure that the digital information (A ') is read correctly from the memory in the form of a number of coordinate bit positions, and the digital information is used to control one or more functions (f). The information intended to be inserted into a memory that provides an address that belongs to the memory. The first control sum carrier bit positions are calculated (53a) from the bit positions of the digital information and their values reaching the memory according to a selected evaluation function (f (x)). The bit positions of the digital information (A) are stored in an address within the memory (51), and the first bit positions carrying the checksum are stored in a direction within a control memory (55). The second bit positions carrying the checksum are calculated when the bit positions of the digital information stored in the address in the memory (51) are read, according to the second evaluation function selected / • '(62). The bit positions of the reading information and its values are accepting as correct and a circuit (60) is activated through a signal in a conductor (57), if the next comparison (63) between the first and second positions The sum of control checksum carriers shows that they are identical.