MXPA96004558A - Receiver and method for stabilizing a demodulator by increasing a cd recobr pilot component - Google Patents

Abstract

The present invention relates to a dual-mode automatic gain control (ACC) system for a television receiver in which data in the form of symbols occur at a fixed symbol rate. The symbols are sent in successive data segments, each having a synchronization character. The activation of an automatic frequency control (AFC) overcoming signal defines an initial interval during which the intermediate frequency gain (IF) is maximum. When the AFC bypass signal becomes inactive, the receiver is operated in a non-coherent mode in which the gain of the IF amplifier is reduced in an increased manner, provided that the IF signal exceeds a clipping level for a period of eight synchronizations of successive symbol. When a segment synchronization neclavation condition occurs, a normal coherent mode is accessed, where the AGC responds to a signal characteristic, ie data segment synchronization. The rate of change of gain available in the non-coherent AGC mode is much higher than in the consistent AGC norm.

Description

AUTOMATIC FREQUENCY CONTROL LATCH, EXCITED BY DATA SEGMENT FOR ACROPED LOOP IN STABLE BIFASSIC FREQUENCY PHASE This invention relates in general to digital data receivers and particularly refers to a digital television signal receiver. Recently, a number of systems have been proposed to transmit and receive television signals in digital form. The television signal may comprise, for example, a high-definition compressed broadband television (HDTV) signal or one or more compressed signals from the National Television System Committee (NTSC). The two most widely promoted modulation techniques considered to perform these transmissions are quadrature amplitude modulation (QAM) and residual sideband modulation (VSB). The patent of the U.S.A. No. 5,087,975 discloses a VSB system for transmitting a television signal in the form of successive level M symbols on a standard 6 MHz television channel, with a relatively small pilot (low level) at the lower edge of the channel, while the number of levels M (ie the VSB mode) characterizing the symbols may vary, the preferred symbol rate is set such as at a rate of 684 H (approximately 10.76 Mega-symbols / sec), where H is the frequency of NTSC horizontal scan. The REF number: 23072 symbol levels used in any particular situation is substantially a function of the signal to interference ratio (S / N) that characterizes the transmission medium, a smaller number of symbol levels is used in situations where where the S / N ratio is low. A system that allows symbol levels of 24, 16, 8, 4 and 2 is considered to provide adequate flexibility to satisfy most conditions. It will be appreciated that lower values of M can provide improved S / N ratio performance at the cost of reducing the transmission bit rate. For example, when considering a speed of 10.76 Megabytes / sec, a 2-level VSB signal (1 bit per symbol) provides a transmission bit rate of 10.76 Megabits / sec, a 4-level VSB signal (2 bits per second). symbol) provides a transmission bit rate of 21.52 Megabits / sec, and so on. Proper operation of a digital television receiver requires that the received carrier signal be acquired relatively quickly and the gain of the radio frequency (RF) and intermediate frequency (IF) sections adjusted appropriately. The acquisition of carrier in QAM receivers is relatively difficult, due to the absence of any kind of pilot. While the use of a pilot in the aforementioned VSB system greatly facilitates carrier acquisition, however, some difficulties may be encountered due to the relatively low level of the pilot and the limited range of activation of synchronous modulators used in VSB receivers. One aspect of the invention improves the activation of the phase and frequency synchronized loop (FPLL) and another deals with an improved automatic gain control (AGC) system. Also, the FPLL in the synchronous demodulator is stable two-phase. Consequently, the phase of the output data can be inverted and therefore requires to be inverted in phase. Furthermore, the interlocking characteristics of the FPLL are determined by the characteristics of the automatic frequency control filter (AFC) and in another aspect of the invention, an improvement in these characteristics is provided. The present invention is directed to an AFC latch excited by the segment to stabilize the FPLL. It is therefore a basic objective of this invention to provide an improved FPLL in a digital data receiver, which employs a synchronous demodulator that develops a direct current (DC) pilot. Another aspect of this invention is to provide an improved FPLL that is not affected by interference or data breadth. Additional features and advantages of the invention will be apparent upon reading the following description of preferred embodiments of the invention, in conjunction with the drawings, wherein: Figure 1 is a partial block diagram of a receiver constructed to receive an M-level signal VSB; Figure 2 is a larger detail showing the IF amplifier and synchronous demodulator of Figure 1; Figure 3 is the circuit for controlling the AGC for the receiver; Figure 4 illustrates the operational modes of the AGC circuit; Figure 5 describes a data polarity inverter for automatically inverting the data in phase, if required; Figure 6 is an AFC latch excited by segment synchronization according to the invention; and Figures 7.A and 7B are curves illustrating the operation of the filter of Figure 6. As mentioned above, the transmitted VSB signal preferably includes a small pilot at the lower border of the 6 MHz television channel, which it is converted to an intermediate frequency (IF) of about 46.69 MHz near the upper border of the channel. Also, although not limited thereto, the transmitted signal preferably comprises successive data frames, each including 313 data segments. Each data segment includes 832 symbols (occurring at a speed of approximately 10.76 Megabytes / sec.), 828 of which are used for data and 4 of which are provided in a fixed position of each data segment, to define a Segment synchronization character. The data segment synchronization character comprises only 2-level symbols, while the data symbols can be 2, 4, 8, 16 or 24 levels, depending on the application. Also, the first data segment of each frame comprises a 2-level symbol sequence representing a frame synchronization code and a VSB mode control signal that identifies the M level (24, 16, 8, 4 or 2) of the data symbols of the remaining 312 data segments of the table. The pilot can be conveniently developed at the transmitter by entering a displacement (constant CD level) at the symbol values. In the receiver, the displacement generates a constant CD that is used for carrier recovery. In accordance with an aspect of the invention, this "recovered" CD in the receiver is removed from the data channel, after acquisition of the carrier, to optimize further processing. With reference to Figure 1, the received RF signal is converted to an IF signal by a tuner 10, which is controlled by a microprocessor 12. The microprocessor 12 responds to user feeds, either from a keypad 14 or an IR receiver 16 , to apply appropriate signals to the tuner 10, to tune the select channel. The IF signal that includes the pilot at 46.69 MHz, is applied to the tuner 10 through a SAW filter 18, which has a pass band of approximately 41-47 MHz, to an IF amplifier and synchronous demodulator 20. The baseband output The analog of the modulator 20 is coupled by a capacitor 21 to an analog to digital (A / D) converter 22, which samples the signal and provides the level symbol information M in binary form to a digital processor 24. The capacitor 21 eliminates the CD displacement mentioned above of the A / D supply 22. As will be explained in more detail below, A / D 22 is operated to sample the output of the demodulator 20 at the correct symbol times, in response to a clock signal generated by the digital processor 24. The digital processor 24 supplies the data and also supplies an AGC control signal to the IF amplifier and synchronous demodulator 20, which in turn supplies a delayed AGC signal to the tuner. or 10. Both the demodulator 20 and the digital processor 24 respond to an AFC bypass signal generated by the microprocessor 12, in response to selected start conditions, such as energization, channel change and loss of data segment or frame synchronization. . Finally, since the data output phase can be reversed because the FPLL in the synchronous demodulator is stable bi-phasic, an automatic arrangement is also included to provide the appropriate phase of data. This is described more fully in connection with Figure 5. The IF amplifier and synchronous demodulator 20 are illustrated in more detail in Figure 2. The IF signal of the SAW filter 18 is applied through a gain controlled amplifier 30 to a power supply. of an IF switch 32. The gain in the amplifier 30 is regulated by an AGC control and charge pump 31. The circuit 31 responds to gain increase and gain reduction signals, to charge and discharge a capacitor 33 to a desired value , to control the gain of the amplifier 30. The circuit 31 also generates a delayed AGC signal for application to the tuner 10. A crystal oscillator 34 is activated in response to the AFC bypass signal of microprocessor 12, to apply a relatively strong signal to the pilot frequency (46.69 MHz) to a second power supply of the IF switch 32. The IF 32 switch also responds to the AFC Overcoming signal to couple the output d the crystal oscillator 34 to the switching output and otherwise operable to couple the output of the IF 30 amplifier to its output. In this way, the output of the IF switch 32 is the IF signal when the AFC bypass signal is absent, and is the output of the crystal oscillator 34, when the AFC Override signal is present.

The output of the IF switch 32 is applied to the first feeds of a pair of multipliers 40 and 42.

A voltage controlled oscillator (VCO) 44 nominally generates an output at a frequency equal to 4 x pilot frequency (i.e. 186.76 MHz), which is applied to a preset circuit on a divide-by-four scale 46 to produce a pair of signals displaced in phase at 90 ° in the pilot frequency. The in-phase signal (0o) is applied to the second feed of the multiplier 40 to produce a baseband component in phase I and the quadrature signal (90 °) is applied to the second feed of the multiplier 42, to produce a quadrature baseband component Q. The I and Q components are coupled through respective low pass filters 50 and 52 to remove harmonic second and higher order harmonic products and amplified by respective amplifiers 54 and 56, to provide the desired output levels. The amplified I and Q components are supplied to respective feeds of an FPLL 58, which is operated, in a well-known manner, to generate a tuning voltage vt to synchronize the frequency and phase of the signal generated by VCO 44 to 4 times the pilot frequency. The capacitor 21 as mentioned above, prevents the CD shift in the channel I signal that is applied to the A / D 22. In this way, the quadrature signals produced by the divider 46 are synchronized to the pilot IF frequency to demodulate appropriately the received IF signal. During certain types of start conditions, such as during energization or a channel change, the VCO 44 frequency may be so far from its nominal frequency of 186.76 MHz that a fast interlock by the FPLL 58 in response to the relatively small received pilot does not it can happen (FPLL 58 typically has an activation range of only approximately + 100 KHz at the IF frequency with the weak pilot signal, while its activation range with a strong signal is typically around + 750 KHz). To overcome this problem, the relatively strong 46.69 MHz output of the crystal oscillator 34 is applied through the IF switch 32 to the feeds of the multipliers 40 and 42 during an initial interval, which is defined by the duration of the Overcoming signal. AFC, ie the AFC Overcoming signal is activated, instead of the IF signal received from the IF amplifier 30. The initial interval comprises a fixed period (approximately 200 milliseconds (ms) in duration) of maximum gain. It will be appreciated that it takes approximately 1 ms to bring the gain to the maximum-this is considered part of the initial interval. During the initial interval corresponding to the duration of the AFC bypass signal, the gain of the IF amplifier is maintained at its maximum level, regardless of the current level of the IF signal. In this way during the interval, the AGC system is transferred. A relatively strong signal, at the frequency of the IF pilot, is applied to the synchronous demodulator from the crystal oscillator 34, during the initial interval, to allow the FPLL 58 to rapidly bring the VCO frequency 44 to its nominal value. After the initial interval, as determined by the absence of the channel data signal, a maximum value or clipping level is continuously compared by a comparator 72. If the absolute value of the received data signal exceeds the clipping level by eight consecutive symbols, the decoder 68 generates a decoder that outputs 70 to generate a gain reduction signal to reduce the gain of the amplifier 30 by a predetermined amount or increment. This continues as long as it satisfies the condition required by the comparator 72. For periods when the condition is not satisfied, no gain reduction occurs. When segment lock interlock is reached, the decoder 68 is deactivated and the receiver enters the coherent AGC operation mode, wherein the gain of the amplifier 30 is controlled in accordance with the strength of the received IF signal, for example as determined from the segment synchronization character, which is represented by the correlated pulse that occurs at the filter output 62. The correlated pulse is applied to a circuit for polarity section (illustrated in Figure 5) to ensure that the polarity of data is correct, since the FPLL 58 can latch in any of two phases. As will be seen, a polarity inverter control (FIG. 5) which is developed in response to the correlated pulse and a sign bit for polarity selection, are used to control the polarity of the polarity inverter 59 and the position of a switch 73 which applies a voltage to ground (zero) or a voltage + 5V to the FPLL circuit in Figure 6, cc.uo will be described. This feature involves the present invention. A reference level of the correlated pulse is subtracted in an adder 76 and the result is integrated into an AGC integrator 74, the output of which is applied to the decoder 70 to control the charge pump 31. In particular, when the integrated output of the adder 76 exceeds a first level, a gain reduction signal is generated by the decoder 70, to reduce the gain of the amplifier 30 and when the integrated signal falls below a second level, a gain increase signal is generated by the decoder 70, to increase the gain of the amplifier 30. The integrator 74 is readjusted by the decoder 70 after a gain increase or gain reduction signal is generated. The output of the adder 76 also applies to a segment synchronization integrator 94, the output of which is applied to a power supply of the comparator 96, the other supply of which is supplied with a zero signal reference. The output of the comparator 96 is supplied to a segment synchronization generator 98, to provide a segment synchronization output, provided that the integrated correlation pulse of the filter 62 is equal to or greater than a zero value and the synchronization interlock signal of segment when the segment synchronization interlock has been achieved. The segment synchronization generator 98 develops a segment synchronization interlock signal when a sufficient number of segment synchronization has been found (which can be achieved by using a confidence counter assembly) and the segment synchronization interlock signal is converts the FPLL into Figure 5. As will be seen, the polarity reversal control, the segment synchronization interlock signal and the absence of the AFC Override signal are employed to achieve the present invention of locking the AFC for the FPLL. The non-coherent AGC operation is relatively fast, capable of effecting a gain change every eight synchronizer symbols. On the other hand, a coherent AGC operation responds to the segment synchronization character and in this way can make a gain change only once per data segment. It will be appreciated that the AGC can consistently respond to any signal characteristics and this invention will not be limited to the use of a segment synchronizer to develop the AGC voltage. As mentioned, the FPLL 58 in the synchronous demodulator 20 (Figure 2) is stable bi-phasic. Consequently, the phase of the output data can be reversed. The polarity inverter 59 in the digital processor 24 inverts the data signal phase, if necessary. The polarity inverter 59 is regulated by the polarity reversal control, from the polarity selection circuit (Figure 5). In Figure 5, the sign bit of the correlated synchronization pattern that occurs at the outlet of the filter 62, is coupled to the supply D of a first tilting circuit 82, whose output Q is coupled to the supply p of a second circuit rocker 84, and to a power supply of a comparator 86, whose second supply is supplied with the output Q of the swiveling circuit 84. The output of the comparator 86 is applied to the reset supply of a 3-bit counter 88, whose transmission output is coupled to a supply of a Y (AND) gate 90. A second feed of the AND gate (AND) 90 is supplied with the Q output of the swiveling circuit 82 and the gate output is coupled to the switching feed of a switch jogger 92. The output Q of the flip-flop 92 comprises the control signal for polarity reversal which controls the operation of the polarity inverter 59. Two flip-flops 82-84 and the counter 88 are synchronized by the segment synchronization signal derived from the synchronization generator of segment 98 (Figure 3). The sign bit of the correlated output of the filter 62 will be logical 0, when the output of the synchronous demodulator 20 is placed in phase appropriately. If the sign bit is logical 1, the inverter 80 will be operated to reverse the polarity of the data signal applied to the digital processor 24. More specifically, the rockers 82 and 84 are operated to store the successive output sign bits of the filter for synchronization correlation 62. The logical sign O and logic 1 bits result in tilting states of Q = O and Q = l, respectively. If the sign bit does not change (ie there is no output from comparator 86) by 8 synchronization characters of successive segments, the output of counter 88 activates gate Y (AND) 90, to check the polarity of the current sign bit. If it is not logical 0, ie the state of the rocker 82 is Q = 1, Y (AND) 90 will produce an output to switch the rocker 92, causing the polarity inverter 59 to change state. If the sign bit was logical 0 , gate Y (AND) 90 does not produce an output and the state of inverter 80 is unchanged. Figure 6 shows the preferred embodiment of the FPLL 58 (Figure 2) which also responds to the AFC bypass signal from the microprocessor 12 and the latch arrangement of the present invention as described below. The FPLL conventionally includes an AFC filter 80 comprising a series of resistors R1, R2 and R3 and capacitors Cl, C2 and C3. The filter feed 80 is connected to receive the demodulated channel I data signal and its output is connected to a first supply of a limiter 82, the second supply of the limiter 82 is supplied with a reference voltage by a resistor 88 which is it couples to a potentiometer 91. The output of the limiter 82 is supplied to a multiplier supply 84. The demodulated Q signal is supplied to a second multiplier supply 84 whose output is connected to a PLL 86 filter that generates the voltage Vt to control VCO 44 (Figure 2). It will be seen that according to the present invention, the second power of the limiter 82 is also connected through a resistor 92 to a closed terminal (C) of a switch 94 that is operated in response to the segment synchronization interlock signal. . The mobile element of the switch 94 is connected to another switch 100 which is operated in response to the AFC Override signal and which is supplied from the switch 73 in Figure 3. It will be recalled that the switch 73 couples either a + 5V or a OV (ground) depending on the interlocking polarity of the stable two-phase FPLL 88. Arranging the multiple switches in series prevents the FPLL from latching until segment latching has been achieved and the AFC bypass signal is inactive. The result is that the circuit for increasing the pilot of the invention is immediately deactivated in response to a channel change, an on / off switching operation, etc. The AFC filter 80 has amplitude and phase versus frequency response characteristics as illustrated in solid lines in Figs. 7A and 7B, respectively for (1) rejecting the high frequency data components in the I and channel data signal ( 2) provides a phase shift of the power signal. An error in the frequency of VCO 44 from its nominal demodulation frequency, is reflected in the production of beat freques in the I and Q signals. As long as the beating freques are not excessive, that is, the frequency of the VCO 44 -is within a certain range of the nominal demodulation frequency, the AFC 80 filter will produce an output of sufficient amplitude and phase to allow correction of the VCO frequency. This correction is made by multiplying the limited output AFC filter 80 with the Q signal to supply a correction signal to the PLL frequency filter 86. Referring to Figures 7A and 7B will be noted that as the beat frequency increases , the amplitude of the AFC filter response decreases and the phase shift imposed in this way approaches 180 °. Both of these factors reduce the effectiveness of the AFC 80 filter to make the necessary frequency correction. In particular, when the phase shift of the filter exceeds 180 °, the VCO frequency 44 is currently pushed in an opposite direction from that required to achieve frequency interlock. During conditions of receiver activation, channel change or signal loss, the VCO frequency 44 may be sufficiently different from its nominal frequency to make acquisition of the received signal very difficult, even when the FPLL is operated in response to the output of the crystal oscillator 34. The above problems are overcome by providing a charge pump 88 which is activated by the AFC Bypass signal for injection in a stream at the output node 90 of the AFC 80 filter, in response to the I signal. This in effect modifies the phase and amplitude response characteristics as illustrated in dotted lines in Figures 7A and 7B. It will be seen that the modified amplitude response provides a more gradual progressive attenuation in the amplitude response of the filter with increased frequency and in phase shift. The phase shift, most importantly, is set essentially to approximately 90 ° to increase freques and never reaches 180 °. In this way, the AFC filter 80 provides an increased level output signal having a phase shift less than 180 '(ie approximately 90 °) to facilitate carrier acquisition in response to the output of the crystal oscillator 34 during the initial interval. The present invention is thus seen to provide improved performance of the acquisition circuitry (FPLL 58) which develops a small DC voltage in response to the pilot in the received signal. It will be recalled that before acquisition, the AGC system is operated at maximum gain, which amplifies the CD pilot and assists in the acquisition of frequency interlock. During normal, coherent operation of the AGC (after segment lock interlock has been achieved) the IF gain is reduced from what it was at the beginning of the initial interval and thus is the CD pilot. The various circuit elements in the analog demodulator 20, of which FPLL 58 is a part, can introduce DC voltages that can displace the small pilot CD. Also, the data symbols are multilevel and can adversely influence the stability interlocking FPLL by decreasing the magnitude of the pilot CD developed at the output of filter 80. In some cases, data or DC voltages spurious in demodulator 20 can overcome the CD and result in loss of lock or introduction modulation dependent data phase of VCO 44. This is avoided in the present invention to fix or acerrojar the AFC when it has reached locking synchronization segment, to supply a voltage Increasing CD (relatively) large to the pilot CD, thus preventing unlocking of the FPLL due to data or spurious CD voltages on the chip. Either a ground potential or + 5V is applied to the second limiter feed 82 when the segment synchronization interlock has been achieved by the switches 94 and 100. The determination of + 5V or ground is made by detecting sign bit of the synchronization correlation filter 62. The sign bit is determinant of the data polarity and the pilot. The FPLL is biphasic and can be locked with any pilot polarity and any CD polarity that enclave is reinforced by the arrangement of the invention. It is recognized that numerous changes will occur in the disclosed embodiment of the invention to those skilled in the art without departing from the invention. The invention will be limited only as defined in the claims. It is noted that in relation to this date, the best method known to the applicant to carry out the aforementioned invention, is that which is clear from the present description of the invention. Having described the invention as above, property is claimed as contained in the following:

Claims (9)

1. CLAIMS 1. A method to operate a receiver that includes a biphasic stable synchronous demodulator that samples a received signal to retrieve data, and a CD pilot component, the data is formatted in the successive data segments, with each data segment that includes a synchronization character, the method is characterized in that it comprises the steps of deriving data segment synchronization information that includes a sign bit from the sampled signal and using the sign bit to increase the CD pilot component, in response to the synchronization information of data segment. The method according to claim 1, characterized in that the pilot signal component CD is recovered to latch an FPLL (locked loop in frequency and phase) and the last mentioned step includes phase inversion of the recovered data when the bit of sign indicates the wrong polarity and apply a DC voltage to increase the CD pilot component, in response to the data segment synchronization information and the sign bit. The method according to any of claims 1 or 2, characterized in that it includes a filter in the synchronous demodulator, to recover the CD pilot component, the method includes the step of applying a DC voltage to overcome the filter in response to the bit of sign and data segment synchronization information. 4. A television receiver, for receiving a digital television signal formatted in repetitive data segments, including synchronization characters and a pilot component, the receiver includes sampling means for recovering data and the CD pilot component from the television signal , synchronous demodulator means which include a locked phase in biphase stable phase locked by the pilot component CD, to control the sampling means, phase inverting means, to receive the phase of the recovered data, means that respond to the synchronization characters for producing a sign bit indicative of the polarity of the recovered data, means for operating the phase reversal means, when the sign bit indicates the wrong polarity, and means in response to the sign bit, to stabilize the locked loop in biphase stable phase. 5. The receiver in accordance with the claim 4, characterized in that the means responsive to the data segment synchronization characters develop a segment interlock signal, to control the operation of the stabilization means. 6. The receiver in accordance with the claim 5, characterized in that the biphasic stable phase locked loop includes an AFC filter for recovering the CD pilot component and wherein the stabilization means includes means for supplying a relatively large DC voltage to overcome the AFC filter in response to the interlock signal of the AFC filter. segment. 7. The receiver in accordance with the claim 6, characterized in that the polarity of the relatively large DC voltage is determined by the polarity of the sign bit. 8. Apparatus for demodulating a digitally encoded modulated signal, characterized in that it includes a demodulator that responds to the digitally encoded modulated signal, to produce a demodulated output signal having either a first polarity or a second opposite polarity, the demodulated signal includes a pilot component CD, means for determining the polarity of the demodulated signal, and means responsive to the determining means for increasing the pilot component CD. The receiver according to claim 8, characterized in that the signal comprises repetitive segments of multi-level symbols, each segment includes a segment synchronization character, the apparatus includes means for developing a segment interlock signal that responds to the character of segment synchronization, filter means in the demodulator to recover the pilot component CD, and the augmentation means applying a relatively large DC voltage, to overcome the filter means in response to the determining means and to the segmented interlock signal. € snto.