MXPA96003751A - Method and apparatus for performing two dimensional video convolving - Google Patents

Abstract

A two dimensional video convolver generates visually acceptable images on a standard television receiver and includes first and second adder stages and two pixel time period delays. The first adder stage simultaneously receives binary data from three adjacent pixels in a predetermined line in a first direction of a picture to be reproduced on a display during each pixel scan period. The second adder stage output signal during a time period for each of three predetermined adjacent lines in a second orthogonal direction of a picture to be reproduced on a display. Weighting is accomplished in the first and second adder stages by using binary data bits for a pixel as received when the weight for that pixel is a numerical one, and by shifting the received binary data bits by a multiply function when a respective weight is greater than one and equals 2y.

Description

METHOD AND APPARATUS FOR MAKING CQNVO BIDIMENSIONAL VIDEO UCION Reference to Related Requests This invention relates to the following applications, all of which are assigned to the assignee of the present invention, have common inventors, and are concurrently filed: United States Patent Application Serial Number ( GID906), entitled "Apparatus For Processing Mixed YUV and Palettized Video Signals", Patent Application of the States United States of America with Serial Number (GID907), entitled "Video Magnification Apparatus", and United States of America Patent Application with Serial Number (GID908), entitled "Apparatus Using Memory Control Tables Related To Video Graphics Proccesing For TV Receivers ".

Field of the Invention The present invention relates to a method and apparatus for performing two-dimensional video convolution that provides visually acceptable images in a television receiver of the National Standards System Committee (NTSC) or Alternating Phase Line (PAL).

BACKGROUND OF THE INVENTION Convolution techniques are used for a variety of image processing purposes. For bidi-ensional images, convolution is used, for example, for pattern recognition, edge detection, edge improvement by non-sharp masking, spatial frequency filtering, and deconvolution of degraded images by different aberrations produced in the process of image formation. U.S. Patent No. 4,623,923 (Orbach), issued November 18, 1986, describes a real-time video image enhancement system that forms a convolver. The convolver uses digital and analog circuits to convolve a digitized video with a user defined mask to generate an analog video output. The convolver comprises nine convolutional devices in a 3 by 3 matrix, wherein each convolver device comprises a digital-to-analog converter device for receiving a separate digital input from the mask matrix, an element including a plurality of resistors m, and a box that includes a plurality of four switches. The four switches in the box are used to set any of 16 mask values for the associated input. The nine outputs from the nine convolutional devices are added together to be transmitted on an output line. United States Patent Number 4,750,144 (Wilcox), issued June 7, 1988, discloses a 3 by 3 convolver that uses nine binary arithmetic block units connected in cascade to multiply 12-bit binary pixel values that they are positive, or binary members of the complement of twos and scaled to values of 17 bits in a scaler by weights of magnitude of 5 bits that can be positive or negative, which are stored in three recorders. The arithmetic block units are implemented with very large Integrated Silicon Circuit (VLSI) chips, where a multiplication of a 17-bit pixel value is performed with its 5-bit sed by an operations multiplication algorithm. of repeated addition and change in each arithmetic block unit. The algorithm for arithmetic units is implemented for a 17-bit pixel and a 5-bit weight with a 17-by-5 array of full one-bit summing circuits for a total of 85 full summing circuits. For the nine arithmetic units for the 3-by-3 convolver, a total of 765 complete adder circuits are required in addition to the registers, nine O-Exclusive gates to provide the appropriate signed arithmetic for the weights and pixel values, and two climbers. The Patent of the United States of America Number 5, 151,953 (Landeta), issued September 29, 1992, describes a two-dimensional convoluctor. The convolver comprises: (a) a receiving element for sequentially receiving data words from an MxN array, (b) a storage element for storing the coefficients associated with the array QxR, which is a subset of the MxN array, ( c) a QxR matrix of multiplier elements to multiply data words with the associated coefficients, and (d) an adder at the output of the matrix QxR of the multiplier element to sum the multiplication products, to produce an output convolution value designated as Pe. The ultiplier matrix comprises nine multipliers of 8 x 8 configured in three vertical rows. A first input of each multiplier receives a pixel value or a delayed pixel value, and a second input receives an associated coefficient, which multiplies each other. The multiplication or division element required in the prior art configurations typically consumes significant areas of a silicon chip, and is expensive. It is desirable to provide a two-dimensional video convolver that operates to closely approximate the function of a television camera, that uses simple and effective circuits for cost, and that provides visually acceptable images in a television receiver of the National Standards System Committee (NTSC). , or Alternate Phase Line (PAL).

Summary of the Invention The present invention relates to a method and apparatus for performing two-dimensional video convolution that closely approximates the function of a television camera, and uses simple and effective circuits for cost, and provides visually acceptable images of images. and graphics on standard television receivers of the National Standards System Committee (NTSC) or Alternate Phase Line (PAL). Viewed from one aspect, the present invention relates to a two-dimensional video convolver comprising first and second summing stages. The first adding stage responds to the received binary data from a plurality of X pixels in a previously determined line in a first direction of an image to be reproduced in a video display during each period of pixel scanning. The first adding stage processes each of the plurality of X pixels with a previously determined weight, by using bits received from the binary data of a pixel as received when the weight for that pixel is an integer one, and changing the bits received from the binary data by a predetermined number of and bits when the weight is an integer greater than one and equal to 2y, to generate an output signal of the first binary summing stage. The output signal of the first binary summing stage corresponds to an average result for the plurality of X pixels in the line previously determined in the first direction. The second adding stage responds to the binary output signal from the first adding stage during each of X lines previously determined in a second orthogonal direction of the image to be played in the video display. The second adding stage processes each of the plurality of X lines with a previously determined weight, by using the binary data of a line in the first direction as received in the output signal from the first adding stage, when the weight for that line is an integer one, and changing the bits received by a previously determined number of and bits when the weight for that line is greater than the integer one, and is equal to 2y, to generate an output signal from the video convolver . The video convolver output signal corresponds to an average result for the plurality of X pixels in the first direction on the plurality of X lines in the second orthogonal direction, where X > 3. Seen from another aspect, the present invention relates to a two-dimensional video convolver that comprises a first adding stage, a delay element, and a second adding stage. The first adding stage responds to a reception of binary data from a plurality of three pixels in a previously determined line in a first direction of a video image to be played in a video display during each period of pixel scanning. The first adding stage adds the binary data of the plurality of three pixels, multiplied by predetermined weights, by using the bits received from the binary data of a pixel as received when the weight for that pixel is an integer one, and changing the bits received from the binary data of the pixel by a predetermined number of and bits when the weight is greater than the integer one and is equal to 2Y, to generate an output signal of the first binary summing stage. The output signal of the first binary summing stage corresponds to an average result for the plurality of three pixels in the previously determined line in the first direction. The delay element receives the output signal of the first binary summing stage, and generates from it a first delayed output signal corresponding to the output signal of the first binary summing stage delayed by a period of pixel scanning, and generates a second delayed output signal corresponding to the output signal of the first binary summing stage delayed by two periods of pixel scanning. The second summing stage responds to the output signal of the first binary summing stage, and the first and second output signals delayed from the delay element during each of the three previously determined lines in a second orthogonal direction of the video image which will be played in the video deployment. The second summing stage processes the received signals for each of the plurality of three lines with previously determined weights, by using bits of the binary data of a line as received from the output signal of the first adding stage, and the first and second delayed output signals when the weight for that line is an integer one, and changing the bits received from the binary data for that line by a predetermined number of y bits when the weight for that line is greater than the integer one and is equal to 2y, to generate an output signal from the video convolver. The output signal of the video convolver corresponds to an average result for the plurality of three pixels in a first direction on the plurality of three lines in the second orthogonal direction.

Seen from still another aspect, the present invention relates to a method for convolving a three-by-three matrix of binary pixel data received in a two-dimensional video convolver, for generating an output signal of the video convolver that corresponds to a sum weighted of three adjacent pixels in three adjacent lines. In a first step of the method, the binary data for three pixels in a previously determined line in a first direction, are received simultaneously during each period of pixel scanning. In a second step, the binary data received for the three pixels is summed up in a first summing stage of the video convolver, and each of the binary data for the three pixels is multiplied by a previously determined weight by using bits of the binary data of a pixel as received when the weight for that pixel is an integer one, and changing the bits received from the binary data by a predetermined number of y bits, when the weight of that pixel is greater than the integer one, and is equal to 2y, to generate an output signal of the first binary summing stage. The output signal of the first binary summing stage corresponds to an average result for the plurality of three pixels in the previously determined line in the first direction. In a third petso, a delayed first output signal is generated that corresponds to the output signal of the first binary summing stage from the second step, delayed by a period of pixel scanning, and a second delayed output signal is generated that corresponds to the output signal of the first binary summing stage from the second step, delayed by two periods of pixel scanning. In a fourth step, the output signal of the first binary summing stage is added from the second step, and the first and second output signals delayed from the third step, during each of the three previously determined lines in a second orthogonal direction of the video image that will be played in the video deployment. More specifically, the signals received for each of the plurality of three lines are processed with previously determined weights by using the bits of the binary data of a line as received in the output signal of the first adding stage , and in the first and second delayed output signals, when the weight for that line is an integer one, and by changing the bits received from the binary data by a predetermined number of and bits when the weight for that line is greater than the integer one and equals 2Y, to generate the output signal of the video convolver. The output signal of the video convolver corresponds to an average result for the plurality of three pixels in a first direction on the plurality of three lines in the second orthogonal direction. The invention will be better understood from the following more detailed description taken with the accompanying drawings and with the claims.

Brief Description of the Drawings Figure 1 shows a matrix diagram of 3 by 3 pixels associated with a scan point in a television camera, illustrating nine adjacent pixels and their area factors as percentages in accordance with the present invention. Figure 2 shows the matrix diagram of 3 by 3 pixels of nine adjacent pixels and their area factors as numbers that are formed from the pixel matrix diagram of Figure 1 according to the present invention. Figure 3 shows a block diagram of a two-dimensional video convolver in accordance with the present invention.

Detailed Description It should be understood that the corresponding elements that perform the same function in each of the figures have received the same designation number. Due to inherent bandwidth limitations of a standard National Standards System Committee (NTSC) or Alternating Phase Line (PAL) television (TV) system, and the interlaced scanning format of their visual television displays, unacceptable visual artifacts are evident when synthetically generated graphics are displayed in those intertwined visual television displays. More particularly, multiple effects are presented in a vertical direction and in a horizontal direction of a visual display when printing a high bandwidth video signal, for example, an NTSC television receiver. In the vertical direction of the interlaced visual display, one or more bands can be presented that jump vertically in the visual display of the interlaced television receiver. These bands that jump vertically can be seen, for example, when graphs produced in an economical way are displayed on a commercial advertisement with insufficient filtration. In the horizontal direction, a "ziper in motion" effect can be found in a visual display. The effect of "ziper in movement" appears as teeth of a ziper that moves slowly upwards of a visual display, and really it is a blink that appears in alternating frames of an image. However, for the human eye, it appears as if the blink moves upward from the visual display in the shape of a ziper's teeth.

Referring now to Figure 1, a 3 by 3 pixel matrix diagram associated with a scan point 5 oned in a television camera (not shown) is shown. The 3 by 3 matrix diagram illustrates the locations of nine pixels in three adjacent rows of a portion of an image to be displayed in a visual television display. Each pixel is labeled PiRj, where i is a numerical location of the pixel within a row j of the matrix, and i and j are integers between 1 and 3, depending on their location inside the matrix. More particularly, row 1 (Rl) is a top row in the matrix diagram associated with scan point 5, and all three pixels of row 1 (Rl) are shown as pixels P1R1 to P3R1 as progress from left to right. The pixels P1-P3 of row 2 (R2) and row 3 (R3) are numbered in a similar manner, and the matrix includes a central pixel P2R2 and the eight surrounding pixels. The nine adjacent pixels of the image further indicate their associated area factors (%) specifically assigned and used in accordance with the present invention. It should be understood that a scanning point 5 in a television camera (not shown) is not infinitely small. In reality, the television camera responds to visible light not only from a central pixel (P2R2) of a scanning position, but also to a lesser degree, from the pixels of an image surrounding the central pixel (P2R2) of the point 5. The amount of visible light oned from the nine pixels of the scanning point 5 varies essentially, for example, by the amount of the area of each pixel that lies within the scanning point 5, etc. As a result, a weighted value (Pix output) for the central output pixel (P2R2) is oned from a sum of the nine pixel values multiplied by their individual area factors. This weighted value is expressed as: Pix output = 0.03125 (P1R1 + P1R3 + P3R1 + P3R3 + 0.0625 (P1R2 + P3R2) + 0.1875 (P2R1 + P2R3) + 0.375 (P2R2). (1) The area factors selected above solve two important issues.A first issue is that multiplications and / or real divisions are needed to calculate the value for Pix output.These multiplications or divisions require circuits that normally consume significant areas of a silicon chip.However, the two-dimensional video convolutionator of the present invention can be simplified by the use of non-complex adders capable of integrating into a relatively small silicon area of a chip for low cost silicon applications.A second issue is that the frequency response of a visual display is not symmetrical in the horizontal and vertical directions, in a more particular way, a vertical filter that works with the columns of the matrix diagram should have r a much lower cutoff frequency than a horizontal filter that works with rows of the matrix diagram. Therefore, the weighting factors (area) for the nine pixels are not uniform around the central pixel (P2R2). This lack of uniformity results from the speed of the horizontal pixels, which is, for example, 74 nanoseconds, while the speed of the vertical pixels (line speed) of an interlaced visual display is, for example, 63.55 microseconds. The tree factors in Figure 1 are selected to facilitate circuits that reduce the amount of silicon needed to implement the calculation of Pix output in Equation (1), and to accommodate the lack of uniformity of horizontal and horizontal pixel speeds. vertical. Referring now to Figure 2, there is shown a 3 by 3 matrix of pixel values of nine adjacent pixels and their equivalently numbered area factors formed from the pixel matrix diagram of Figure 1 in accordance with present invention. In a more particular way, the pixels P1R1, P1R2 and P1R3 of a first column, receive area factors, integers of 1, 2 and 1, respectively. In a similar manner, pixels P3R1, P3R2 and P3R3 of a third column receive integer area factors of 1, 2 and 1, respectively. The pixels P2R1, P2R2 and P2R3 of the second column receive integer area factors of 6, 12 and 6, respectively. The percentages and integer area factors provided in Figures 1 and 2, respectively, provide two important elements. A first element is that the integer values for the area factors in Figure 2 have the same proportion between the corresponding adjacent pixels as the percentages shown for the area factors in Figure 1. For example, in Figure 1, the factors of area for P1R1 and P1R2 are 3.125 percent and 6.25 percent, respectively, corresponding to a ratio of 1 to 2, as used by the integer area factors shown in Figure 2. Area factors for P1R2 and P2R2 are 6.25 percent and 37.5 percent, respectively, and correspond to a ratio of 2 to 12, as used by the integer area factors shown in Figure 2. The proportions among the other pixels correspond in a way Similary. A second significant element in the selection of percentages and factors of area valued before the whole, is that the total number of units for the area factors in each of the rows of Figure 1, is a binary number, where the factors area of rows 1 to 3 total a binary number of 8, and the area factors of row 2 total a binary number of 16. The total of all units (area factors) is also a binary number of 32. Having summed up each of the partial terms, only multiplications and divisions are required by the binary numbers to calculate the value of Pix output in Equation (1). All mathematical operations can be performed by the change output bits in a first and a second directions, respectively, as will be discussed later in the present for Figure 3. Referring now to Figure 3, a diagram of blocks of a two-dimensional video convolver 10 (shown within a dotted line rectangle) in accordance with the present invention. The video convolver 10 comprises a first adder 12, a second adder 14, a third adder 16, a fourth adder 18, and a fifth adder 20, and first and second delay of pixels connected in series 22 and 24 to achieve the average of pixels (weighting) using 32 units, as illustrated above in Figure 2. The first adder 12 receives the binary data indicating the values of the corresponding pixels from the first and third rows in a previously determined column of the matrix of 3 by 3 pixels associated with a scan point 5 (shown in Figure 1) in the first (A) and second (B) inputs, respectively, and generates, at an output (C), a binary sum output signal from of the same. The second adder 14 receives the binary sum output signal from the first adder 12 at a first input (A) thereof, and receives the binary data indicating a value of one pixel of the second row of the matrix within the point of scan 5 at an input (B) thereof, and generate, at an output (C), a binary sum output signal S = (Rl + 2 * R2 + R3 / 4) from the same, where 2 * R2 indicates a weight of 2 multiplied (*) by the binary value of the bits processed for the pixel signal R2. The binary sum output signal S from the second adder 14 is received at an input of the first pixel delay 22 and a second input (B) of the third adder 16. The first delay of pixel 22 delays the output signal of binary sum S from the second adder 14 for a time necessary to scan a pixel in a row of pixels to generate a first delayed binary output signal Sdl. The first delayed binary output signal (Sdl) from the first pixel delay 22 is received at an input of the second pixel delay 24, which similarly delays the output signal from the first pixel delay 22 for a time necessary to scan a pixel in a row of pixels, to generate a second delayed binary output signal Sd2. The third adder 16 receives the second binary delay output signal Sd2 from the second pixel delay 24 at a first input (A), and adds this output to the binary output signal S from the second summer 14, to generate a signal from binary sum output of the third adder (S + Sd2) / 2. The fourth adder 18 receives the first delayed output signal Sdl from the first pixel delay 22 in both a first (A) and a second (B) inputs thereof, and generates a binary sum output signal from the fourth adder ( Sdl + 2 * Sdl) from the same. The fifth adder 20 receives the binary sum output signal (S + Sd2 / 2) from the third adder 16 in a first input (A), and the binary sum output signal (Sdl + 2 Sdl) from the fourth adder 18 in a second input (B), and generates, in an output (C), a binary sum output of the video convolver (S + 6 * Sdl + Sd2) / 8 from the same, which corresponds to a sum Weighted of the nine pixels shown in the pixel matrix of Figure 2. In the operation, the convolver 10 simultaneously receives three corresponding pixel values PnRl, PnR2 and PnR3, located in a vertical of a received image signal (not shown) in the first input (A) of the first adder 10, in the second input (B) of the second adder 12, and in the second input (B) of the first adder 10, respectively, during each pixel scan time period. The first and second adders 10 and 12 perform the pixel average (weighting) using the assigned weights of the pixel matrix of Figure 2. More particularly, the first adder 12 receives values of 8 bits (bits 7-0 ) for the pixels PnRl and PnR3 of a vertical (column) of pixels in the first (A) and second (B) entries, respectively, of the same, where Pn represents a pixel of a certain column n. The first adder 12 adds the bits 7-0 of the two binary pixel values for the pixels PnRl and PnR3 received, to generate an output R1 + R3 comprising 9 bits (bits 8-0) at its output (C). It should be understood that a sum of two 8-bit numbers (bits 7-0) results in a 9-bit number (bits 8-0), which is provided as a binary output signal of the first adder in the output (C ). It should also be understood that the reception of the. 8-bit values for each of the three pixels of a vertical of the image received as input, are for example purposes only, and that the pixel values may contain any desirable number of bits. The second adder 14 receives the binary output signal (bits 8-0) from the first adder in a first input (A), and the pixel value PnR2 binary in a second input (B), where the pixel value PnR2 binary is offset in adder 12 to operate on bits 7-0 of an 8-bit PnR2 value, such as bits 8-1 for the summing process. The offset of the bits of the pixel value PnR2 by one bit to the left corresponds to multiplying the pixel value PnR2 binary by 2. The sum of two numbers of 9 bits in the second adder 14 results in a number of 10 bits (bits 9-0), of which only bits 9-2 are transmitted as a binary output signal of the second adder S at output (C). It must be understood that the discarding of bits 0 and 1 of the sum corresponds effectively to a function of dividing by four. Accordingly, the binary sum output signal (S) from the second adder 14 at its output (C) corresponds to S = (R1 + 2 * R2 + R3) / 4. More particularly, the summation output signal S from the second adder 14 corresponds to the weighted sum of the three pixel values for a previously determined column, wherein the pixel of a first row (Rl) of that column has a weight of 1, the pixel of the second row (R2) of that column has a weight of 2, and the third pixel of the third row (R3) of that column has a weight of 1. As a result, the first and second adders 12 and 14 they provide a correctly weighted sum of the values of three pixels in a vertical direction. The video convolver 10 assumes that the circuitry (not shown), such as a Dynamic Direct Access Memory (DRAM), precedes the first and second adders 12 and 14 to correctly provide three pixels (PnRl, PnR2 and PnR3) from a line vertically simultaneously to the video convolver 10 during each period of pixel scanning, even when the data comes from different fields of an interlaced scan. It should be understood that, although a "line" in a television image is usually defined as a horizontal line of pixels, a "line" for the purposes of the description of the pixel convolution of the matrix diagram shown in Figure 2 by means of the convolver 10, it is later understood herein to mean either a vertical line or a horizontal line in the matrix. The output signal S at the output (C) of the second adder 14 is received at an input of the first pixel delay 22 and at a second input (B) of a third adder 16. The first pixel delay 22 responds to the pixel clock signals to delay the binary output signal from the second adder 14 for a period of pixel scanning, to generate a first delayed binary output signal (Sdl). The first delayed output signal (Sdl) from the first pixel delay 22 is transmitted to a second delay of pixel 24, which also responds to the pixel clock signals to delay the output signal from the first pixel delay 22 by another period of pixel scanning, and generating a second binary delayed output signal Sd2. Accordingly, the output signals (S) from the second adder 14, the first pixel delay 22 (Sdl), and the second pixel delay 24 (Sd2) provide concurrently averages for three corresponding pixels Pn in the first, second and third adjacent columns, respectively, of an image signal. The third adder 16 adds the bits 7-0 from the second binary delayed output signal (Sd2) of the second pixel delay 24 as received in a first input (A), and the bits 7-0 of the binary output signal (S) from the second adder 14 as received in a second input (B) to generate a sum value of 9 bits, of which only the bits 8-1 are transmitted as the bits 7-0 in a binary output signal of the third adder. The binary output signal from the third adder 16 represents the sum of (S + Sd2) / 2, where the division between two is obtained from a discard of bit 0, from the sum value obtained. The output signal (Sdl) from the first delay of the pixel 22 is received in the first (A) and second (B) inputs of the four summer 18. However, only the bits 7-0 received in the first input (A) , and the R-i bits received in the second input (B) are used in the addition process in the fourth adder 18, to generate a binary output signal of the fourth adder (bits 9-0) represented by (Sdl + 2 * Sdl) = (3 * Sdl) on its output (C). A fifth adder 20 adds the output signals (S + Sd2) / 2 and (Sdl + 2 * Sdl) = (3 * Sdl) from the third and fourth adders 16 and 18, respectively, using only bits 7-0 of the output signal from the third adder 16, and the bits 9-0 of the output signal from the fourth adder 18, to generate an output signal from the video convolver. The output signal of the video convolver generated by the fifth adder 20 at its output (C), is equivalent to [(S ^ d2) / 2 + 3 * Sdl) / 4], which is equivalent to (S + 6 * Sdl + Sd2) / 8. The combination of the division between 4 at the output of the second adder 14, and the division between 8 at the output of the fifth adder 20, is used to scale the output from the fifth adder 20 to 8 bits from the total of 32 bits used in the matrix diagram of Figure 2. In other words, the division functions between 8 and division between 4 are used to prevent the expansion of aggregated sums up to more than 8 bits for subsequent actions. From the pixel matrix diagram using 32 units, shown in Figure 2, it can be seen that the first (PnRl), second (PnR2), and third (PnR3) corresponding pixels of the first and third columns represented by the output signals (S) and (Sd2) have the same weight ratio values of 1, 2 and 1, respectively, in a vertical direction, as provided in the sum output of the second summer 14. Still, in addition, the pixels of the second column, as represented by the output signal (Sdl), receive weights that are 6 times greater than the weights provided for the pixels of the first and third columns at the output of the fifth summer 20. In a more In particular, the two-dimensional processing is carried out in two stages, where, in a first stage, three vertical pixels with a weight of 1-2-1 are processed, and the result is divided by 4 (changed by two bits). This vertically averaged result for the first, second and third verticals is then processed in a second stage by horizontal coefficients in a weighting of 1-6-1, with a net division between 8 that is done as a division between 2, followed by a division between 4, again implemented by the change bits. Accordingly, the two-dimensional video convolver 10 provides an average of pixels as shown in the pixel matrix diagram of Figure 2, while eliminating the use of more silicon-consuming multiplier and / or splitter circuits, which typically is they are used in the convolders of the prior art. As a result * the two-dimensional video convolver 10 operates to closely approximate the function of a television camera by providing a scan point 5 (shown only in Figure 1), which is appropriately weighted and uses relatively simple circuitry that can be implemented in the modest areas of silicon. This helps maintain the cost of the relatively low two-dimensional video convolver 10. The two-dimensional video convolver 10 calculates a 3-by-3-pixel matrix at the horizontal pixel rate described hereinabove as every 74 nanoseconds. It should be appreciated and understood that the specific embodiments of the invention described above in this, are merely illustrative of the general principles of the invention. Experts in this field can make different modifications that are consistent with the stipulated principles. In a more particular way, the invention contemplates any configuration, design and relation of components that work in a similar way, and that provide the equivalent result. For example, a configuration can be used to perform arithmetic operations by the use of adders, and / or change the interconnections of left or right busbars that first provide the average in a horizontal direction of the pixel array of Figure 2, and then perform an average in the vertical direction. Still, further, it should be understood that the present configuration can use average factors different from those shown in Figures 1 and 2, which also provide binary numbers when adding columns or rows, and allowing simple pixel adders and delays to be used. with a bit change to perform the multiplications and divisions.

Claims (19)

1. A two-dimensional video convolver, which comprises: a first adding stage that responds to binary data received from a plurality of X pixels in a previously determined line in a first direction of an image to be played in a video display during each pixel scanning period, to process each of the plurality of X pixels with a previously determined weight by using bits of the binary data of a pixel, as they are received, when the weight for that pixel is an integer one , and changing the received bits of the binary data by a predetermined number of and bits when the weight is an integer greater than one and is equal to 2y, to generate a binary output signal of the first adding stage, which corresponds to a averaged result for the plurality of X pixels in the previously determined line in the first direction; and a second adding stage that responds to the binary output signal from the first adding stage during each of the X lines previously determined in a second orthogonal direction of the image to be reproduced in the video display, and the processing of each of the plurality of X lines with a predetermined weight by using bits of the binary data of the line as received in the output signal from the first adding stage, when the weight for that line is an integer one, and changing the received bits by a predetermined number of and bits when the weight for that line is greater than the integer one and is equal to 2y, to generate an output signal of the video convolver that corresponds to a weighted sum for the plurality of X pixels in the first direction on the plurality of X lines in the second orthogonal direction, where X > 3. The two-dimensional video convolver of claim 1, wherein X = 3, and the first adding stage comprises: a first adder to receive binary data associated with a first and a third pixel in a previously determined line in the first direction of the image to be reproduced in the video display, and to add each of the binary data for the first and third pixels, as they are multiplied with a previously determined weight to generate a binary output signal of the first adder that corresponds to the weighted sum of the first and third pixels; and a second adder to receive the binary output signal of the first adder in a first input, and binary data associated with a second pixel in the previously determined line in the first direction in a second input, and to sum the output signal of the first adder and the binary data for the second pixel, as multiplied with the previously determined weights, to generate a binary output signal of the second adder corresponding to the weighted sum of the first, second and third pixels in the previously determined line. 3. The two-dimensional video convolver of claim 2, wherein: the first adder receives the data bits 7-0 associated with the binary data of each of the first and third pixels on a previously determined line, and applies a weight from an integer one to each of the data bits, and adds the data bits 7-0 of the first and third pixels to generate the output signal of the first adder comprising the bits 8-0 corresponding to the weighted sum of the first and third pixels; and the second adder receives the data bits 8-0 of the output signal of the first adder in a first input, and the data bits 7-0 of the binary data of the second pixel in the previously determined line in a second input as the data bits 8-1 which correspond to the data bits 7-0 multiplied by a weight of 2, and sum the data bits to generate an output signal of the second adder using bits 9-2 of the binary addition which corresponds to the weighted sum of the first, second and third pixels in the previously determined line, divided by four. The two-dimensional video convolver of claim 2, wherein the second adding stage comprises: a delay element for receiving the binary output signal of the second summer, and generating therefrom each of a first output signal delay corresponding to the binary output signal of the first adding stage, delayed by a period of pixel scanning, and a second delayed output signal corresponding to the binary output signal of the second delayed adder by two periods of pixel scanning; and an adder element for receiving the binary output signal of the second adder and the first and second output signals delayed from the delay element, which correspond to the three previously determined lines in the second orthogonal direction of the image to be reproduced in the video display, and to process each of the binary output signals of the second adder and the first and second delayed output signals, as they are multiplied with predetermined weights, to generate an output signal of the video convolver that corresponds to the weighted sum of the three pixels of each of the first, second and third lines. 5. The two-dimensional video convolver of claim 4, wherein the summing element comprises: a third adder to receive the binary output signal of the second adder from the first adder stage, and the second delayed output signal from the second adder element; delay, in a first and in a second inputs, respectively, and to add the binary values for the output signals, to generate a binary output signal of the third adder that corresponds to a weighted sum of the three pixels in each of the first and third lines in the second orthogonal direction; a fourth adder to receive the first delayed output signal from the delay element in the first and second inputs, and add the binary values of the output signals to generate a binary output signal of the fourth adder corresponding to a weighted sum of the three pixels in the second line; and a fifth adder to receive the binary output signals of the third and fourth adders in the first and second inputs, respectively, and add the binary values of the output signals to generate the output signal of the video convolver, which corresponds to the weighted sum of the three pixels in each of the first, second and third lines. The two-dimensional video convolver of claim 4, wherein: the third adder receives the bits 9-2 of the output signal of the second adder from the first adder stage as the data bits 7-0 in the first entry, and the second output signal delayed from the delay element as the data bits 7-0 in the second input, and sum the data bits to generate the binary output signal of the third adder, which produces only the data bits 8-1 from the addition corresponding to a weighted sum of the three pixels in each of the first and "third lines in the second orthogonal direction, divided by an integer 2; • the fourth adder receives the data bits 7 -0 from the first delayed output signal from the delay element in the first and second inputs as the data bits 7-0 and 8-1, respectively, and sum the data bits to generate the binary output signal of the fourth adder as the bits of data 9-0, which corresponds to the weighted sum of the three pixels in the second line, multiplied by three; and the fifth adder receives the output signal from the third and fourth adders in the first and second inputs as the data bits 7-0 and 9-0, respectively, and adds the data bits to generate the output signal from the convolver of video, which produces only the 9-2 data bits of the addition that correspond to. the weighted sum of the three pixels in each of the first, second and third lines, divided by eight. The two-dimensional video convolver of claim 1, wherein the sum of the numerical weights assigned to the plurality of X pixels in a previously determined line in the first direction or in the second direction of an image to be reproduced in a video display, they represent a binary number in a group consisting of a binary number that has a series of Os and ls that contains only a single 1, and the total number of pixels of all the pixels X by X in the first and second directions, is also equal to a binary number in the defined group. 8. A two-dimensional video convolver, which comprises: a first adding stage that responds to a reception of binary data from a plurality of three pixels in a previously determined line in a first direction of a video image to be played in a display of video during each period of pixel scanning, to sum the binary data of the plurality of X pixels multiplied by predetermined weights, by using bits of the binary data of a pixel as received when the weight for that pixel is an integer one, and changing the bits received from the binary data for the pixel by a predetermined number of and bits, when the weight to be applied is greater than the integer one and is equal to 2y, to generate a binary output signal of the first adding stage corresponding to a weighted sum of the plurality of three pixels in the line previously determined in the first direction n; a delay element for receiving the binary output signal of the first adding stage, and for generating therefrom, a first delayed output signal corresponding to the binary output signal of the first additive stage delayed by a period of scanning of pixels, and generating a second delayed output signal corresponding to the binary output signal of the first additive stage delayed by two periods of pixel scanning; and a second adding stage that responds to the binary output signal of the first adding stage and to the first and second delayed output signals from the delay element for each of the first, second! and third predetermined lines, respectively, in a second orthogonal direction of the video image to be reproduced in the video display, and processing the signals for each of the plurality of three lines with previously determined weights by means of the use of bits of the binary data of a line as received from the output signal of the first adding stage and the first and second delayed output signals, when the weight for a line is an integer one, and changing the bits received from the data binary by a predetermined number of and bits when the weight for the line is greater than the integer one and is equal to 2y, to generate a binary output signal of the video convolver corresponding to a weighted sum of the plurality of three pixels in a first direction on the plurality of three lines in the second orthogonal direction. The two-dimensional video convolver of claim 8, wherein the first adding stage comprises: a first adder to receive binary data associated with a first and a third pixel in the previously determined line in the first direction of the video image that is going to reproduce in the video display, and to add the binary data for the first and third pixels multiplied with previously determined weights, to generate a binary output signal of the first adder that corresponds to the weighted sum of the first and twist pixels; a second adder to receive the binary output signal of the first adder and the binary data associated with a second pixel in a previously determined line in the first direction, and to add the binary data of the binary output signal of the first adder and the second pixel multiplied with predetermined weights, to generate a binary output signal of the second adder corresponding to the weighted sum of the first, second and third pixels in the line previously determined in the first direction. 10. The two-dimensional video convolver of claim 9, wherein: the first adder receives the data bits 7-0 associated with the binary data of each of the first and third pixels in the previously determined line, for the purpose of applying a weight of an integer one to the data bits of each of the first and third pixels, and adding the data bits 7-0 of the first and third pixels to generate the binary output signal of the first adder comprising the bits 8-0 corresponding to the weighted sum of the first and third pixels; and the second adder receives the data bits 8-0 of the binary output signal of the first adder in a first input, and the data bits 7-0 of the binary data of the second pixel in the previously determined line in a second input , at the data bit positions 8-1 which correspond to the data bits 7-0 multiplied by a weight of 2, and sum the data bits to generate a binary output signal of the second adder producing only the bits 9 -2 of the binary addition corresponding to the weighted sum of the first, second and third pixels, divided by 4. The two-dimensional video convolver of claim 10, wherein the second adding stage comprises: a third adder to receive the binary output signal of the second summer from the first adding stage, and the second delayed output signal from the delay element in a first and a second inputs, respectively, and to sum the received output signals to generate a binary output signal of the third adder corresponding to a weighted sum of the three pixels in each of the first and third lines in the second orthogonal direction; a fourth adder to receive the first delayed output signal from the delay element in each of the first and second inputs, and sum the received output signals to generate a binary output signal of the fourth adder corresponding to a weighted sum of the three pixels in the second line in the second orthogonal direction; and a fifth adder to receive the binary output signals of the third and fourth adders in the first and second inputs, respectively, and sum the received binary output signals to generate the output signal of the video convolver corresponding to the weighted sum of the three pixels in each of the first, second and third lines. The two-dimensional video convolver of claim 11, wherein: the third adder receives the bits 9-2 of the binary output signal of the second adder transmitted from the first adding stage at the data bit positions 7-0 in a first input, and the second output signal delayed from the delay element as the data bits 7-0 in a second input, and sum the data bits to generate the binary output signal of the third adder that produces only the bits data 8-1 from the addition corresponding to a weighted sum of the three pixels in each of the first and third lines in the second orthogonal direction, divided by an integer 2; the fourth adder receives the data bits 7-0 of the first binary delayed output signal from the delay element in a first and a second input as the data bits 7-0 and 8-1, respectively, and sum the data bits for generating the binary output signal of the fourth adder as the data bits 9-0, which corresponds to the weighted sum of the three pixels in the second line in the second orthogonal direction, multiplied by three; and the fifth adder receives the binary output signals of the third and fourth adders in the first and second inputs as the data bits 7-0 and 9-0, respectively, and adds the data bits to generate the output signal of the convolver of video by transmitting only the data bits 9-2 of the addition, which correspond to the weighted sum of the three pixels in each of the first, second and third lines in the second orthogonal direction, divided by eight. The two-dimensional video convolver of claim 8, wherein the sum of the numerical weights assigned to the plurality of three pixels in a previously determined line in the first direction or in the second direction of an image to be reproduced in a video display, represents a binary number in a group consisting of a binary number that has a series of Os and ls that contains only a single 1, and the total of the numeric weights of all the pixels of 3 by 3 in the first and second addresses, is also equal to a binary number in the defined group. 14. A method for convolving a three-by-three matrix of binary pixel data received in a two-dimensional video convolver, to generate a video convolver output signal corresponding to a weighted sum of three pixels in a first direction, or the array in three lines in a second orthogonal direction of the array, the method comprising the steps of: (a) simultaneously receiving binary data for three pixels in a previously determined line in the first direction during each pixel scanning period; (b) adding the binary data for the three pixels received in step (a) in a first summing stage of the video convolver, and multiplying the binary data for the three pixels by previously determined weights by using bits of the binary data of a pixel as received, when the weight for that pixel is an integer one, and changing the bits received from the binary data by a predetermined number of and bits when the weight of that pixel is greater than the integer one and is equal a 2y, to generate a binary output signal of the first adding stage corresponding to a weighted sum for the plurality of three pixels in the previously determined line in the first direction; (c) generating a delayed first output signal corresponding to the binary output signal of the first adding stage of step (b), delayed by a period of pixel scanning, and a second delayed output signal corresponding to the signal binary output of the first adding stage of step (b) delayed by or? periods of pixel scanning, in a delay element; and (b) adding the binary output signal of the first adding stage and the first and second delayed output signals from the delay element for three previously determined lines in a second orthogonal direction of the video image to be reproduced in the display of video, and processing the output signals for each of the plurality of three lines with previously determined weights, by using the bits of the binary data of a line as received in the output signal of the first stage adder, and the first and second delayed output signals, when the weight for that line is an integer one, and changing the bits received from the binary data by a predetermined number of and bits when the weight for that line is greater than the integer one and equals 2y, to generate the output signal of the video convolver that corresponds to a weighted sum of the plurality of three pixels in a first direction on the plurality of three lines in the second orthogonal direction. The method of claim 14, wherein, in step (b), the substeps of: (bl) receive binary data associated with a first and a third pixel on a previously determined line in the first direction of the image to be reproduced in the video display in a first adder, and add each of the binary data for the first and third pixels multiplied with previously determined weights, to generate a binary output signal of the first adder corresponding to the sum weighted of the first and third pixels; and (b2) receiving the binary output signal of the first adder in a first input of a second adder, and binary data associated with a second pixel in the previously determined line in the first address in a second input of the second adder, to sum the output signal of the first adder and the binary data for the second pixel multiplied with predetermined weights, to generate a binary output signal of the second adder corresponding to the weighted sum of the first, second and third pixels in the first direction. The method of claim 15, wherein: in the sub-step (bl), receive the binary data associated with each of the first and third pixels in a previously determined line, the data bits 7-0 by the first adder , and applying a weight of an integer one to each of the data bits, and adding the data bits 7-0 to generate the binary output signal of the first adder comprising the data bits 8-0, and corresponding to the weighted sum of the first and third pixels; and in sub-step (b2), receiving the data bits 8-0 of the weighted output signal of the first adder in a first input of the second adder, and the data bits 7-0 of the second pixel in the lines previously determined in a second input of the second adder as the data bits 8-1, which correspond to the data bits 7-0 of the second pixel multiplied by a weight of 2, and sum the data bits to generate the output signal of the second adder using only the data bits 9-2 of the binary addition corresponding to the weighted sum of the first, second and third pixels, divided by four. The method of claim 16, wherein, in step (d), the substeps of: (di) receiving the data bits 9-2 of the output signal of the second adder are performed from the first adding stage as the data bits 7-0 in a first input of a third adder, and the second output signal delayed from the delay element as the data bits 7-0 in a second input of the third adder, and sum the bits in data for generating a binary output signal of the third adder comprising only the data bits 8-1 of the addition, and corresponding to a weighted sum of the three pixels in each of the first and third lines in the second orthogonal direction , divided by an integer 2; (d2) receiving the data bits 7-0 from the first delayed output signal from the delay element in a first and in a second input of a fourth adder such as the data bits 7-0 and 8-1, respectively , and adding the data bits to generate a binary output signal of the fourth adder comprising the data bits 9-0, which corresponds to the weighted sum of the three pixels in the second line, multiplied by three; and (d3) receiving the binary output signals of the third and four adders in the first and second inputs, respectively, of a fifth adder, such as the respective data bits 7-0 and 9-0, and adding the data bits to generating the output signal of the video convolver comprising only the data bits 9-2 of the addition corresponding to the weighted sum of the three pixels in each of the first, second and third lines, divided by eight. The method of claim 15, wherein, in step (d), the substeps of: (di) receiving the binary output signal of the second summer from the first adding stage, and the second delaying output signal from the element of delay in a first and a second inputs, respectively, of a third adder, and sum the output signals to generate an output signal of the third adder, which corresponds to a weighted sum of the three pixels in each of the first and third lines; (d2) receiving the first delayed output signal from the delay element in the first and second inputs of a fourth adder, and summing the output signals to generate a binary output signal of the fourth adder corresponding to a weighted sum of the three pixels in the second line; and (d3) receiving the binary output signals of the third and fourth adders in the first and second inputs, respectively, of a fifth adder, and summing the output signals to generate the video convolver output signal corresponding to the sum weighted of the three pixels in each of the first, second and third lines. The method of claim 15, wherein, in steps (b) and (d) the sum of the numerical weights assigned to the plurality of three pixels in a previously determined line in the first direction or in the second direction of an image that will be played in a video display, represent a binary number in a group consisting of a binary number that has a series of Os and ls that contains only a single 1, and the total of the numeric weights of all the pixels X by X in the first and second directions, is also equal to a binary number in the defined group. SUMMARY A two-dimensional video convol- erator generates visually acceptable images on a standard television receiver, and includes first and second summing stages, and two delays of the time period of the pixels. The first adding stage simultaneously receives binary data from three adjacent pixels on a previously determined line in a first direction of an image to be reproduced in a visual display during each period of pixel scanning. The binary data of each of three pixels are processed with a predetermined weight to generate a binary output signal of the first stage representing a weighted sum of the plurality of the three pixels in the previously determined line. The second adding stage responds to a binary output signal of the first adding stage for a period of time for each of three adjacent lines previously determined in a second orthogonal direction of an image to be reproduced in a visual display. The second summing stage processes the binary weighted sum of each of the three lines with a previously determined weight, to generate an output signal of the video convolver that represents a weighted sum of the three pixels in a first direction on three adjacent lines in a second orthogonal direction. The weighting is performed in the first and second summing stages by using bits of binary data for a pixel as received when the weight for that pixel is a numerical one, and by changing the binary data bits received by a previously determined number of bits. and bits in a first direction to provide a multiplication function when a respective weight is greater than one and is equal to 2y. * * * * *