MXPA96002531A - An efficient interpolation filter of equipoelectron - Google Patents

Abstract

The present invention relates to an interpolator comprising: a source of input samples, a delay circuit configured to concurrently supply two input samples, a subtracter having first and second input ports coupled to receive the two input samples; conditioned summing circuit to add a weighted difference provided by the subtracter for one of the two input samples to produce an interpolated sample, and conditioned to add the weighted difference to the interpolated sample to produce an additional interpolated sample, the summing circuit that includes: an adder having first and second input ports and an output port: a multiplexer having an output port coupled to the first input port of the adder, having the first input port coupled to the output port of said adder, and that has a second input port coupled to the delay circuit, and additional circuits that have an output port coupled to the second input port of the adder, and having an input port coupled to the subtracter and conditioned to couple a difference signal or a zero value to said sumad

Description

AN EFFICIENT INTERPOLATION FILTER OF ELECTRONIC EQUIPMENT This invention relates to an interpolation apparatus for generating interstitial samples to other samples of a sampled signal. Currently there are many different known interpolation filter designs, but basically they are of three types. The first type is in the form of a heavy finite impulse response output FI R, filter, in which a plurality of successively delayed samples are weighted and summed to generate an interstitial sample value. The second type generally weighs two adjacent original sample values in a complementary manner, and adds the heavy values to form a new sample value. For example, if two original sample values are designated S 1 and S 2, and it is desired to interpose three interpolated values between S 1 and S 2, the following functions will be performed in successive order to generate a sequence of values S 1, Sa, Sb, Se, S2, where Sa, Sb, Se, are interstitial values formed in accordance with the equations: Sa = 0.75 (S 1) + (1 -0.75) (S2) (1) Sb = 0.50 (S 1) + ( 1 -0.50) (S2) (2) Sc = 0.25 (S 1) + (1 -0.25) (S2) (3) It will be noted that in order to generate the Sa values. Sb, Se, the apparatus must be capable of variable weighing; a function that can significantly complicate the interpolation apparatus.

The third type of interpolation filter commonly determines the difference between adjacent original samples, weighs the difference and then adds the heavy difference to the leading sample.

In this instance, the algorithm performed is in accordance with the equation: Si = S1 + (S2-S1) (K) (4) where K is a variable scale factor. If a sequence shows S 1, Sa, Sb, Se, S2, it is going to be performed, the interstitial values Sa, Sb, Se are generated according to the equations: Sa = S 1 + (S2-S 1) (0.25) (5) Sb = S 1 + (S2-S 1) (0.50) (6) Se = S 1 + (S2-S1) (0.75) (7) This type of interpolation filter also requires a variable weighing apparatus that it can significantly complicate the general interpolation apparatus. An interpolation filter according to the present invention includes a subtractor, a weighing circuit and an adder. The subtractor is conditioned to form differences of adjacent original samples. The weighing circuit weighs the differences with a predetermined value. The adder is configured to a) pass an original sample b) add a heavy difference to the original sample; and c) successively adding the heavy difference to the sample previously generated to form successive samples. BR EVE DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of an interpolator showing one embodiment of the invention. Figure 2 illustrates waveforms of the clock signal applied to the apparatus of Figure 1, whose waveforms are useful in describing the operation of the invention. Figure 3 is a block diagram of an alternative interpolator of one embodiment of the invention. Figure 4 illustrates waveforms of the clock signal applied to the apparatus of Figure 3, whose waveforms are useful in describing the operation of the invention. Referring to Figures 1 and 2, a sampled signal "DATA IN °" is applied to a "D type" multivibrator or D-bolt 10. It is assumed that the samples occur synchronously at a predetermined rate fs defined by the F1 signal The input samples are valid at the intervals shown as boxes S1, S2 and S3.The output of the Bolt D 10 is coupled to an input of a Bolt D 12. The output terminals of the Bolts D 10 and 12 are applied to a subtractor 14 which generates the difference of successive sample values stored in the D-bolts 10 and 12. The differences are applied to a weighing circuit 15, which weighs the respective differences by a value K. If the weighing value is a binary fraction such as Ví ", the weighing circuit can be a simple bit shifter for shifting respective bits of the difference value to bit positions of lower significance.

Alternatively, if the scale factor is equivalent to a sum of binary fractions, the weighing circuit may be in the form of a bit sum and displacement circuit. The weighing circuit may take other forms such as a programmed memory at respective address locations with values corresponding to the heavy address value by the desired weighing factor. In an alternative configuration, using memory as a weighing device, only the most significant bits of the respective difference values can be used as address values applied to a preprogrammed memory. An advantage of using memory programmed as a weighing circuit is that it can be easily reprogrammed to provide different weighing factors for different applications. The heavy differences of the weighing circuit 15 are stored in a Bolt D 16, which responds to a clock signal F2. The clock signal < t > 2 occurs in the same regime as the clock signal F1, and in this example, it is measured in time such that it can be used to operate the additional circuits of the multiplexers 18 and 20. The sample values of the Bolt D 12 are applied to an input of the multiplexer 18, and a feedback signal of an adder 22, is applied to a second input of the multiplexer 18. The output of the multiplexer 18 is coupled to an input port of an adder 22. The sample values of the Locks D 16 are applied to a first input port of multiplexer 20 and a zero value is applied to a second input port of multiplexer 20. The output port of multiplexer 20 is coupled to a second input port of adder 22. The output port of the adder 22 is applied to a Bolt D 24 that is measured in time by a clock signal F3, which in the illustrated example has a rate four times the rate of the clock signal F 1. This clock configuration allows inserting three interpolated samples between respective original samples. The output port of Bolt D 24 provides both a sampled output signal and the feedback signal to the multiplexer 18. If the multiplexer 18 is conditioned to apply a sample form of the Bolt D 12 to the input of the summer 22, the summing circuit It operates as a simple forward feed adder. Alternatively, if the multiplexer 18 is conditioned to apply the feedback signal to the input of the summer 22, the summing circuit operates as an accumulator, successively adding, to each previous sum, values applied to the other input of the adder of the multiplexer 20. Assume that the input sample stream consists of the samples; S 1, S2, S3, S4 A representative output sample sequence may consist of; S1, S1 + KD21 l S1 + 2KD21 > S1 + 3KD21, S2, S2 + KD32, S2 + 2KD32 ... where D21 and D32 correspond to the differences S2-S1 and S3-S2, respectively. When generating the sequence, the K value remains constant. The multiples of K are made by successively adding the difference Dj to the sample previously generated. The operation of the apparatus of Figure 1 will be described for the system providing four output samples for each original input sample. In this example, all the Bolts D are assumed to be triggered by positive flank. That is, a value present at the input of a respective Bolt D is loaded into the latch before the occurrence of a positive transition of the clock signal applied to its clock input terminal. Locks D 10 and 12 are measured in time with the clock signal F 1. Assume that at times T1, T3, and T9, samples S1, S2, and S3 are measured in succession time on Bolt D 12. Concurrently, samples S2, S3, and S4 are measured in time at Bolt D 10. Samples respective resides in Locks D 10 and 12 for a full period of the clock signal F 1. At times T2 and T8 the valid heavy differences (S2-S1) K and (S3-S2) K are present at the output port of the weighing circuit 15, and the sample values S1 and S2 respectively are present in the output port of the Bolt D 12. At time T2, the clock signal F2 sets the scaled difference value (S2-S 1) K in the Bolt D 16. , whose value will be valid at the exit port of Bolt D 16 until time T8. Also at time T2, the clock signal F2 conditions the multiplexer 18 to couple the sample S1 of the Bolt D 12 to an input port of the adder 22, and conditions the multiplexer 20 to couple the zero value to the other input port of the adder 22. The adder 22 will produce an output of a sum equal to S 1 + 0 = S1, which is set in the Bolt D 24 at time T3. At time T4, the clock signal F2, conditions the multiplexer 18 for coupling the feedback of the Bolt D 24 to the input of the adder 22, and conditions the multiplexer 20 to apply the value (S2-S1) K of the Bolt D 16 to the other input port of the adder 22. The adder 22 provides the sum S1 a = S1 + (S2-S1) K, whose sum is stored in Bolt D 24 at time T5, and the output as a second sample in the sequence. At the time T6, the value S1 + (S2-S1) K is coupled to an input port of the adder 22 by the multiplexer 18 and the value (S2-S1) K is applied again to the other input port of the adder 22 by multiplexer 20. Adder 22 generates the sum S 1 b = S1 + 2 (S2-S1) K, which is loaded into Bolt D 24 at time T6, and the output has a third value in a sequence. This sum is applied to the input of the adder by the multiplexer 18, and the value (S2-S1) K of the Bolt D 16 is applied to the other input port of the adder 22 by the multiplexer 20. The adder 22 generates the sum S1 c = S1 + 3 (S2-S1) K, which is loaded in Bolt D 24 at time T7, and the output as the fourth sample in the sequence. At the time T8, the clock signal F2 interrupts the multiplexers 18 and 20 to apply the value in the Bolt D 12 and the value "0" respectively, to the two input ports of the adder 22, starting a new sequence of four samples . The value in Bolt D 12 is now S2, having been loaded into Bolt D 12 at time T5, and the Bolt value D 16 is (S3-S2), loaded at time T. The adder 22 produces the sum of S2, which is stored in Bolt D 24 at time T9 as the fifth sample in the signal sample stream. The output signal sequence is equal to S1, S1 + (S2-S1) K, S 1 +2 (S2-S1) K, S1 +3 (S2-S1) K. S2, S2 + (S3-S2) K The value of K for the previous example is Y * for upstream sampling of 4: 1 linear interpolation. In alternative systems where N samples are provided for each of the original samples, the K value should be equal to 1 / N, and in general will be constant. A generalized sequence of samples will be in the form; S1, S1 + (S2-S1) / N, S1 +2 (S2-S1) / N S1 + (N-1) (S2-S1) / N, S2 .... The apparatus of Figure 1, includes a variable control signal of element 26, to change the value K. However, in this system, it is assumed that said changes will not occur between samples but rather only to reconfigure the system in order to change the number of interstitial samples to be produced between the original samples. It will also be appreciated by those skilled in the art that the multiplexer function 20 can be performed by a "Y" gate to couple the heavy differences to the adder. In this instance, gate Y can be enabled to pass values with a signal that is the logical inverse of clock F2. In addition, the control of the multiplexers can be by signal other than the clock signal F2, for example a signal of similar frequency but slightly different in time or phase, and / or of frequency different from F2. This is suggested in Figure 1, by the arrow in dashed lines between the element 26 and the multiplexer 20. With reference to Figures 3 and 4, an alternative configuration of the interpolator will be described. The elements in Figures 3 and 4, designated with similar numbers as the elements in Figures 1 and 2, respectively, are similar and perform similar functions. As in Figure 1, the elements 10-16 generate sample differences, but with respective differences set in the Bolt D 16 that responds to a clock signal FS. The output port of the Bolt D 16 is directly coupled to an input port of an adder 40. The adder 40 is configured as an accumulator with its output port coupled back to its second input port via a delay element of Sample period consistent in this example of a Bolt D 44 is which is measured in time by a clock signal F3. A multiplexer 42 is interposed between the output port of the adder 40 and the input port of the delay element 44 for the purpose of re-establishing the value of the accumulator. The reset value is provided from Bolt D 12 to a second input terminal of the multiplexer 42. An FM clock signal, is applied to reset the Hasp D 44, and to control the multiplexer 42. A slight delay is provided in the clock signal between the Hasp D and the multiplexer to enable the latch D in order to load a value provided by the port of input "1" of the multiplexer before the multiplexer is conditioned to change to its input port "0". In this example of this mode, the clock signal maintains the delay element 44 (Lock D 44) reset until a particular sample value occurs, in this instance the sample S1. When the sample S1 is available in the Bolt D 12, the FM clock signal rises immediately before the time T3, releasing the reset control of the Bolt D 44. At time T3, the sample S1 is fixed in Bolt D 44 and provided as the first output sample in the output sequence. Immediately after the time T3, the delayed signal FM conditions the multiplexer 42 to couple the output of the adder 40 to the input port D of the latch D 44, thus configuring the adder in the configuration of the accumulator. The multiplexer can be maintained in this state indefinitely. As in the example of Figure 1, the waveforms of Figure 4, applied to the apparatus of Figure 3, correspond to a system for interpolating three interstitial samples between each pair of original samples. The weighing factor K is equal to V *. At time T3, the accumulator is set with the value of sample S1. Subsequently the accumulator, in response to the clock signal F3, successively summs the heavy differences provided by the Bolt D 16 to the previous sum, to provide an output sample sequence having a sample rate four times the sample rate of entry. For each pair of samples, the difference between the pair is accumulated four times. In the fourth accumulation, the second sample of a respective sample pair is produced. Note, for example, S 1 + 4 (S2-S1) (%) = S1 + S2 -S1 + S2. Therefore, there is no need to reset the accumulator for each original sample value, and the adder can operate continuously as an accumulator by adding difference values. The difference values will change in the input sample rate, but the weighing factor remains constant. The number of samples per input sample is determined between the difference between the input sample rate and the rate of the clock signal F3. If the clock signal F3 is R times the input sample rate, involving an up-conversion of the sample rate of R times, the weighing factor should be 1 / R.

However, it should be appreciated that an error generated in the configuration of Figure 3 can be propagated in a large number of samples, which is not the case in the configuration of Figure 1, where at most one error can propagate only in the sample interstitial generated between a pair of original samples. In a further embodiment, the Bolt D 44 and the multiplexer 42 of the circuits of Figure 3 can be independently controlled. The multiplexer 42 can be controlled, with a clock pulse similar to the signal CLOCK (CLOCK) F5 in Figure 4, to reset the accumulator with each new sample value.

This configuration reduces the necessary circuits relative to Figure 1, and includes the advantages of the embodiment of Figure 1.

Claims (9)

1. CLAIMS 1. An interpolator characterized by: a source of input samples; delay circuits configured to concurrently provide two input samples; a subtractor having first and second input ports coupled to receive such two input samples; conditional summing circuits to sum a heavy difference provided by such a subtractor to one of such two input samples to produce an interpolated sample, and conditioned to add said heavy difference to the interpolated sample in order to produce an additional interpolated sample.
2. 2. The interpolator set forth in claim 1, characterized in that said summing circuits include: an adder having first and second input ports and an output port; a multiplexer having an output port coupled to the first input port of said adder, having a first input port coupled to the output port of said adder, and having a second input port coupled to said delay circuits; and additional circuits having an output port coupled to said second input port of such adder, and having an input port coupled to said subtractor and conditioned to couple a difference signal or a zero value to such adder.
3. 3. The interpolator set forth in claim 2, characterized in that said additional circuits comprise an additional multiplexer. The interpolator set forth in claim 2, characterized in that said additional circuits comprise a gate Y. 5. The interpolator set forth in claim 1, characterized in that said subtractor includes a weighing circuit to produce a fractional value of differences provided by such subtractor. . 6. The interpolator set forth in claim 5, further characterized by a latch coupled between said weighing circuit and the additional circuits. 7. The interpolator set forth in claim 1, further characterized by a latch coupled between said subtractor and summing circuits. The interpolator set forth in claim 2, further characterized by a latch coupled between the output port of said adder and the first input port of said multiplexer. 9. An interpolator characterized by: a delay circuit having an input port for receiving input samples and first and second output ports for concurrently providing two input samples; a subtractor having first and second input ports coupled to said first and second output ports of said delay circuit, and having an output port in which heavy differences are provided; an accumulator having a first input port coupled to receive such a heavy difference, an output port for providing interpolated samples, and said accumulator is conditioned to sum each heavy difference to respective interpolated samples.