AN EASILY EXPANSIBLE TRANSPORTATION CURRENT ENCODER The present invention relates to a transport current coder for allowing data from a large number of sources to be combined into a single packet stream, the number of sources being easily expandable. In today's high-definition television (HDTV), and in satellite transmission systems, the programs comprise combinations of a video signal representing a moving image, one or more audio signals (for stereo or multi-language capability) , and one or more data signals (for subtitling, and / or data and / or interactive computer program code). As a specific example, a system proposed by the Grand Alliance consortium provides a program to contain a video signal component, two audio signal components and four auxiliary data signal components. A stream of successive packets of data is formed, each packet containing data from one of the component signals. In this way, the seven component signals are multiplexed in time into a single packet stream, which is transmitted on a transport link. The remote locations receive and process the data contained in the packet stream to reproduce the seven component signals. The image represented by the video signal component is displayed on a display screen, and the sound represented by the components of the audio signal is reproduced in loudspeakers. The auxiliary data component signals are processed by appropriate circuits in the remote location, and are used as intended. For example, if one of the auxiliary data component signals represents subtitling information, a video signal representing a subtitling image is generated, that image signal is combined with the image signal representing the video signal component, and The image represented by the combined image signals is displayed on the display screen. The device used to combine the seven component signals is called a transport current encoder. A working outline published by the International Organization for Standardization, ISO / I EC JTC 1 / SC29 / WG 1 1, Film and Audio Coding Associate, entitled "MPEG-2 Systems Working Draft", (ISO / IEC / JTC1 / SC29 / WG1 1 / N0531) in September 1993, illustrates a block diagram of a transport current coder. This block diagram includes a first-in-first-out (FI FO) data selector and buffer to temporarily and temporarily store data representing the seven components of digital data signals and produce data representing a selected component of the data. seven signal components. These data are fed to the packet maker. A programmer selects which of the signal components will be taken to the next packet slot using either a priority scheme or a fixed time slot scheme, both of which are described in more detail below. To form a packet containing data of a selected signal component, the programmer conditions the data selector to couple the input terminal of the IF input FO for the selected signal component to the packet former, and conditions that IF input FI produce the data that will be carried in that package. The resulting packet is transmitted on the transport link. One problem with the transport current coder illustrated in the previous work outline is that the number of signals that can be combined in the transported packet stream is limited to the seven mentioned above. In future developments, it will probably be required to carry more than those seven signal components in the transmitted packet stream. However, it is difficult to expand the system in the work outline. For each additional signal component a FIFO must be added, the data selector must be redesigned to include an aggregate input terminal, and in the same way the circuits must be expanded to select that aggregate component and to connect the output of that FI FO of the added component to the packet maker. It is recognized herein that it is desirable for a transpolator current encoder to be expandable for more signal components without requiring a complicated redesign of the transport stream encoder. In accordance with the principles of the present invention, a transport stream encoder comprises a plurality of buffers (ie, FIFO buffers) coupled to component signal sources. Each of the buffers has a data output terminal to produce component signal data. A packet former has a data input terminal for receiving component signal data, and produces a packet stream. A data collector is coupled in common to the data output terminals of the FIFO buffers and the data entry terminal of the packet former. A transport stream encoder in accordance with the present invention is easily expanded to accommodate large numbers of component signals by adding more buffers (FIFO) to the data collector, without requiring any major design. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings: Figure 1 is a block diagram of a transport current coder in accordance with the present invention.; Figure 2 is a more detailed block diagram of a FIFO buffer that is used in the transport current coder of Figure 1; and Figure 3 is a memory configuration diagram illustrating a series of tables maintained in the scheduler controller for assigning packet slots to component signals. Figure 1 is a block diagram of a transport current coder in accordance with the present invention. In Figure 1, the illustrated signal lines represent multiple or single bit digital signal lines. Other signals, such as clock generators and synchronizers, are not illustrated to simplify the figure. Although not illustrated, those skilled in the art of digital systems design will understand what signals are needed and how to generate and distribute them to appropriate locations in the system. In Figure 1, one or more program sources (not shown), produce a plurality N of digital signal components, respectively coupled to a corresponding plurality of input terminals 5. Program sources may include data compression networks such as MPEG encoders. The first, second and third signal components are respectively coupled to the input terminals 2, 4 and 6. A signal component N is coupled to an input terminal N. In FIG. 1, the signal components represent a program of Satellite television or HDTV: the first, second and third signal components, coupled to the input terminals 2, 4 and 6, represent a video signal V, audio signal A and CC subtitling information signal, respectively. Such sources of programs, their operation, and the digital, audio and video data signals they produce are well known and will not be described in detail. The plurality of input terminals 5 are respectively coupled to data input terminals DI of a corresponding plurality of IF FO 10 buffers. The input terminals 2, 4, 6 and N are coupled to respective data input terminals. DI of intermediate memories of FI FO 12, 14, 16 and 1 N. The respective data output terminals DO of the FIFO buffers 12, 14, 16 and 1 N are coupled in common to a data collector 20. The data collector 20 is also coupled to a data input terminal of the data collector. a packetizer 30. An output terminal of the packetizer 30 is coupled to an output terminal 15. The output terminal 15 is coupled to the transport link (not shown) to process the packet stream and transmit it to the packet stream. remote locations. The transport link, and its operation, are well known and will not be described in detail. The transport link may include transmission processing networks, such as modulating networks, spectrum shaping and coding. A program controller 50 includes a signal input terminal of available R, and output signals of enabling signal E and signal of the identifier I D. The respective available R output terminals R of each of the IF buffer memory number 10 are coupled in common to the available input terminal R of the programmer controller 50. The output terminal of the ID of the programmer controller 50. , is coupled in common to the respective input terminals of the respective identifier ID of each of the plurality of IF buffers FO 10, and the output terminal of enable E of the programmer controller 50, is coupled in common to the respective ones input terminals to enable E of each of the plurality of FIFO buffers 10. The signal lines that couple together the available terminals R, the ID identifier and enable E, form a control collector 22, which operates in driving with the data collector 20. A start signal output terminal S of the packet former 30, is coupled to a start signal input terminal of the program controller 50. A memory 70 is coupled to the programmer controller 50. A user input terminal 25, which may be coupled to a source of the user's input, such as a computer terminal (not shown), is coupled to an input port of a microprocessor (μP) 60. The μP 60 has a control output port coupled to a control input terminal C of the program controller 50. In a In this embodiment, the program controller 50 may be constructed as an independent controller in a known manner. In this modality, the programmed controller r 50 is directly coupled to the memory 70 and includes its own processor which receives only control information from the μP 60, and controls the storage of information towards, and the retrieval of information from the memory 70. In a second embodiment, the program controller 50 operates as an input / output adapter coupled to the system collector (not shown) of the μP 60. In this embodiment, the program controller 50 is operated under the control of a running program. in μP 60. Memory 70 is coupled to the system collector (not shown) of μP 60, as illustrated in dashed lines in Figure 1, and μP 60 controls the storage of information towards and recovery from memory information 70. In operation, the packetizer 30 produces a stream of sequential packets. Each packet contains data from one of the component signals or, if there is not enough data in that FI FO of the component at the time the packet is formed, a null packet. The packet stream is divided into successive groups of packet slots, each group having a predetermined number of packet slots. The programmer controller 50 controls which signal component is inserted in each packet slot. In a manner that will be described in more detail below, the program controller 50 contains a series of lists of allowable signal components, a list for each packet slot. The list series is stored in a memory associated with the program controller 50. If the program controller 50 is operated as an μP 60 input / output adapter, then the series of lists is stored in the RAM (not shown). ) in μP 60, otherwise, the program controller 50 contains its own memory to contain this series of lists. Regardless of where they are stored, the contents of this series of lists are maintained by the input of a user input terminal 25, via the μP 60 in a known manner. Each FIFO buffer 10, has a unique predetermined address of identification value associated therewith, and the program controller 50 maintains, as part of its lists of allowable signal components, described above, the identification value of each buffer. of FIFO 10 on your list. When it is time to fill a packet slot, the list of allowable signal components for that packet slot is scanned. The program controller 50 places an identification signal containing the predetermined unique identification value for FIFO buffer 10 of the component of the first signal on the signal line ID. This identification signal is received by the input terminals ID of all the FIFO 10 buffers in common. If the identification signal received in the input terminal ID of a FIFO buffer 10 matches its own identification value, it generates a signal available in the available output terminal R indicating whether there is enough data in the FIFO to fill a package; otherwise, the identification signal is ignored, and the FIFO buffer 10 remains dormant. The program controller 50 receives the available signal at its available input terminal R. If the available signal indicates that there is not enough data in the FIFO buffer 10 addressed to form a packet, then the next entry in the list of components signal allowances is accessed, and an identification signal having the predetermined unique identification value associated with that next input is placed on the identification signal lines, and its available signal is also analyzed. This process is repeated until either a FIFO buffer 10 is found that has enough data to form a packet, or there are no more entries in the list. The packetizer 30 generates a start signal at its start output terminal S to indicate the start time of a packet slot. If a FIFO buffer 10 having sufficient data to form a packet was found, then when the start signal is received by the programmer controller 50, an enable signal is produced at its output terminal of enabling E. The buffer FIFO 10 addressed responds to the enable signal, while the other non-addressed FIFO buffers 10 ignore it and remain dormant. In response to the enable signal, the DO data output terminal of that FIFO buffer 10 is enabled, and the data of the FIFO buffer 10 is provided to the data collector 20. The packetizer 30 receives these data from the data collector 20, and generates a packet containing that data. While the packet builder 30 is generating the packet, the program controller 50 is testing the plurality of the FIFO buffers 10 to determine the contents of the next packet slot. However, * if none of the FIFO 10 buffers in the list have enough data to fill a packet, then a null packet is produced for that packet slot. Figure 2 is a more detailed block diagram of a FIFO buffer 10, used in the transport current coder illustrated in Figure 1. In Figure 2, the signal lines represent multiple or single bit digital signals. Other components and signals, for example for synchronization and / or timing, are not illustrated in order to simplify the figure. Those skilled in the art of digital circuit design will understand what components and signals are required, and how to design and interconnect them to the illustrated components. In Figure 2, the data input terminal DI of the FIFO buffer 10 is coupled to an input terminal I of a FIFO 102. An output terminal O of the FIFO 102 is coupled to the data output terminal DO of the FIFO buffer 10. The input terminal of the ID identifier is coupled to an address input terminal of an address comparator 104. A first output terminal of the address comparator 104 is coupled to an input terminal of enabling of an intermediate memory / driver 106, and a second output terminal of the address comparator 104 is coupled to a first input terminal of a "Y" port of two inputs 108. A complete output terminal F of the FI FO 102, is coupled to a data entry terminal of the buffer / driver 106. A data output terminal of the buffer / driver 106 is coupled to the available output terminal R of the memory FIFO intermediate 10. The input terminal of enabling E of the IF buffer 10 is coupled to the second input terminal of the "Y" gate 108. The output terminal of the "Y" gate 108 is coupled to an input terminal enable FIFO output 102. In operation, the address comparator 104 receives the identification signal of the output terminal ID of the programmable controller 50 (of Figure 1) via the control manifold 22. This received identification signal is compared to the predetermined unique identification assigned to this memory FIFO intermediate 10 in the address comparator 104 in a known manner. If the received identification signal is the same as the identification of this FIFO buffer 10, then the signals on the first and second output terminals of the address comparator 104 have a first state indicating that this IF FO 1 0 buffer is being addressed From another man, the signals on the first and second output terminals of the address comparator 104 have a second state - indicating that this IF FO buffer is not being addressed. Those skilled in the art of digital system design will understand that each FIFO buffer 10 may be pre-allocated to any identifier, regardless of the physical or logical location in the data collector 20, provided they are mutually different from those assigned to the other IF FO 10 intermediate memories. FI FO 102 receives data at its input terminal I, and temporarily stores them internally, in a known manner. The signal at the full output terminal F gives an indication of the amount of data currently stored in the IFF 102, also in a known manner. If there is enough data in FI FO 102 for the packetizer 30 (of Figure 1) to form a packet, the signal in the full output terminal F has a first state, otherwise it has a second state. When the FO buffer FI 10 is addressed by the program controller 50, the signal at the enable input terminal of the buffer / driver 106 of the address comparator 104 conditions the buffer / driver 106 to pass the signal of the complete output terminal F of the FI FO 102 to the available output terminal R of the IF FO 10 buffer. When the IF FO 10 buffer is not addressed, the signal on the input terminal enables the of the intermediate / exciter memory 106 conditions the buffer / driver 106 to place its output terminal in a state of high impedance, essentially by disconnecting the FIFO buffer 10 from the control collector 22. Thus, only the memory FIFO 10 address intermediate places a signal on the available line R of the control manifold 22. The FI FO 102 will produce the data currently stored internally at its terminal. alida of data Or when being enabled by an appropriate signal in its input terminal to enable E. When the FIFO buffer 10 is addressed, the address comparator signal 104 to the first input terminal of the "Y" gate 108 is a logic signal "1". This conditions the "Y" gate 108 to pass the signal at its second input terminal, from the input terminal of enabling E of the IF buffer 10, to its output terminal, and in this way, to the terminal E-enable input of the FIFO 102. When the FIFO buffer 10 is not addressed, the address comparator signal 104 is a logical signal "0". This conditions the "AND" gate 108 to produce a logical signal "0" at its output terminal, which disables the output terminal O of the FO FO 102. In this way, only the IF FO 10 buffer allocated will produce data in its data output terminal DO when it is enabled by the programmer controller 50 (of Figure 1). The technique used by the programmer to select which signal component is inserted into the next packet is a hybrid between a priority scheme and a fixed time slot scheme. Figure 3 is a memory configuration diagram illustrating a series of tables, described above, maintained in the program controller 50 for assigning data representing component signals to packet slots. In Figure 3, a portion of a packet stream 10 produced by packetizer 30 (see Figure 1) is illustrated at the top of the figure. Each packet in the illustrated portion of packet stream 10 is represented by a rectangle. The packet stream 1 10 is divided into groups, each containing a predetermined fixed number M of packet slots: slot 1, slot 2, slot 3 to slot M. This group of packet slots is repeated continuously in the packet stream 1 10. That is, the pack immediately following the illustrated slot M is slot 1 of the next group. A service table 130 contains an input for each of the component signals being transmitted by the transmission system. Each entry contains a description of the component signal and an ID identifier. In the illustrated service table 130, the first VIDEO 1 input represents the video component of the first program, and has the identifier 1. The second input AU DIO 1, represents the audio component of the first program and has the identifier 2, and the third input CLOSED CAPTION 1 (SU BTITU LACIÓN), represents the subtitling information for the first program and has the identifier 3. Likewise, the fourth, fifth and sixth entries in the service table 130 (VIDEO 2, AUDIO 2, SUBTITULATION 2) represent the video, audio and subtitling information for a second program and have the identifiers 4, 5, and 6, respectively. Finally, inputs are provided for component signals generated by the transmission system itself. For example, the input having the identifier N-1 represents a signal component that carries a program clock reference signal and encryption keys, and the input having the identifier N represents a signal component that carries several signal tables. systems (that is, the service table). Referring again to Figure 1 and Figure 2, in the illustrated embodiment the identifier in each entry in the service table 130 refers to the pre-assigned identification of the FIFO buffer 10 carrying the associated component signal. Thus, the input having the identifier 1 (VIDEO 1) refers to the video signal component V, coupled to the uppermost part of the FIFO buffer 12 which, in the illustrated embodiment, has the pre-assigned identification of "1"; the input having the identifier 2 (AUDIO 1) refers to the audio signal component A coupled to the FIFO buffer 14, which has the pre-assigned identification of "2"; and the input having the identifier 3 (SUBTITULATION 1) refers to the CC subtitling signal component coupled to the FIFO buffer 16 with the pre-assigned identification of "3". The inputs having the identifiers 4, 5 and 6, refer to similar signal components of video, audio and subtitling of a second program source (not shown). Each packet slot in packet stream 1 10 has a priority list associated therewith. This is illustrated in Figure 3, by a plurality 120 of priority lists, each associated with a respective packet slot, and illustrated immediately below its associated packet slot. The association of priority lists with packet slots is indicated by arrows between each priority list and its associated packet slot. That is, the priority list 1, with the number 122 is associated with the slot of pack 1, the list of priority 2, with the number 124 with the slot of pack 2, the list of priority 3, with the number 126 with slot 3, and priority list M 129 with slot M package. Each priority list contains a plurality of entries each represented by a rectangle. The content of each entry is an identifier (ID) representing a component signal such as that contained in the service table 130. For example, the first entry ID 1 in the priority list 1, with the number 122 contains the identifier "1"representing the video signal component V of the first program source. This is represented in Figure 3 by an arrow between the first entry ID 1 in the priority list 1, with the number 122 and the first entry VIDEO 1 in the service table 130. The second entry I D2 in the list of priority 1, with the number 122 contains an identifier "4" representing the component of the video signal (not shown in Figure 1) of the second program source (not shown). This is represented in Figure 3 by. an arrow between the second input ID2 in the priority list 1, with the number 122 and the fourth input VIDEO 2 in the service table 130. Additional inputs (I D3 ...) in the priority list 1 with the number 122 they can, for example, similarly contain identifiers for all the video signal components being transmitted. Similary, the priority list 2, with the number 124, can, for example, contain entries identifying all the audio component signals. That is, the first entry ID 1 in the priority list 2, with the number 124 represents the component of the audio signal A of the first program source and has the value 2 (represented by an arrow of ID 1 of the list from priority 2 with the number 124, to the second input of AUDIO 1 in the service table 130), the second input ID2, represents the audio signal component of the second program source and has the value 5 (represented by a arrow of I D2 of the priority list 2 with the number 124, to the second input AU DIO 2 in the service table 130), and so on. The priority list 3 may, for example, contain entries identifying the video component signals similar to the priority list 1 - possibly with the video signal components having different positions in the priority list. The following priority list (not shown) can, for example, include entries identifying all subtitle component signals, followed by another priority list of video signal components, and so on. The final priority list M can, for example, contain entries identifying PCR and N-1 component signal of mixer keys and the signal component of the tables. The number of package slots in the group, and the assignment of component signals to the associated priority list for each of the packet slots is best done by considering the respective data regimes of each of the component signals. That is, component signals that have higher data rates (ie, video signal components) will be assigned to more than one priority list, and hence, to more than one packet slot in the group, while Component signals that have lower data rates (for example, audio signal components) will be assigned to only a priority list. Those skilled in the art of digital data transmission will understand how to assign signal components to priority lists to optimize the data throughput of the system, while minimizing the probability of a null packet being inserted into the packet stream. In operation, each time a packet slot occurs, the scheduler controller 50 (of Figure 1) traverses the priority list for that packet stream. The programmer controller 50 extracts the identifier of the first entry in that priority list and places an identification signal representing that identifier in the ID signal lines of the control manifold 22. The addressed FIFO buffer 10 responds by placing the signal of the complete output terminal F of the FIFO 102 (of Figure 2) in the available signal line of the control manifold 22. If the available signal forms a packet, then the program controller 50 waits for a start signal from the train former. packets 30, and when the start signal is received, it generates a enable signal on the enable signal line of the control collector 22. In response to this enable signal, the addressed FIFO buffer 10 produces the data for that packet slot, which is transmitted to packetizer 30, via data collector 20, all as described above. If, on the other hand, the available signal indicates that the routed FIFO 10 buffer does not have enough data to form a packet, then the scheduler controller 50 extracts the identifier of the next entry in the priority list 120 for that slot. package and places a signal representing that identifier in the ID signal lines of the control collector 22, and awaits the available signal from the newly addressed FIFO buffer 10. This continues until either an available signal is received indicating that one of the addressed FIFO 10 buffers has enough data to form a packet, or that the last entry in the priority list is processed, in which case a null packet is placed in the packet slot. Then, the same procedure is followed for priority list for the next packet slot. A transport stream encoder using a data collector for coupling IF FO buffer to the packet former provides the flexibility to easily add more IF FO buffers to the encoder. A new FIFO buffer is coupled to the data and control collectors and assigned an identifier which is different from the identifiers of the IF FO buffers that are already in the collector. In addition, a transport stream encoder, in accordance with the present invention, can easily allow large numbers of FIFO buffers to be attached to the packet former, and in this way a large number of component signals are transmitted on a radio link. transport. The hybrid scheme of assigning signal components to packet slots provides great flexibility. This allows the transmitter to easily provide each component signal with the performance it requires, while minimizing the number of transmitted null packets.