MXPA95001506A - Device and method for controlling the exploring speed of a deimagen entry terminal for balancing the de-synchronization speed of a principle interface - Google Patents

Abstract

The present invention relates to a system for transferring video data from an image input terminal to a main terminal, the main terminal has a transfer rate slower than a data transfer rate of the image input terminal, which system is characterized in that it comprises: control means for selecting a scanning speed and a line sampling rate; image means, operatively connected to the control means, for scanning a document at the selected scanning speed and for producing a set of N valid image data scanning lines therefrom, N is equal to two or more; intermediate memory means, operatively connected to the control means, for storing less than N valid image data scan lines of according to the selected line sampling rate, and interface means, operatively connected to the media buffer, to output the stored scan lines of image data to the terminal terminal

Description

"DEVICE AND METHOD FOR CONTROLLING THE SPEED OF EXPLORING AN IMAGE INPUT TERMINAL TO BALANCE THE SYNCHRONIZATION SPEED OF A MAIN INTERFACE" Inventor: JAMES. STEVENS, North American, domiciled at 90 Thorncliffe Drive, Rochester, New York 14617, E.U.A.

Causaire: XEROX CORPORATION, New York State Corporation, E.U.A. domiciled in Xerox Square - 020, Rochester, New York 14644, E.U.A.

FIELD OF THE INVENTION The present invention relates to a device or method for transferring scanned video data between an image input terminal and a main terminal. More specifically, the present invention is directed to controlling the scanning speed of an image input terminal, when the internal data rate of the image input terminal exceeds the synchronization speed of the main interface.

BACKGROUND OF THE PRESENT INVENTION The frame input scan apparatuses typically employ one or more arrays such as CCD (charge coupling device) for scanning. The arrangement converts each scanned image line into a series of charges which, following the appropriate processing, are emitted as image signals or pixels to an end user. The scanning arrangement, for example, can be carried on a carriage, which moves back and forth under a press plate to provide the necessary relative movement between the image and the array. Other arrangements such as a lamp scan arrangement with a movable document, etc., may also be used. An optimal system focuses the reflected image on the arrangement, and one or more lamps provide image illumination. In a typical scanning process, the image area displayed by each arrangement of photodetectors is converted into a charging potential representative of the gray level of the image. The exploration is carried out during a period of interrogation of a pre-established duration. Following the integration, the image loads are transferred to a pair of analogue shift recorders, the sequence of operation is such that during the integration period, the image loads (image data) of a previous scan line , are synchronized from the shift registers, to leave the shift recorders free to receive the image loads of the next integration period. The duration of the integration period, which must be long enough to fully integrate the image line that is scanned and not yet so long as to allow the array of photodetectors to become saturated, is measured by a fixed-speed synchronization signal Periodic or displacement pulses. When the scanning apparatus operates in a synchronized manner, the relative scanning movement between the array and the images is at a fixed speed. This in turn allows the timing of the displacement pulses in the signal that requires the next line of image signals, referred to as the integration signals, to be synchronized with each other. However, when a scanning apparatus operates in an unsynchronized manner; that is, when the internal transfer rate of the image input terminal is faster than the data transfer rate of the device that receives the image data; the relative exploration movement between the arrangement and the image is not fixed, but disordered and changes with demand. In other words, the signals are produced in response to the movement of the arrangement or document. As a result, the timing of the integration signal may vary and not be in synchronism with the fixed-speed displacement pulses. This can reduce the integration period, to result in incomplete integration of the image line that is scanned. Many methods and devices have been developed, which provide unsynchronized transfer when there is a difference in the transfer speed between the sending and receiving devices and also address the incomplete integration problem. These various procedures will be described shortly thereafter. U.S. Patent 4,541,061 issued to Schoon discloses a method wherein the operating synchronization signal of a scanning apparatus is provided at a rate that balances the varying speed of the scanning mirror through the use of a memory, in which several speeds of synchronization are stored based on the repetitive movement of the mirror. The complete contents of this North American patent are incorporated herein by reference. Another method has been proposed in US Pat. No. 4,587,415 issued to Tsunekawa et al. This North American patent discloses a photodetector with a timing control unit for controlling the information storage and the information reading process of the detector. The complete contents of this North American patent are incorporated herein by reference. In addition, U.S. Patent 4,628,368 issued to Kuraka et al., Discloses a system for controlling the scanning speed of a document reading apparatus, in which the speed, acceleration, and deceleration of the reading apparatus are set according to the image information stored in a buffer. The complete contents of this North American patent are incorporated herein by reference. U.S. Patent 5,043,827 issued to Beikirch discloses an exploration system which corrects incomplete integration. The scanning system uses an interpolator to provide a composite line of image signals when an integration period is prematurely terminated. The complete contents of this North American patent are incorporated herein by reference. In addition, U.S. Patent 4,878,119 issued to Beikirch et al, describes a process for operating a scanning array in an unsynchronized manner. The array has at least one row of detectors to scan an image displayed by the array during an interrogation period and a shift register to receive the signal loads developed by the detector following the integration period. This process includes periodically generating, at a constant synchronization speed, integration pulses defining a succession of predetermined integration intervals and generating an initial or starting integration signal in response to a demand for a line of image signals, wherein The time at which the initial or initial integration signals are presented is different to the time at which the integration impulses are presented. The process interrupts the current integration interval in response to an initial or starting integration signal to start a new integration interval to provide the unsynchronized transfer of a line of image signals. The complete contents of this North American patent are incorporated herein by reference. When using the asynchronous stop / stop scan, the optical system or documents are stopped or stopped completely until an output buffer in the image input terminal is empty enough to reassume the scan. The video data timing is not synchronized to a fixed synchronization, but is dependent on the motion control system. This involves a more complex control system and has issues of motion and image quality associated with it. In addition to an unsynchronized transfer system, a large memory buffer may be used in the image input terminal to solve the problem of different transfer rates. In this situation, a full page can be stored in resident memory and be transferred at the speed used by the interface of the main terminal. However, this technique increases the cost of the system in terms of power consumption of additional components, and the space required by the page memory. There is a problem when trying to transfer scanned video data between an image input terminal and the main terminal, when the internal data transfer rate of the image input terminal exceeds or is capable of exceeding the transfer speed from the main terminal. An example of such a situation is when the output of the scanning apparatus is video based on gray, which is many times the volume of a threshold binary image. This produces an imbalance of the data rate, which can result in a truncated or contaminated page. The problem associated with data transfer is the limited bandwidth of a synchronized image / interface input terminal, when used with an image input terminal which is capable of producing a wide range of volumes and data speeds. An example is an image input terminal capable of producing binary and gray video data at various resolutions. In a binary mode, data speeds can be managed; however, when used in a gray output mode, data rates become prohibitive. This is especially true when the interface is governed by the main terminal which receives the data. Also, when the image input terminal produces video data which exceeds the main synchronized interface speed, such as in a gray output mode, the output video page is contaminated. To prevent or avoid these problems; that is, the unbalance of the transfer speeds, the present invention performs scanning at a slow speed, with the same integration time; that is, a higher resolution, and periodically discards or omits a selected number of valid image data scan lines, to cause the scanning apparatus to perform a virtual or apparent data transfer rate, which is equal to, or less than, the data transfer speed of the main terminal. In other words, the internal data transfer rate of the scanning apparatus is masked, such that the transfer rate as perceived from the outside is equal to, or less than, the data transfer rate of the scanner. the main terminal.

BRIEF DESCRIPTION OF THE INVENTION One aspect of the present invention is a system for transferring video data from an image input terminal to a main terminal. The main terminal has a slower transfer rate than an internal data transfer rate of the image input terminal. The system includes a controller, to select a scanning speed and a line sampling rate. An image scanner is connected to the controller and scans an original at the selected scan speed to produce image data lines. A buffer stores only a portion of the produced lines of valid image data, according to the selected line sampling rate. Then, an interface outputs the stored lines of image data to the main terminal. Another aspect of the present invention is a method for transferring video data from an image input terminal to a main terminal. The main terminal has a slower transfer rate than an internal data transfer rate of the image input terminal. The method selects a scanning speed and a line sampling rate. An original is scanned at the selected scanning speed to produce image data lines. Only a portion of the produced lines of valid image data are selected and stored. The remaining portion of produced lines of valid image data are omitted. The stored lines of image data are output to the main terminal. A third aspect of the present invention is a method for transferring video data from an image input terminal to a main terminal. The main terminal has a slower transfer rate than an internal data transfer rate of the image input terminal. The method generates a set or multiple sets of N valid image data lines, where N is two or more. A line of any set of N valid image data lines is stored, whereas N-l valid image data lines of any set of N valid image data lines are discarded. The stored line of valid image data is issued to the main terminal. A fourth aspect of the present invention is a system for transferring video data from an image input terminal to a main terminal. The main terminal has a slower transfer rate than an internal data transfer rate of the image input terminal. The system includes an image device to generate a set or multiple sets of N valid image data lines, where N is equal to two or more. A buffer stores a line of any set of N valid image data lines. The system further includes a skip circuit to prevent the buffer from storing N-l valid image data lines from any set of N image data lines. An interface outputs the stored line of image data to the main terminal. Further advantages of the present invention will become apparent from the following description of the various features of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The following is a brief description of each drawing used to describe the present invention, and thus, are presented for illustrative purposes only and should not be limiting of the scope of the present invention, wherein: Figure 1 is a block diagram illustrating the relationship between an image input terminal and a main terminal; Fig. 2 is a block diagram illustrating the circuit for intermediate (or temporary) storage of the video data of the image input terminal; Figure 3 is a block diagram illustrating a circuit for controlling temporary or intermediate storage operations of the present invention; Figure 4 is a block diagram showing the temporary storage or buffering operations of a modality of the present invention; Fig. 5 is a block diagram illustrating a buffer or temporary storage circuit for data transfer of a preferred embodiment of the present invention; Figure 6 is a block diagram illustrating a circuit for generating detector line synchronization signals in the present invention; Figure 7 is a block diagram illustrating a circuit for generating a line 1 synchronization of signal N in the present invention; Fig. 8 is a timing diagram illustrating the generation of line 1 synchronization of signal N in the present invention; Figure 9 is a block diagram illustrating an embodiment of a control circuit for the present invention; and Figure 10 is a block diagram illustrating a preferred embodiment of a steering control circuit for the present invention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION The following will be a detailed description of the drawings illustrating the present invention. In this description, also as in the drawings, similar reference numbers represent devices, circuits, or equivalent circuits, which perform the same or equivalent functions. Figure 1 illustrates a relationship between an image input terminal 100 and a main terminal 200. The image input terminal (IIT) 100 converts a reflected image of a document into electrical signals. Then these electrical signals (video data) are transferred to the main terminal 200 in a serial or parallel manner. The main terminal 200 can be either a printing machine, a computer processor, a file server, an electronic storage device, or any electronic device capable of receiving or processing image data. In addition, the IIT 100 and the main terminal 200 communicate from one side to the other to indicate when the main terminal is ready for the transfer, also as provided by the synchronization signals necessary to effect the transfer. To synchronously transfer image data from the IIT 100 to the main terminal 200, the effective data transfer rate of the terminal IIT 100 must be equal to the transfer rate of the main terminal 200. In other words, a transfer Synchronized data from the IIT 100 to the main terminal 200 implies that the scanning device of the IIT 100 scans the image at a constant speed, by using a constant integration time, without having to wait or stop the scanning process to allow it to the main terminal an opportunity to receive all image data from a pre-scan line before the scanning apparatus produces the next new scan line of valid image data. Figure 2 illustrates a circuit used in the temporary storage of video data received from an image detector 80 before the video data is transferred to an output interface 50. As illustrated in Figure 2, the video data generated by the image detector 80 are input to a line buffer 40. The line buffer 40 includes a line buffer 60 and a line buffer memory control circuit 70. The line buffer 60, in one embodiment of the present invention, consists of two separate scan line buffers, which act in tandem to ensure the proper transfer of the video data from the image detector to the interphase interface. output 50. Separate scanning line buffers of the preferred embodiment of the present invention are illustrated in FIG. 5. During temporary storage (or buffering) of the appropriate video data, one of the buffers The scan line receives video data from the image detector 80 and temporarily stores this video data within its memory array, while the other scan line buffer transmits video data from a pre-scan line to the interface 50. The operations of the scan line buffers are controlled by the electronic circuit. 70 buffer of line buffer, according to the pixel synchronization signal of the received image input terminal and the line 1 synchronization of signal N. The pixel synchronization signal of the input terminal allows the circuit control 70 of the line buffer write individual pixels of video data into the scanning line buffer 60. In addition, the line 1 synchronization of the N signal informs the control circuit 70 of the line buffer, when the next line of video data exploration will be introduced for temporary storage. Figure 3 illustrates a circuit for determining which life data scan lines of the image detector 80 are to be transferred to the main terminal and thus which video data scanning lines will be temporarily stored by a line memory buffer 105a. exploration. In Figure 3, a line synchronization signal, from the image detector 80 is input to an N-bit counter 10, and a state decoder 20. The N-bit counter 10 outputs binary signals representing a number of relative scan line, within a set of scan lines. In other words, if the second scan line after re-establishing the counter (the counter is reset after the counter reaches its maximum count) is scanned by the image detector 80, the N-bit counter will emit a logically active signal on line / data line synchronization 2. In addition, if the image detector 80 is scanning the fourth scan line after resetting the counter, the N-bit counter 10 will emit a logically active signal on the line / line synchronization of data 2 and the line / data line synchronization 4. The state decoder 20 receives the input signals from the N-bit counter 10 and input signals from a microprocessor 30. The state decoder 20, from the inputs, determines which individual scan line of valid data from N valid data scan lines will be transferred to the main terminal and which lines N scanning lines of valid image data will be discarded, omitted, or prevented from being stored temporarily in a scan line buffer. When the synchronization of line 1 of signal N is logically active, state decoder 20 indicates that the scan line of valid image data that is presented to a scan line buffer must be temporarily stored in this buffer. The number of scan lines N is predetermined according to the difference between the normal or typical internal data transfer rate of the IIT and the data transfer rate of the main terminal. The resolution at which the image is to be explored, the size of the image and the number of bits per pixel, are also factors in the determination of N.For example, if it is desired that half the number of scan lines generated by the image detector pass through the system, the microprocessor produces signals which cause the state decoder to produce a line synchronization signal from the image detector. of active level logic state for every second state of the N-bit counter. If every fourth line of video is desired, the microprocessor produces signals which cause the decoder to select a line synchronization signal of the image detector, corresponding to each fourth state of the N-bit counter, in addition, if an image is desired of 400 lines by 2.54 cm (1 inch), at half the normal scanning line speed of the image input terminal, the optical system or document is moved at a speed which would generate an image of 800 lines per inch of which every two different scan lines of valid image data are discarded. Figure 5 illustrates a scan line buffer data transfer circuit for a preferred embodiment of the present invention. The pixel data of the image input terminal (IIT) is input to a holding circuit 201 which holds the data in response to a pixel synchronization signal of the IIT. The pixel data of the holding circuit 201 is output to a bidirectional buffer 202 and a bidirectional buffer 205. The bidirectional buffer 202 controls the data flow between the IIT and the buffer (A) 184 also as the flow of data. data from the buffer memory (A) 184 to the main terminal 200 via the output interface 50. A selection signal A / B controls whether the buffer memory (A) 184 is receiving data from the IIT or is outputting data. If the buffer memory (A) is outputting data, the buffer data (A) 184 is passed through the bidirectional buffer 202 and input to a multiplexer 203. The bidirectional buffer 205 operates in the same manner as the bidirectional buffer 202 except that the data stream is controlled by an inverted A / B selection signal. Thus, when the bidirectional memory 202 is allowing the pixel data of the IIT to be stored in the buffer memory (A) 184, the bidirectional buffer 205 is allowing the data stored in the buffer memory (B) 194 to be transferred to the the main terminal 200 via the output interface 50. The data in the buffer memory (B) 194 passes through the bidirectional buffer 205 and is input to the multiplexer 203 when the pixel data resident in the intermediate memory (B ) 194 will be transferred to the main terminal 200. The multiplexer 203 selects either the data from the buffer memory (A) 184 or the data from the buffer memory (B) 194 (by means of the bi-directional buffers-202 and 205) according to the selection signal A / B. The data selected by the milliplexer 203 are retained in the holding circuit 204 to allow proper transfer of the pixel data to the main terminal 200. The data from the holding circuit 204 is transferred to the main terminal 200 in accordance with the transfer speed required by the particular main terminal. Figure 6 illustrates a circuit used to generate the line synchronization signal of the detector. A line synchronization signal from the IIT is input to a delay circuit 110 of 32 pixel synchronization together with the pixel synchronization signal of the IIT. The 32-pixel non-sync delay circuit ignores the first 32 pixels of the CCD (charge coupling device) before it produces a detector line synchronization signal which indicates valid CCD data. The line synchronization signal that is input to the timing delay circuit 110 is also used to synchronize a counter 120 which produces, in the preferred embodiment, two binary outputs that can be used to determine which line of a set of four lines will be processed. The outputs of the counter 120 are input to the circuit of FIG. 7 where they are used to select or discard detector line synchronization signals. Figure 7 illustrates a circuit which produces the synchronization of line 1 of signal N. More specifically, gates Y 130, 140 and 150 produce line 1 sync-nization of 1, line synchronization 1 of 2, and synchronization of line 1 of 4, of the signals, respectively. These signals are fed to a gate NO-0 160, which produces the synchronization of line 1 of the signal N to be used by a buffer control unit. For example, line 1 of 4 signal synchronization is the result of discarding 3 out of 4 line synchronization signals from the detector. It is noted that Figure 7 only illustrates the generation of three separate line synchronization signals. This circuit can be easily modified to include any number of line synchronization signals by increasing the number of gates Y, and adding more selection bits (control) and increasing the size of counter 120. FIG. 8 illustrates the timing diagram of the signals generated in figure 7 for three separate situations. In FIG. 8, the line synchronization signal corresponds to the signal generated by the IIT and the line synchronization signal of the detector corresponds to the signal generated by the 32 pixel synchronization delay circuit 110. It is noted that the line synchronization signal of the detector has the same periodicity as the line synchronization signal, but is delayed by 32 pixel synchronization cycles. Line 1 synchronization of signal 1 indicates the situation where each scan line of the image input terminal is transferred to the main terminal in a synchronized manner. In other words, the line 1 synchronization of the signal 1 corresponds directly to the line synchronization signal of the detector. The line 1 synchronization of the signal 2 corresponds to the situation where every two valid image data scanning lines of the IIT are transferred to the main terminal. Thus, the line 1 synchronization of the signal 2 is generated by every two synchronization lines 1 of signals 1. The synchronization of line 1 of the signal 4 corresponds to the situation where one out of four lines of image data scanning Valid generated by the ITT is transferred to the main terminal. Thus, a line 1 synchronization of the signal 4 is generated by every four synchronizations of line 1 of signals 1.

- - Figure 9 illustrates a direction control circuit of the scan line buffer without rotation of 180 degrees. A buffer memory control circuit 170 controls the various operations of the address control circuit in response to a synchronization signal of the main terminal, a pixel synchronization signal of the IIT, and a line 1 synchronization of the N signal. The control circuit 170 of buffer memory, in response to the input signals, produces a write synchronization signal, a read synchronization signal, a selection signal A / B, and an inverted selection signal A / B. The scan line buffer address control circuit includes two counters 180 and 190. The counter 180 is used to generate the write address for either the buffer (A) 184 or the buffer (B) 194. The counter 180 is loaded with a pre-determined write start address, in response to the load function which is activated by the signal line 1 synchronization N. A write synchronization signal is also fed to the counter 180 with the order to change the writing direction. The write synchronization signal is derived from the pixel synchronization input of the IIT to the buffer memory control circuit 170. The write address output from the counter 180 is fed to the multiplexer 182 and the multiplexer 192. The multiplexer 182 and 192 determine whether the write address is fed either to the buffer (A) 184 or the buffer (B) 194 in response to the selection signal A / B and the inverted selection signal A / B, respectively. The counter 190 produces the read address to be used by the buffer memory (A) 184 and the buffer memory (B) 194. A predetermined read start address is loaded to the counter 190 according to the line synchronization 1 of the N signal that activates the charging function. A read synchronization signal is also fed to the counter 190 in order to change the reading direction. The read synchronization signal is derived from the input to synchronize the main terminal to the buffer memory control circuit 170. The read address output from the counter 190 is fed to the multiplexer 182 and the multiplexer 192. The selection of the read address either for the buffer (A) 184 or the buffer (B) 194 is controlled by the signal selection A / B and the inverted selection signal A / B, respectively. Therefore, when the multiplexer 182 feeds the write address to the buffer (A) 184, the multiplexer 192 feeds the read address to the buffer (B) 194. Thus, the buffer (A) may be storing IIT image data, while the buffer (B) may be transferring image data to the main terminal. Figure 10 illustrates a preferred embodiment of the output buffer which allows rotation of 180 ° in the IIT. In this embodiment, a buffer memory control circuit 270 receives a synchronization signal from the main terminal, a pixel synchronization signal from IIT, and a line 1 synchronization of signal N. From these input signals, the buffer control circuit 270, produces a write synchronization signal, a read synchronization signal, and a selection signal A / B. Fig. 10 operates in much the same way as Fig. 9, except that Fig. 10 has two separate counters for producing the write addresses. More specifically, Figure 10 illustrates the use of a write down counter 280 and an up write counter 295. The read counter 290 in Figure 10 operates in the same way as the counter 190 of Figure 9.To allow rotation of 180, FIG. 10 includes two multiplexers 283 and 293. Each multiplexer receives a read address of read counter 290 and a write direction up and a write direction down from counters 295 and 280, respectively. A selection signal A / B is also fed to the two multiplexers 283 and 293 to allow the multiplexers to choose between the read address or the write addresses. Thus, the selection signal A / B operates essentially in the same way as the selection signal A / B and the inverted selection signal A / B of FIG. 9. To effect the rotation of 180, a selection control signal Two-way scanning is fed to each multiplexer 283 and 293. The bidirectional scanning selection control signal allows the selection of either or both of the write directions towards aba or when the rotation is not desired or the write direction towards up when the rotation of 180 is desired. In other words, to carry out the rotation, the IIT image data is written into the buffer in the opposite direction from which it is read. The appropriate addresses as selected by the multiplexers 283 and 293 are fed to the buffer memory (A) 184 and the buffer (B) 194 in such a way that appropriate operations can be carried out as described above. The bidirectional scanning selection control signal can be generated either by a control unit or user interface when the rotation state is established. Figure 4 illustrates another embodiment of the scanning buffer circuit 40 of Figure 2. In Figure 4, video data from the image detector 80 is fed to an entry scan line buffer 105, which contains a plurality of memory sites. More specifically, each memory address 105 (1), 105 (2), 105 (3) ... to 105 (x-2), 105 (xl), 105 (x) stores data for an individual pixel within a scanning line. The data corresponding to the first pixel of a scan line is input to the memory address 105 (x) and then the pixel data is moved to the next memory location (105 (xl)) in the array, in response to a signal It gives pixel synchronization. The input scan line buffer 105 operates as a shift recorder having the capability to retain an image data scan line. In response to a load signal that is derived from the line synchronization signals generated to indicate the end of a scan line, the contents of the scan line buffer 105 are loaded to the scan line buffer 107. output, the contents of 105 (x) are transferred to 107 (x), the contents of 105 (xl) are transferred to 107 (xl), and the contents of 105 (x-2) are transferred to 107 (x-) 2), etc. After being loaded into the output scan line buffer 107, the video data is again shifted to the right in response to a second synchronization signal corresponding to the synchronization speed of the main terminal, such that the output of video data from the recorder 107 (1) are input in series to the output interface 50. To clarify the description of the present invention, the operations of the present invention will be explained in more detail below, in conjunction with the drawings and tables 1-3. Table 1 shows the situation when the internal transfer rate of the image input terminal is equal to the data transfer speed of the main terminal, a normal synchronized operation. In this situation, during each integration period, image data is formed by the CCD detectors and stored in the buffer memory. Also, during a single integration period, the image data stored in the temporary or intermediate memory is transferred to the main terminal.

TABLE 1 ABBREVIATIONS: DISP. = Device; PER INT. = Integration period; AIM = Stores; EMIT = Emit: OMIT = omit; CCD = Load Alocking Device; 1/0 = Input / Output; MEM. INT. = Temporary or intermediate memory.

For example, during the integration period 1, as shown in Table 1, the array of CCD detectors emits a single scan line of valid image data, say. During the integration period 1, this individual scanning line of valid image data, di, is stored in a first buffer. At the end of the integration period 1, the first buffer memory begins to transfer the data di, to the main terminal to be carried out during the integration period 2, while the array of CCD detectors emits another individual scan line of valid image data, d2, wherein this individual scan line of valid image data, d2, is stored in a second buffer. In addition, during the integration period 2, the contents of the output scan line buffer 107 are completely transferred to the main terminal. At the end of the integration period 2, the second buffer begins to transfer data, d2, to the main terminal while the first buffer begins to receive data, d3. Thus, the process begins again. As shown by Table 1, the main terminal requires only a single integration period to receive all the valid image data for a single scan line. In other words, the internal transfer rate of the image input terminal is equal to the data transfer rate of the main terminal, and a synchronized transfer can be performed. Table 2 shows an operation wherein the internal transfer rate of the image input terminal is greater than the data transfer rate of the main terminal. In this situation, during each integration period, image data is formed by the CCD detectors. However, in contrast to the situation shown in table 1, not all valid image data is stored in the buffer. In addition, the main terminal requires two integration periods to properly transfer a single scan line of valid image data from the image input terminal.

TABLE 2 DISP. PER INT. 9 EMIT CCD d9 TABLE 2 (Continued) During the integration period 1, as shown in Table 2, the array of CCD detectors emits a single scan line of valid image data, say. During the integration period 1, this individual scan line of valid image data, di, is stored in a first buffer. At the end of the integration period 1, the first buffer begins to transfer the data, di, to the main terminal to be carried out during the integration period 2, while the array of the CCD detectors emits another individual scan line of valid image data, d2. It will be noted that during the integration period 2, a portion of the contents of the first buffer is transferred to the main terminal. The individual scan line of valid image data, d2, produced during the integration period 2, is not stored in a buffer, but is actually omitted or discarded. The array of CCD detectors emits another individual scan line of valid image data, d3, wherein this individual scan line of valid image data, d3, is stored in a second buffer during integration period 3. In addition, the final portion of the contents of the first buffer is transferred to the main terminal. At the end of integration period 3, the second buffer begins to transfer its contents, d3, to the main terminal, and the process starts again. As shown by Table 2, the main terminal requires two integration periods to receive all the valid image data for a single scan line. In other words, the internal transfer rate of the data entry terminal is as much as twice the data transfer rate of the main terminal. In addition, by omitting every two valid image data scan lines and maintaining the integration period at a constant speed, a synchronized transfer can be performed.

Table 3 shows another operation in which the internal transfer rate of the image input terminal is greater than the data transfer rate of the main terminal. In this situation, the main terminal requires four integration periods to properly transfer a single scan line of valid image data from the image input terminal.

TABLE 3 The situation shown in table 3 is similar to that shown by table 2, so only the differences will be discussed for the purpose of brevity. In the situation of Table 3, a buffer transfers about a quarter of its contents each integration period; consequently, the data transfer buffer circuit stores only one of four valid image data scan lines. As shown by Table 3, the main terminal requires four integration periods to receive all valid image data for a single scan line. In other words, the internal transfer rate of the image input terminal is as much as four times the data transfer rate of the main terminal. In addition, by omitting three of four valid image data scan lines and maintaining the integration period at a constant speed, a synchronized transfer can be performed. The present invention reduces the data transfer rate of the image input terminal, while leaving the integration time of the image detector unchanged. This is done by moving the optical system or document at a slower speed and omitting a selected number of valid image data scan lines in a periodic manner. Thus, the image is sampled at a higher resolution (slow scan) and the data is only emitted periodically to allow the output interface to continue with the data transfer rate of the image input terminal. The slow scanning speed and periodic line sampling rates are selected by the microprocessor of the image input terminals, based on the volume of data which will be produced. The volume is known based on the size of the document, the resolution, and the mode, that is, gray or binary. To perform the masking of the internal transfer rate of the IIT, the present invention uses a binary counter and a state decoder for counting scan lines from the image detection circuits. The buffer is used to absorb the image or video data from the image input terminal, and a line signal from the image detector 80 is used to synchronize a counter. The outputs of the counter are used in conjunction with a microprocessor which outputs signals used to derive the synchronization of line 1 of signal N. The synchronization of line 1 of signal N is generated by selecting one of each N cycles of line synchronization of the detector of image, where (Nl) is a number of scan lines of the valid video data to be discarded. When the synchronization of line 1 of signal N is in a logical inactive state, the video data coming from the image detector is suppressed. More specifically, a buffer, when the synchronization of line 1 of signal N is inactive, will not store or synchronize any data of the image detector 80. In conjunction with the line selection logic circuit, the scanning speed of the optical system or document is changed by the ratio of the selected lines of video data to the actual video lines produced by the detector. The function of the scan line buffer is to accept image data at the internal data transfer rate of the system and output image data to the interface of the image input terminal at the interface synchronization speed from the main terminal. To carry out this process, the control circuits of the scan line buffer are used to generate two sets of timing signals for the buffer. The input side of the buffer is filled with an image data scan line, in synchronism with the internal pixel transfer speed of the image input terminal. The output side of the internal memory provides data to the interface in a synchronized manner with a slower synchronization device which is compatible with the main terminal. The image data is read from a buffer and during the entire period in which the synchronization of line 1 of signal N is logically active and inactive. However, a scan line buffer is filled only while the synchronization of line 1 of signal N is logically active. Accordingly, the amount of time available to move a scan line of image data over the interface is increased without sacrificing synchronization. In summary, the present invention solves the situation of different transfer speeds by using a synchronized procedure. The present invention synchronously transfers image data which are scanned at a rate exceeding the transfer speed of a main terminal without experiencing the problems associated with the use of a synchronized operation; the interruption of the integration period or process; and the interpolation gives image data to ensure a line composed of image data. In the synchronized operation of the present invention, the image input terminal scans the entire document at a constant, but slower speed, while maintaining and not interrupting the integration period. This scanning process increases the number of valid image data scan lines available and allows an apparent internal or virtual transfer rate (scan) equal to the data transfer rate of the main terminal, whereby transfer is provided synchronized data between devices where the internal transfer speed of the image input terminal exceeds the data transfer rate of the main terminal. Although the present invention has been described in detail above, various modifications can be made without departing from the spirit. For example, data types, although only described in detail with respect to image data, may be video data or any data that is transferred between devices. In addition, the present invention has been described with respect to the number of discarded scan lines that is equal to N-1. However, the number of discarded lines could be any number that would be less than N, while the number of discarded scan lines allows the main terminal to extend the time to receive the data. More specifically, the number of scan lines discarded could be one of three (N = 3). The number of scan lines to be discarded from the predetermined set can be determined by the image input terminal, based on the specifications of the data to be transferred and the transfer speed of the main terminal. If the difference is a fraction of the period that is required for the image input terminal to present a data scan line to the buffer, the discarded number is rounded to ensure proper transfer to the main terminal. In other words, the transfer rate of the main terminal dominates the determination of the discard relation. While the invention has been described with reference to various embodiments described above, it is not confined to the details set forth above, but rather it is proposed to cover such modifications or changes as may come within the scope of the appended claims. It is noted that in relation to this date, the best method known to the applicant to carry out the aforementioned invention, is that which is clear from the present description of the invention. Having described the invention as above, property is claimed as contained in the following

Claims (17)

1. A system for transferring video data from an image input terminal to a main terminal, the main terminal has a transfer rate slower than a data transfer rate of the image input terminal, which system is characterized in that comprising: control means for selecting a scanning speed and a line sampling rate; image means, operatively connected to the control means, for scanning a document at the selected scanning speed and for producing a set of N valid image data scanning lines therefrom, N is equal to two or more; buffer means, operatively connected to the control means, for storing less than N valid image data scan lines according to the selected line sampling rate; and interface means, operatively connected to the buffer means, to output the stored scan lines of image data to the main terminal.

2. The system according to claim 1, characterized in that the selected line sampling rate is periodic.

3. The system according to claim 1, characterized in that the selected line sampling rate is determined based on a document size, resolution, and mode.

4. The system according to claim 1, characterized in that the selected scanning speed produces image data having a first resolution, the first resolution is higher than a resolution of the image data that is received by the main terminal.

5. A method for transferring video data from an image input terminal to a main terminal, the main terminal has a transfer rate slower than a data transfer rate of the image input terminal, which method is characterized in that it comprises the steps of: (a) selecting a scanning speed and a line sampling rate; (b) scanning a document at the selected scanning speed, and producing N scanning lines of valid image data therefrom, N is equal to two or more; (c) storing less than N valid image data scan lines according to the selected line sampling rate; (d) omitting valid image data scan lines not stored in step (c) according to the selected line sampling rate; and (e) emitting the scanned lines of image data to the main terminal.

6. The method according to claim 5, characterized in that step (a) selects a periodic line sampling rate.

7. The method according to claim 5, characterized in that step (a) determines the line sampling rate as a function of a document size, resolution, and mode.

8. The method according to claim 5, characterized in that step (a) selects a scanning speed to produce image data having a first resolution, the first resolution is higher than a resolution of the image data that is received by the main terminal.

9. A method for transferring video data from an image input terminal to a main terminal, the main terminal has a transfer rate slower than a data transfer rate of the image input terminal, which method is characterized in that it comprises the steps of: (a) generating a set of N valid image data scan lines, N is two or more; (b) discarding N-l valid image data scan lines from the set of valid image data N-lines; (c) storing a scan line of valid image data from the set of N valid image data lines; and (e) outputting the scanned image data line to the main terminal.

10. The method according to claim 9, characterized in that step (a) periodically generates a set of N valid image data scan lines.

11. The method according to claim 9, characterized in that step (a) determines N as a function of a size of a document that is scanned, resolution and mode.

12. A system for transferring video data from an image input terminal to a main terminal, the main terminal has a transfer rate slower than a data transfer rate of the image input terminal, which system is characterized in that comprising: image means for generating a set of N valid image data scanning lines, N is equal to two or more; a buffer capable of storing the generated scan lines of valid image data; omission means for preventing the buffer from storing N-l valid image data scan lines from the set of N valid image data scan lines; and interface means for outputting stored scan lines of image data to the main terminal.

13. The system according to claim 12, characterized in that the image means periodically generate a set of N valid image data scan lines.

14. The system according to claim 12, characterized in that N is determined as a function of a size of a document that is scanned, resolution, and mode.

15. A system for transferring valid video data scanning lines from a first device to a second device, the second device has a slower transfer rate than a data transfer rate of the first device, which system is characterized in that it comprises: counter means for counting a number of valid video data scanning lines in a set of valid video data scanning lines, which have been generated for transfer and for generating a count from them; state decoder means, operatively connected to the counter means, for activating a synchronization signal when the count is equal to a predetermined number; buffer means for storing a scan line of valid video data, when the synchronization signal is activated, and for skipping valid video data scan lines when the synchronization line is not activated; and interface means for outputting the stored scan lines of video data to the main terminal; the buffer means transfers the scanning line of valid video data to the interface means when the synchronization signal is not activated.

16. The system according to claim 15, characterized in that it further comprises: image means for scanning an image and for periodically generating a set of N valid video data scanning lines.

17. The system according to claim 16, characterized in that N is determined based on a size of a document that is scanned, resolution, and mode. In testimony of which I sign the present in this City of Mexico, D.F., on March 24, 1995. Representative SUMMARY OF THE INVENTION An image input terminal synchronously transfers image data to a main terminal, when the internal data transfer rate of the image input terminal exceeds the data transfer rate of the main terminal. The image input terminal scans the document at a constant speed, but the constant speed is slower than the normal scanning speed for the image input terminal, whereby it effectively scans the document at a higher resolution. To perform an apparent internal data transfer rate, equal to the data transfer rate of the main terminal, the image input terminal periodically discards or omits valid image data scan lines, to give the main terminal ample time to complete the transfer of data. valid image data. The image input terminal, to facilitate a synchronized transfer of image data, will bypass N-l valid image data scan lines of N valid image data scan lines, such that N is determined by the speed of data transfer from the main terminal.