MXPA06009704A - Method and apparatus for setting a voltage controlled crystal oscillator in a video processing device - Google Patents

Abstract

The present invention concerns a method and apparatus for setting a frequency reference in an integrated receiver decoder (IRD). More specifically, the present invention discloses an electrical circuit arrangement in which the voltage controlled crystal oscillator (VCXO) is set to oscillate at the desired frequency prior to the initial use thereof and that frequency is stored in a non-volatile memory unit. Upon initial use, the IRD receives a data signal corresponding to a frequency reference. The IRD uses a threshold value to compare the frequency reference of the incoming data signal with the frequency stored in the non-volatile memory. If the frequencies differ by a predetermined value, the frequency from the incoming data signal is stored in the non-volatile memory and is used to set the VCXO.

Description

METHOD AND APPARATUS FOR ADJUSTING AN OSCILLATOR CRYSTAL CONTROLLED BY VOLTAGE IN A DEVICE OF PROCESSING OF VIDEO CROSS REFERENCE WITH RELATED REQUESTS This application claims the benefit of Provisional Patent Application Serial No. 60/548145, filed on February 26, 2004, entitled "METHOD AND APPARATUS FOR SETTING A VOLTAGE CONTROLLED CRYSTAL OSCILLATOR IN A VIDEO PLAYBACK DEVICE" , which is incorporated herein in its entirety as a reference.

FIELD OF THE INVENTION The present invention relates to a video processing system.

BACKGROUND OF THE INVENTION Satellite television receiver systems usually comprise an external unit comprising a disk type antenna and a low noise block amplifier (LNB) and an external unit, commonly referred to as an integrated receiver decoder (IRD). The IRD comprises a tuner and a signal processing section. The signal processing section of the IRD produces a plurality of time signals or clocks, some generated by the voltage controlled crystal oscillators (VCXO), used to tune the desired television signal to be displayed by the user's request. A VCXO oscillates at a certain frequency in response to the bit rate multiplier (BRM). As the BRM varies, the frequency output of the VCXO changes. Typically, during the factory setting of the IRD; the appropriate BRM value is determined for a particular range of VCXO output frequencies and these BRM values are stored in a non-volatile memory. However, the physical attributes of the crystal and the environment, such as the temperature, the cutoff frequency and the age of the crystal, where the IRD is used can affect the output frequency of the VCXO. A particular problem associated with the displacement of the VCXO is the ability of the IRD to generate the color subcarrier, where the VCXO must maintain a frequency of 27 MHz which is used by a PLL to generate 3.579545 MHz. Any discrepancy in this VCXO or the Associated BRM can prevent the display from being set on the color burst signal, which causes the video signal to be displayed in monochromatic, partial color and / or color changes. To compensate for any discrepancy in the VCXO, the IRD microprocessor tracks the interval between the timestamps included in the incoming satellite signal and compares this interval with a similarly derived interval from a local clock based on the output frequency of the VCXO. When the compared variables vary greatly, the microprocessor will alter the BRM to correct the output of the VCXO clock. Typically, an acceptable variation for the VCXO clock is less than 15 ppm. According to the physical attributes of the crystal or the change of the environment of those present during the factory setting of the IRD, the time required for the microprocessor to adjust the BRM becomes more important and increases. In addition, when there is no present reference time stamp, this process becomes impossible and the microprocessor will not be able to adjust the factory setting BRM value to compensate the derivations. It would be desirable to be able to correct changes in the physical attributes of the crystal or the environment in cases where there are no time stamps available for the microprocessor to be used in the comparison.

BRIEF DESCRIPTION OF THE INVENTION In one aspect, the present invention involves a method for adjusting a voltage-controlled crystal oscillator in a video processing device comprising the steps of receiving a television signal, determining a first value from the television signal and replace a second value stored in the memory with the first value. In a second aspect, the present invention involves an apparatus comprising a memory for storing a first parameter of the oscillator, an input for receiving the television signal, which comprises time reference data and a processing means for determining a second parameter of the oscillator in response to the time reference data and store the second parameter of the oscillator in the memory.

BRIEF DESCRIPTION OF THE DIGITS Figure 1 is a block diagram of an exemplary embodiment of a digital satellite transmission system. Figure 2 is a block diagram of a multi-format signal processing system. Figure 3 is a block diagram of an exemplary embodiment of a frequency reference in an integrated receiver decoder. Figure 4 is a flow diagram illustrating an exemplary embodiment of a process for updating a frequency reference in an integrated receiver decoder. Figure 5 shows a flow diagram illustrating an exemplary embodiment of a process for initiating the update of a frequency reference in an integrated receiver decoder. Figure 6 shows a flow chart illustrating an exemplary embodiment of a process for interrupting the operation to update the stored BRM value of a frequency reference in an integrated receiver decoder. Figure 7 shows a flow chart illustrating an exemplary embodiment of a fine-tuning process of the BRM of a frequency reference in an integrated receiver decoder. Figure 8 shows a flowchart illustrating an exemplary embodiment of a process of gross adjustment of the BRM of a frequency reference in an integrated receiver decoder.

DETAILED DESCRIPTION OF THE INVENTION The features and advantages of the present invention will be more apparent from the following description, provided as an example. A mode of the present invention may be included within an integrated circuit. Another embodiment of the present invention may comprise separate elements forming a circuit. The examples set forth herein illustrate the preferred embodiments of the invention and such examples should not be construed as limiting the scope of the invention in any way. The present invention relates to a method and an apparatus for adjusting a frequency reference in an integrated receiver decoder (I RD). More specifically, the present invention describes an electrical circuit arrangement wherein the voltage controlled crystal oscillator (VCXO) is adjusted to oscillate at the desired frequency before the initial use thereof. Preferably, the VCXO is adjusted so that the IRD has the ability to generate a color burst signal from the incoming data signal to correctly generate a color subcarrier for the incoming data signal. The IRD has a non-volatile memory unit to store the BRM value corresponding to the frequency at which the VCXO operates. After receiving the data signal, the IRD uses the threshold value to compare the clock of the incoming data signal with the locally generated clock. When the clock difference exceeds a predetermined value, the BRM value is adjusted to reduce the difference. When the new BRM value differs from the BRM value stored in the non-volatile memory, the new value is stored in the non-volatile memory. An alternative method would be to save the BRM value corresponding to the frequency set in the non-volatile memory when the power is removed. This stored value will be used for the next time the IRD is turned on. The present invention can be implemented in a transcoder or in a video decoder that has the capability of receiving a satellite signal or a cable television signal. Such a system usually receives encoded data packets that represent the audio and video information in a compressed form. Part of the data of the incoming packet data signal is the video signal that is encoded, so that the color signal can be generated and viewed after it has been decoded at the appropriate frequency. This is why it is important that the VCXO be set to oscillate at the appropriate frequency. With reference to Figure 1, a diagram of an exemplary mode of the satellite television system is shown. Figure 1 shows a transmitting satellite (110), a parabolic disk antenna (120) with a low noise block 130, a digital satellite transcoder 140 and a television monitor 150. A satellite transmission system operates to transmit microwave signals to a broad transmission area. In a digital television transmission system, this is achieved by transmitting the signals from a geosynchronous satellite 110. A geosynchronous satellite 110 orbits the Earth once a day at an altitude of approximately 35,786 kilometers above the earth's surface. Since the digital television transmission satellite 110 generally orbits around the Equator, it constantly remains in the same position with respect to the positions on the ground. This allows the satellite receiving antenna 120 to maintain a fixed viewing angle. A digital television transmission satellite 110 receives a signal from an upstream transmitter and then retransmits the signal back to Earth. The altitude of the transmission satellite 110 allows subscribers to receive a signal in a geographically wide area. However, the distance from the Earth and the hard energy conservation requirements of the satellite also result in a weak signal that is received by the subscriber. Therefore, it is critical that the signal be amplified as soon as possible after it is received by the antenna.

This requirement is achieved through the placement of a low noise block descending converter amplifier 130 (LNB) in the feed mouth of antenna 120 of the parabolic dish. With reference to Figure 2, a block diagram of an exemplary digital video receiver system 200 in accordance with the present invention is illustrated. System 200 includes an antenna 220 and an input processor 222 for receiving and digitizing a modulated transmission bearer with associated audio, video and data signals. The system 200 also includes a demodulator 224 for receiving and demodulating the digital output from the input processor 222. In addition, the system 200 includes a remote control unit 232 for receiving user input commands. The system 200 also includes activators 246 for displaying digital-input to digital-output or digital-input to-analog-output and a display (230) digital-input or analog-respective input for together converting the digital video image data in visual representations. In the preferred embodiment, the display 230 is a multi-format television display unit and in accordance therewith, display triggers 246 is a digital-input-to-multiformat-output device. While the present invention is described with respect to the exemplary embodiment of Figure 2, which includes a deployment device, the invention can also be applied to systems that include a display device such as transcoders, video cartridge recorders and DVD players. . The system 200 also includes a video processor 226. In general, the video processor 226 receives user input commands from a remote control unit 232, receives the demodulated data from the demodulator 224, and transforms the demodulated data into video image data for the video activators 246. deployment in accordance with user input commands. Accordingly, the video processor 226 includes a remote interface 236 and a controller 234. The remote interface 236 receives the user input commands from the remote control unit 232. The controller 234 interprets the input commands and appropriately controls the settings for the different components of the processor 226 to carry out the commands (i.e., channel selections and / or an on-screen display ("OSD")). The video processor 226 also includes a decoder 280 for receiving the demodulated data from the demodulator 224 and outputs a digital signal that is decoded by grid, copied to byte length data segments, deinterleaved and corrected for Reed error -Solomon. The output data corrected from the decoder 280 is in the form of a transport data stream compatible with the Moving Pictures Experts Group (MPEG) standard containing the multiplexed audio, video and data components representative of the program.

The processor 226 also includes a selector 238 decoding packet identifier ("PI D") and a transport decoder 240. The selector 238 PI D identifies and routes the selected packets in the transport stream from the decoder 280 to transport the decoder 240. The transport decoder 240 demultiplexes the selected packets into audio data, video data and digital data in digital form. other data for further processing by the processor 226, as described below. The transport stream provided to the processor 226 comprises data packets containing program channel data, auxiliary system time information, and program specific information, such as the program content audience and program guide information. With the use of the program-specific information, the transport decoder 240 identifies and assembles the individual data packets that include the program channel selected by the user. The transport decoder 240 directs the auxiliary information packets to the controller 234, which analyzes, collects and assembles the auxiliary information in tables arranged in a hierarchical way. The time information of the system contains a time reference indicator and associated correction data (for example, daylight savings time indicator and displacement information that is set for the time shift, years elapsed, etc.). The time information is sufficient for an internal decoder (e.g., 242 M PEG decoder, described below) to convert the time reference indicator into a time clock (e.g., time and date from the eastern United States) to set the time of day, the date of future program transmission by the program's broadcaster. The time clock can be used to start the processing functions of the projected program, such as playing the program, recording the program and playing the program. Meanwhile, the program-specific information contains conditional access, network information, and identification and link data that allow the system 200 to tune to the desired channel and assemble data palettes to form complete programs. The program-specific information also contains auxiliary information about the content of the program (for example, the audience based on the age of the viewers), program guidance information (for example, an electronic program guide (EPG)). ), and descriptive texts related to the transmission programs as well as the data that support the identification and assembly of this auxiliary information. The system 200 also includes an MPEG decoder 242: The transport decoder 240 provides video, audio, and currents that are MPEG-compatible sub-images for the MPEG decoder 242: Video and audio streams contain compressed audio and video data represent the program content of the selected channel. The sub-image data contains information associated with the content of the channel program such as audience information, program description information, and their peers. The decoder 242 MP EG decodes and decompresses the audio and video data into MPEG-compatible packets from the transport decoder 240 and derives the program representative data decompressed therefrom. The MPEG decoder 242 also assembles, collects and interprets the sub-image data from the transport decoder 240 to produce formatted program guide data for transmission to an internal OSD module (not shown). The OSD module processes the sub-image data and other information to generate the copied pixel data representing the subtitles, control and information menu displays that include selectable menu options and other items for presentation in the display 230. The control and information displays, which include text and graphics produced by the OS D module, are generated in the form of pixel map data superimposed under the address of the controller 234. The pixel map data superimposed from the module. The OSDs are combined and synchronized with the representative data of the pixel from the decoder 242 under the direction of the controller 234. The combined pixel map data representing a video program on the selected channel together with the associated sub-image data is encode by the MPEG decoder 242. Fig. 3 is a block diagram of an exemplary embodiment of a frequency reference in an integrated receiver decoder, shown in accordance with the present invention. Figure 3 shows a transport demultiplexer 314, a controller 334, a VCXO 374, and a digital-to-analog converter 394 and a memory 354. In the system 300, at the start and during operation, the controller 334 applies a BRM value to VCXO 374, such that the VCXO 374 generates a clock signal at the desired clock frequency. The clock frequency is selected such that the color signal can be decoded appropriately. The transport demultiplexer 314 separates the incoming packet information received from the demodulator (Figure 2, 224). Among the different types of information in received palettes, the adaptation fields comprising timestamps are transmitted in the common conductor to the controller 334. The controller 334 calculates the time interval between the time of the local clock in the reception time of the time stamp and the time of the local clock to the reception of the previous time stamp and compares it with the time interval that is the difference between the two time stamps received. The controller 334 may alternatively convert the interval between the timestamps to a representative BRM value and compare this value to a BRM value stored in the memory 354. When the controller 334 determines that the newly calculated time interval is very different from the interval stored in memory 354, controller 334 will store the new value in memory 354 and apply the value BRM associated with the new interval for VCXO 374, which adjusts the output clock frequency of VCXO 374. This has the effect It is desirable to correlate the clock frequency of the VCXO 374 with the time stamps of the data in received packets, which compensates for any physical changes related to the VCXO crystal or the environmental effects in the IRD installation. The new clock frequency is then applied to the digital encoder 394 and can be fed back to the controller 334. In an exemplary embodiment, the digital encoder 394 uses a VCXO 374 centered at 27.000000 MHz (+/- 25 ppm) as its clock frequency. reference. When a voltage is applied to the varaters of the VCXO 374, the center frequency of 27 MHz can be adjusted by approximately +/- 150 ppm (+/- 4050 Hz). This corresponds to -4050 Hz for a BRM value 00 and a +4050 for a BRM FF value. Since there are 256 states for a BRM value and an approximate pull interval of 8100 Hz, then each BRM state is approximately 31.6 Hz. The 27 MHz clock is used to generate a horizontal, vertical and chroma burst time. Chorinance burst time is 27.000000 MHz / 7.542858101 = 3.579545 MHz. When the 27 MHz oscillator is at its lowest frequency, 26.995950 MHz, then 26.995950 / 7.542858101 3.579008 MHz. When divided, there will be a difference of 537 MHz. the frequency (3.579545 MHz) of FCC chrominance burst. This difference is large enough to cause a loss of color in the television set. Typically, a television set has a PLL (phase locked circuit) in the chrominance circuits that allow this internal 3.579545 oscillator to be set to the incoming video burst frequency. This fixation is necessary for a color image to occur. The typical setting range for a television set is +/- 300 Hz. When the generated burst frequency is outside the fixing range, then a black and white image will be displayed. When closed at the maximum setting range, then an effect is displayed for the colors of the rainbow on a television set. A television set will also display irregular colors on its screen when the chrominance setting is reached but a closed trace is not maintained. Figure 4 is a flow chart illustrating an exemplary embodiment of a process for updating a frequency reference in an integrated receiver decoder (140 of Figure 1). During the start procedure after being turned on at 410, the IRD will load the stored BRM value from the non-volatile memory 420. The IRD then applies this BRM value to the VCXO to tune the satellite signal 430. Once the IRD is set to the satellite signal, the controller will receive the data packets comprising timestamps that indicate the time in which the packets were transmitted from the satellite 445. After at least two timestamps are received, the controller calculates the desired BRM value for the VCXO based on the time interval between the two or more timestamps 447. The controller then compares the desired BRM value against the BRM value to be applied to the VCXO 450. When the desired value is very different from the applied BRM value, the controller stores the desired BRM value in the non-volatile memory 460, loads this BRM value from the non-volatile memory 420 and then apply this new BRM value to the VCXO 430. This process for determining a new value 445 BRM, the comparison 450 and the possible update 460 are then repeated after a predetermined time interval. However, when the desired BRM value is not very different from the stored BRM value, the BRM value is not updated and the process is repeated to determine a new value 445 BRM, a comparison 450 and a possible update 460, after an interval of predetermined time Figure 5 shows a flow chart illustrating an exemplary embodiment of a process for initiating the update of a frequency reference in a decoder (140 of Figure 1) integrated receiver. After a new BRM value is calculated by the controller, the process of updating the BRM value applied to the VCXO starts 510. The controller reads the BRM value from the memory, as an EEPROM 520. The controller then determines whether the BRM value is a valid 530 value. When the BRM value is not valid, the controller continues to use the 540 BRM value by default. When the value is valid, the controller replaces the default BRM value with the calculated 550 BRM value. The controller then changes the adjustment state to adjust the BRM value applied to the VCXO to fine 560. The controller then returns to the operational state 570. Figure 6 shows a flow diagram illustrating an exemplary embodiment of a process for interrupting the operation to update the stored BRM values of a frequency reference in an integrated receiver decoder (140 of Figure 1). After a period of time has elapsed, since the previous BRM update, the controller will monitor the incoming data signals until an adaptation packet containing a timestamp is received. After the adaptation packet containing the time stamp is received, the operation of the controller is interrupted. An exemplary period of time between the BRM updates may be 1 second, but may be longer or shorter, depending on the operating requirements of the system and / or the design goals. Once the interruption has been generated, the controller sets the local clock to obtain a value, called a local clock reference (LCR) in this mode, which represents the local time when the time stamp was received in the field. adaptation 620. Then, the previous controller saves the LCR previously stored in a location 630 of alternate memory. The controller then stores the new local clock reference at location 640 of primary local clock reference memory. The previously stored system clock reference (SCR), calculated from the time stamp previously received in the adaptation field, is stored in a location 650 of alternate SCR memory. The newly received SCR is then stored in location 660 of Primary SCR memory. The controller then checks the appropriate memory value to determine the reference state variable 670 of the BRM adjuster. When the stored state variable is coarse, the controller executes sub-routine 680 of coarse adjustment. When the stored state reference variable is not equal to coarse, the controller executes the fine adjustment subroutine 690. After the appropriate subroutine is completed, the controller returns to its operating state 695. FIG. 7 shows a flow diagram which illustrates an exemplary embodiment of a fine-tuning process of the BRM of a frequency reference in an integrated receiver decoder (140). of Figure 1). The interrupt routine described in Figure 6 or the coarse adjustment subroutine described in Figure 8, initiate sub-routine 705 of fine adjustment. First, the controller decides whether an appropriate interval has elapsed since the last 710 calibration of the BRM. When an appropriate interval has elapsed, where in this mode the interval is 1 second, a reference delta of the system clock is calculated by subtracting the previous SCR value of the new value 715 SCR. Then, a local clock reference delta is calculated by subtracting the local pre-clock reference value from the new local clock reference value 720. The clock error is then calculated by subtracting the reference delta from the local clock from the reference delta 725 of the system clock. When the clock error is greater than a predetermined fine adjustment threshold, the controller starts sub-routine 735 for coarse adjustment. When the clock error is less than a predetermined fine adjustment threshold, the controller then determines if the clock error is greater than the 740 BRM resolution. Since the BRM value is a digital value, it has a finite number of values, as described in the description of Figure 4, and can only be set if the clock error is greater than half the resolution BRM. In this exemplary embodiment, the BRM value is adjusted when the clock resolution is greater than the 745 BRM resolution. When the clock error is less than the value of the BRM resolution, the BRM value is not adjusted. After the controller adjusts the BRM value or not, the BRM delta is calculated by subtracting the current BRM value from the BRM value stored in the memory 750. When the BRM delta value is greater than a newly determined BRM threshold, the current BRM value it is stored in memory instead of the previous BRM value stored in memory 760. When the delta BRM is not greater than the new BRM threshold; the driver does not store the current BRM value in memory and the previous BRM value is retained. The controller then returns to the interrupt sub-routine 770. Figure 8 shows a flowchart illustrating an exemplary embodiment of a process for grossly adjusting the BRM of a frequency reference in an integrated receiver decoder (140 in Figure 1). The interrupt routine described in Figure 6 or the fine-tuning routine described in Figure 7 can initiate the coarse adjustment sub-routine in this 805 mode. First, the controller decides whether an appropriate interval has elapsed since the last time the BRM value was calibrated 810. When an appropriate time interval has elapsed, where in this mode, the interval is 1 second, the reference delta of the system clock is calculated by subtracting the previous SCR value from the new value 815 SCR. A reference delta of the local clock is then calculated by subtracting the previous local clock reference value from the new reference value 820 of the local clock. The clock error is then calculated by subtracting the reference delta from the local clock from reference delta 825 of the system clock. When the clock error is greater than a predetermined fine adjustment threshold, in this mode, the threshold is 0, the controller sets the value 835 BRM. When the clock error is less than the clock error threshold, 850 the fine adjustment sub-routine is started.

After the controller adjusts the BRM value, the delta BRM is calculated by subtracting the current value BRM from the BRM value stored in the memory 840. When the delta value BRM is less than the previously determined gross threshold, the sub-threshold 850 is started. fine adjustment routine. After the fine-tuning sub-routine is completed, the sub-routine from which the gross adjustment sub-routine was started is returned to 855. When the gross adjustment threshold is not exceeded, the sub-routine from the When the sub-routine of gross adjustment was initiated, we return to 855. While the present invention has been described with reference to the preferred modalities, it is evident that several changes can be made in the modalities without departing from the spirit and scope of the nvention, as defined by the appended claims.

Claims (15)

1. A method for adjusting the frequency of a local oscillator, characterized in that it comprises the steps of: receiving a television signal; determine a first value from the television signal; and replacing a second value stored in a memory with the first value. The method according to claim 1, characterized in that the step of replacing the second value with the first value is carried out in response to the fact that the first value is different from the second value. 3. The method according to claim 1, characterized in that the step of replacing the second value with the first value is carried out in response to the fact that the first value is greater than 15 parts per million different from the second value. The method according to claim 1, characterized in that the step of replacing the second value with the first value is carried out in response to the fact that the first value is 0.0015% different from the second value. 5. The method according to claim 1, characterized in that the step of determining a first value from the television signal comprises the steps of: receiving a first data packet; receive a second data packet; determining a difference between the information received in the first data packet and the information in the second data packet; and determine the first value in response to the difference. The method according to claim 5, characterized in that the information received in the first data packet and in the second data packet are time references. 7. An apparatus characterized in that it comprises: a memory for storing a first parameter of the oscillator; an input for receiving a television signal comprising the time reference data; and a processing means for determining a second parameter of the oscillator in response to the time reference data and storing the second parameter of the oscillator in the memory. The apparatus according to claim 7, characterized in that the processor replaces the first parameter of the oscillator with the second parameter of the oscillator in response to the second parameter of the oscillator which is different from the first parameter of the oscillator. The apparatus according to claim 7, characterized in that the processor replaces the first parameter of the oscillator with the second parameter of the oscillator in response to when the second parameter of the oscillator is greater than 0.0015% different than the first parameter of the oscillator. The apparatus according to claim 7, characterized in that the processor replaces the first parameter of the oscillator with the second parameter of the oscillator in response to the second parameter of the oscillator being greater than 15 parts per million different than the first parameter of the oscillator . The apparatus according to claim 7, characterized in that the first parameter of the oscillator and the second parameter of the oscillator is a multiplier value of the bit rate. 1

2. A method for updating a digital video signal processor parameter, characterized in that it comprises a processing means for: extracting a first timestamp from a first data packet; extracting a second timestamp from the second data packet; determine the time interval between the first timestamp and the second timestamp; calculate a parameter of the video signal processor based on the time interval; replace the stored video signal processor with the parameter of the video signal processor. The method according to claim 12, characterized in that the parameter of the video signal processor is replaced with the parameter of the video signal processor only in response to the parameter of the video signal processor which is different from the parameter of the video signal processor. video signal processor stored. 14. The apparatus according to claim 12, characterized in that the parameter of the video signal processor is replaced with the parameter of the video signal processor only in response to the fact that the parameter of the video signal processor is greater than 0.001 5% different than the parameter of the signal processor of stored video. 15. The apparatus according to claim 12, characterized in that the parameter of the stored video signal processor is replaced with the parameter of the video signal processor only when the parameter of the video signal processor is greater than 15 parts per second. million different to the parameter of the stored video signal processor.