MXPA01007160A - Interface - Google Patents

Abstract

An interface between base band circuitry and RF transceiver circuitry, particularly relating to the Bluetooth standard. The interface has a plurality of connectors (DBus) for controlling the RF transceiver circuitry including providing control information for changing the mode of operation of the transceiver, said modes including a transmit mode and a receive mode;at least first and second further connectors (RFBus) wherein in the transmit mode, one of said first and second connectors supplies data to the transceiver and the other is operable to perform a first function such as controlling the power amplifier in the RF circuitry and wherein, in the receive mode, one of said first and second connectors receives data from said RF module and the other is operable to perform a second function different from the first function.

Description

INTERFACE DESCRIPTION OF? INVENTION The present invention relates to an interface between a set of baseband circuits and a set of radio frequency transceiver circuits, particularly circuits that operate in accordance with the Bluetooth Low Power Radiofrequency Specification. Additionally it is related to devices that have such an interface and any of the circuit types.

Low-power radio frequency systems allow communication between devices over short distances, typically tens of meters. Each of the devices must be able to receive and transmit according to the system protocol.

A low-power radio frequency system is the Bluetooth system. This system is designed to replace the wire and cable connection with wireless connectivity. For a device to communicate with another device, no wire will be necessary to connect them. Instead, each device will serve a transceiver. A transceiver has a part of baseband and a part of radio frequency (RF). The Ref: 131640 server itself may have processing circuits capable of performing baseband processing and that server will only require RF transceiver circuits to properly connect to that set of processing circuits. It would be desirable to create RF transceiver circuits that can connect to several different servers to provide the servers with wireless connectivity. It would be desirable to standardize the interface in which the connection is made between the set of baseband circuits and the set of transceiver circuits making them independent of the provider and the platform. It would be desirable to have a simple interface between the baseband part and the radio frequency part and in particular to have a reduced number of pins or pins in the interface. A reduced number of pins provides the advantages of a reduced chip area and reduced power consumption due to fewer pin connections. According to one aspect of the present invention there is provided a device according to claim 1. According to another aspect of the invention, transceiver circuits are provided according to claim 21.

According to further aspects of the invention, a method according to any of claims 25 and 26 is provided. Also according to a further aspect of the invention there is provided an interface in accordance with claim 27. Therefore the methods of The present invention provides an interface with a reduced number of pins and a low power consumption. The lowest number of pins arises from: the burst mode controller and the microcontroller both using the data transmission path (DBus); the burst mode controller that uses the DBus for different tasks and the function of the radio frequency transmission path (RFBus) that depends on the operational mode. The burst mode controller controls the critical time tasks in the RF circuits using the DBus and RFBus. DBus is used to control critical weather configurations. The RFBus is used to transfer data and, in transmission mode, to control the power amplifier. For a better understanding of the present invention and to understand how it can be carried out, reference will now be made, only by way of example, to the accompanying tables and figures in which: Table 1 illustrates the signals provided at the interface between the baseband circuitry (BB) and the radio frequency (RF) circuitry; Table 2 illustrates the effect of the operational modes on the signals provided at the interface via the RFBus; Figure illustrates the BB side of the RF-BB interface; Figure Ib illustrates the RF side of the RF-BB interface; Figure is a schematic illustration of an LPRF transceiver illustrating the functionality of the RFBus; Figure 2a illustrates how the RFBus is configured and how the RF chip responds in the control mode; Figure 2b illustrates how the RFBus is configured and how the RF chip responds in transmission mode; Figure 2c illustrates how the RFBus is configured and how the RF chip responds in the reception mode; Figure 3 illustrates how the DBus can control devices in addition to an RF chip of LPRF having the RF circuitry; Figure 4a illustrates the Write Access in the DBus; Figure 4b illustrates the Read Access in the DBus; TABLE 1: SUMMARY OF INTERFACE SIGNALS TABLE 2: MODES OF OPERATION AND THEIR INFLUENCE ON THE DATA INTERFACE DETAILED DESCRIPTION OF THE INVENTION The Figure illustrates the baseband circuitry (BB) 100 having an interface 10. The interface is connected or can be connected to a corresponding interface 10 of a set of radio frequency (RF) circuits 200 illustrated in Figure Ib. The interface '10 has seven pins. The pins 20, 22 and 24 are assigned to the transmission or bus path of the DBus control signals 12 and transfer respectively the DbusDa, DbusEnX and DbusClk signals. The pin 30 is assigned to the latent control signal LatenteX 14. The pins 40, 42 and 44 are assigned to the RFBus 16 data signal transmission paths and respectively transfer the RFBusl, RFBus2 and BBClk signals. The pins of the interface 10 in the circuitry of BB are connected or can be connected to the corresponding pins of the interface 10 of the RF circuitry 200. The DBus 12 has three signal lines associated with the pins 20, 22 and 24. A bidirectional signal line for the transfer of the DbusDa data signal from the circuitry of BB 100 to the RF circuitry 200 or the RF circuitry 200 to the circuitry of BB 100, via the plug 20. A unidirectional signal line for transferring and allowing the DbusEnX signal from the circuitry of BB 100 to the RF circuitry 200, via the pin 22. A unidirectional signal line for the transfer of a DbusClk clock signal from the circuitry from BB 100 to RF circuitry 200, via pin 24. RFBus 16 has three signal lines associated with pins 40, 42 and 44. A bidirectional signal line for transfer e the RFBusl signal via pin 40. A unidirectional signal line for the transfer of the BBClk signal from the RF circuit set 200 to the BB 100 circuit set via the pin 44. A unidirectional signal line for the transfer of the signal. RFBus2 signal from the circuit set of BB 100 to the RF circuit set 200 via pin 42. LatenteX 14 is a unidirectional signal line for the transfer of a LatenteX signal from the BB 100 circuitry for the control of the power descent in the RF circuitry 200. Table 1 illustrates the signals provided in the interface 10 and identifies each of the signals of the interface by its associated interface pin, its name, its address and its function.

DBus The DBus 12 is an input / output data transmission path (I / O) in series. It is a Clock, Data, Permission interface. It is not purely dedicated to the interface 10 between the RF circuitry 200 and the circuitry of BB 100. FIG. 3 illustrates the situation in which the circuitry of BB 100 is integrated in another server system. The circuit set of BB 100 is the Master DBus. In this example the server system is a radiotelephone 300, but it could be a computer or a personal digital assistant (PDA). The DBus 12 communicates with the DBus Slaves. A Slave DBus is the RF circuit set 200 which is connected to the DBus via the interface 10. Other slaves with which it communicates are in the illustrated example Power Supply Management Circuits 310 and the Set of Modulating Circuits of RF 320 for the GSM protocol. The DBus (DbusDa, DbusEnX and DbusClk) is used to control the set of RF circuits and other devices as illustrated in Figure 4. The DBus writes control data to the registers and reads the control data from the registers, in the RF circuitry 200. The registers to which it has been written may include a register which controls the frequency at which the RF chip transmits or receives a register that controls the energy to which the RF chip transmits and register which identifies if the RF chip is in the control mode, transmission or reception. The records that have been read may include a record that contains RSSI information. Therefore the DBus can control the operation of the RF circuitry, for example, the control of the transition from reception to transmission. The circuit set of BB 100 controls access to the DBus. The BB circuitry precedes text of transferred data with a device address, a Read / Write identification bit (R / W) and a registration address. Each device address is of a length of 3 bits that allows access for 8 devices (the set of RF 200 devices and 7 others). The R / W bit when it is LOW indicates that the circuit set of BB is for writing to the addressed register and when it is HIGH indicates that the circuit set of BB is for reading from the addressed register. The address of the register is of a length of 5 bits that allows 32 registers to be addressed. The data text can be of a variable length and can have a practical limit of 32 bits. The 16-bit data texts are preferred to transfer to / from the RF circuit set 200. The address bits and the R / W bit are verified before linking the data to allow the transmission path to share with the devices that are used concurrently for the RF 200 circuitry. The access via the DBus is obtained by taking the LOW DbusEnX with an average clock cycle before the first positive clock margin of the DBusClk. In the first ascending margin of the DbusClk the MSB of the address of the device will be clocked from the DbusDa within the DBus Slave. A write access is illustrated in Figure 4b. To write to the RF 200 circuit set, the circuitry of the DBus Maestro 100 places the data in the DbusDa in the downstream range of the DBusClk. The DBus Slave 200 having verified that it is addressed takes data from the DbusDa in each ascending margin of the DBusClk. The DBus Maestro 100 changes the state of the data in the descending margin of each clock pulse of the DbusClk. Following the 8 bits of address and the R / W bit, the data bits are sent with the same timing as the address bits. After the last bit of data, the allowed DbusEnX line is set to HIGH. Then the clock pulses one more pulse and then keeps it LOW for a minimum of one cycle before a new access is initiated. The allowed DbusEnX is therefore kept HIGH for a minimum of two cycles.

A read access is illustrated in Figure 4a. The DBus Slave when it is being read, places data in the DBusDa in each of the ascending margins of the DBusClk. The data is read from the DBusDa by the DBus Master 100 in each of the descending margins of the DBusClk. During a read access, the addressed device generates data in the DBus so that they can be read by the control device. Next to the 8 bits of address and the R / W bit there is a return bit that lasts a half of the clock cycle and has a realignment effect of the DBus timing so that the addressed device will load bits into the DBus during the ascending margin of the DBusClk. The bits are read in the DBus Maestro 100 in the descending margins of the DBusClk. After the last data bit the DbusClk is disabled for at least one clock cycle before the next access. The length of the data text is not fixed. The DBus Maestro 100 controls the DBusEnX. By convention, the number of data bits in the length of the data text is set for a certain direction.

RFBus Interface 10 has a dedicated pin for the RFBusl signal, a dedicated pin for the RFBus2 signal; and a dedicated pin for the clock signal of the BBClk (13 MHz), used to synchronize the data transferred via the RFBus. The BBClk can also be used for the timing logic of the circuit set of BB 100. The BBClk is generated by the set of RF circuits 200 at 13 MHz for a symbol rate of 1 Mbaud @ 13 times oversampling. The RFBus 16 'is multifunctional. The RFBus is used for the transfer of data received from the RF circuitry 200 to the circuitry of BB 100, for the transfer of data for the transmission of the circuitry of BB 100 to the RF circuitry 200 and the transfer of control data between the circuitry of BB 100 and the RF circuitry 200. The capability of the RFBus to transfer control data is used for different purposes depending on the operational mode of the system. RFBus 1 is bidirectional. In a transmission mode the RFBus 1 provides data to the RF circuit set 200 for transmission. In a Receive Mode the RFBus 2 receives data from the RF circuitry 200. Although in the given examples a simple data signal from the RFBus 1 is illustrated, numerous such data signals may be used to increase in bandwidth. The RFBus 2 is used to control critical time tasks in the RF 200 circuitry. Critical time tasks are tasks that need to be performed on a time scale of less than 1 bit width - (1 μs in Bluetooth) ). The RFBus 2 is fast (13 MHz) in the transmission of control signals from the circuitry of BB 100 to the RF circuitry 200. In the Transmission Mode, the RFBus2 is used to control the timing of the 'Power Amplifier. . In Reception Mode, RFBus 2 is used to control the timing of the change of the DC estimator from a fast data acquisition mode to a slower data acquisition mode. The operational mode of the system is determined by the circuitry of BB 100. The circuitry of BB indicates a change of mode for the RF circuit set 200 via the DBus. Modes include Transmission Mode, Reception Mode and Control Mode.

Interface of the BB circuitry The circuitry of BB illustrated in the Figure has the interface 10 previously described, aionally has a Serial Control Interface 110, a Burst Mode Controller (BMC) including a Timing Control Unit 130, a microcontroller 140, a latent mode controller 150 and a clock distribution circuitry (CDC) 160. The Serial Control interface 110 provides the DBus in the plugs 20, 22 and 24. The Burst Mode Controller 120 provides RFBus 1 at pin 40 and RFBus2 at pin 42. The Latency Mode Controller provides LatencyX at pin 30. The Clock Distribution Circuit Board 160 it is connected to the plug 44 of the interface 10 and receives the BBClk from the RF circuitry 200. The CDC 160 provides clock signals derived from the BBClk for the BMC 120, from the microcontrollers 140 and from the Serial Control Interface 110. The Serial Control Interface 110 is controlled to produce the DBus by the microcontroller 140 or the Burst Mode Controller 120. The Burst Mode controller controls the DBus when critical time settings are made for the RF circuit set 200 If the microcontroller 140 or the BMC 120 controls the content of the DBus, it is determined by a switching signal 142 provided by the microcontroller 140 for the Serial Control Interface 110. The BMC 120 Data information 122, address information 124 and information from R / W 126 to the Serial Control Interface 110 that places this information in the correct serial format in the DbusDa. The DbusClk clock signal (13 mHz) is received from the Clock Distribution circuitry. The timing of the transitions in the DbusEnX Permission signal is controlled by an Activation signal 132 provided by the Timing Control Unit 130 in the BMC 120. The Burst Mode controller 120 controls the contents of the RFBusl and RFBus2 and can additionally control the content of the DBus. It directly provides the RFBus2 to the plug 42 and provides the RFBusl to the plug 40 in the Transmission Mode and receives the RFBusl from the plug 40 in the Receive Mode. The microcontroller can access the DBus and then the RF circuit set via the Serial Control Interface. When the DBus is controlled by the microcontroller, no critical time task can be controlled via the DBus. This configuration is used in the boot phase or for the RSSI measurement. When the BMC 120 controls the DBus, it is possible to control critical time tasks via the DBus. The ability of the BMC 120 to control the critical time tasks via the DBus depends on the resolution of the activation signal 132 which is at least lμs. The control signals sent by the BMC 120 via the RFBus2 can have an even higher resolution if they are directly timed by the BBClk @ 13 MHz.

RF Circuitry Interface Figure Ib illustrates the RF circuitry 200 which has an interface 10. The interface has pins 20, 22 and 24 dedicated respectively to the DBusDa, DBusEnX and the DBusClk, the pin 30 dedicated to the LatenteX and pins 40, 42 and 44 dedicated respectively to RFBusl, RFBus2 and BBClk. The RF circuitry 200 includes a Control Interface 210; a set of registers 220 that illustratively includes registers 222, 224 and 226; decoding circuits 230; a negation gate (NOT) 232; a gate of two inclusion entries (AND) 234; a gate of three alternative inputs (OR) 236; a set of power supply regulating circuits 240; a reference oscillator 250; a switching circuit 260; a Transmission Path 270 and a Reception Path 280. The Control Interface 210 has an input interface 212 connected to the DBus and an input 214 for the reception of the Latent X. It has an output 216 for supplying a control signal of mode the input of the decoding circuitry 230 and the control input 262 of the switching circuitry 260 and an interface 218 for accessing a record set 220. The interface 210 receives the DBus and performs the appropriate action which may involve writing to a register or reading a register and changing the operation mode of the RF 200 circuit set. By writing the appropriate registers the Control Interface 210 can control the operational mode of the RF 200 circuit set, control the frequency synthesizer in the Tx or 'Rx trajectory, control whether the RF circuitry should receive or transmit, and control the power to which it should to transmit the trajectory Tx 270. By reading from the appropriate registers the information concerning the received signal quality such as RSSI can send by means of the Control Interface 210 to the circuit set of BB 100. For simplicity of illustration the operational connections of the Rx Path 280 and the Tx Trajectory 210 with the record set 220. A two-bit signal is provided at the output 216 indicating the operational mode - [10] indicates Reception Mode, [01] indicates Transmission Mode and [11] indicates Control Mode. The switch circuitry 260 has an input 262 connected to the output 216 of the Control Interface 210, a single primary interface and three secondary interfaces. The primary interface has a port connected to the plug 40 to transfer the RFBusl and another port connected to the plug 42 to transfer the RFBus2. One of the secondary interfaces is connected at any time to the primary interface depending on the signal received at the input 262. When the signal at the input 262 indicates Control Mode a port 264 of a first of the secondary interfaces is connected to the plug 40 via switch circuitry 260. Port 264 is connected to an AND gate gate. When the signal at input 262 indicates Transmission Mode, a port 266 of a different one of the secondary interfaces is connected to pin 40 via switch circuitry 260 and the other port 267 of that secondary interface is connected to pin 42. via the switch circuitry 260. When the signal at the input 262 indicates Reception Mode, a port 268 of another of the secondary interfaces is connected to the plug 40 via the switch circuitry 260 and the other port 269 of that secondary interface is connected to pin 42 via switch circuitry 260. Ports 266 and 267 and 268 and 269 are connected to Path Tx 270 and Path Rx 280 respectively as illustrated in more detail in the Figure. . The set of decoding circuits 230 has a width of 2 bits connected to the output 216 of the Control Interface 210 and provides its output to an input of the AND gate 234 and, via gate NOT 232, to an input of gate OR 236. The set of decoding circuits 230 produces a HIGH output when the signal received at its input identifies the Control Mode and on the contrary, a LOW signal. The OR gate receives an input via the NOT 232 gate as described, another input from the pin 30 which receives the LatenteX and a final input from the output of an AND gate 234. The output of the OR gate 236 is provided as a wait control signal to the Power Supply Regulation Circuitry Assembly 240 and to the Reference Oscillator 250. A LOW output of the OR gate 236 places the Power Supply Regulation Circuitry Assembly 240 in a standby state of consumption low-power switch and turn off the Reference Oscillator 250. The Reference Oscillator 250 provides its output to pin 44. Its output is also used anywhere within the RF circuits, but this is not illustrated for purposes of clarity. The figure illustrates the control carried out in the Tx 270 trajectory during the Transmission Mode and the control carried out in the Rx 280 trajectory during the Reception Mode. The Transmission path 270 includes the Pulse Formation Circuitry Assembly 272 which receives an input from port 266 of the switching circuitry 260 in the Transmit Mode and does not receive an input in the contrary manner. The output of the Pulse Formation Circuitry Assembly 272 is provided as an input to the Modulation Circuitry Assembly 274 which provides the modulated signal to the Power Amplifier 276 for amplification and subsequent transmission via an antenna. The Power Amplifier 276 has a control input by which the gain of the amplifier can be forced to rise or descend. This control input is connected to port 267 of switching circuitry 260. The power amplifier can therefore be turned on or off. Reception path 280 includes the Frequency Declination Conversion Circuit Assembly 286 which receives an antenna input in Reception Mode. The circuits 286 convert the received signal to a lower frequency and provide it to the Demodulation Circuitry Assembly 284. The demodulated signal is provided to the DC estimation circuits 282. The amplitude data output decided by the estimation circuitry. of DC 282 is supplied to port 268 of switching circuitry 260. The DC Estimation Circuitry Assembly 282 has a control input connected to port 269 of switching circuitry 260. The signals provided in the control input determines whether the DC Estimate operates in the fast mode or in a slow mode.

Operational Modes In Transmission Mode, as illustrated in Figure 2b, RFBusl and RFBus2 are driven by the circuit set of BB 100. RFBusl supplies digital data for transmission < TXDATA > from the circuitry of BB 100 to the RF circuitry 200 via the plug 40. Logic levels are used and the pulse formation is performed entirely on the RF circuitry 200. The RFBus2 controls the timing of the power rise in the Power Amplifier (PA) in the RF circuitry 200 using the control signal < PAON > . When RFBus2 = < PAON > = HIGH the Power amplifier is on, when RFBus2 = < PA0N > = BAJ0 the Power Amplifier is off. Turning the Power Amplifier on and off is "time critical" when it must be controlled on time scales of less than 1 bit in duration (1 μs for the Blutooth 1.0 Specification). In the Reception Mode, as illustrated in Figure 2c, the RFBusl is directed by the RF circuitry 200 and the RFBus2 is directed by the circuitry of BB 100. The RFBusl supplies the received data. </ RTI> RXDATA > to the circuit set of BB 100 via pin 40. The RFBus2 controls the DC estimate on the RF 200 set of circuits via pin 42. The change of the DC estimate is "critical of time" when occurring on a scale of less than 1 segment duration. < DCTRACK > = LOW causes the use of a quick acquisition of a DC estimate that is typically used at the start of a received packet and < DCTRACK > = HIGH controls the use of a DC estimate which is typically used for the rest of the package. The change of the DC estimate is "time critical" which must be controlled in time scales of less than 1 bit in duration (lμs for the Bluetooth 1.0 Specification). The Control Mode is the neutral mode entered when neither the Transmit Mode nor the Receive Mode are active. It is entered when LatenteX is LOW or via a control text in DBus. In this mode, as illustrated in Figure 2a, RFBusl and RFBus2 are driven by the circuitry of BB 100: RFBus2 does not have an assigned functionality; RFBusl = < ClkON > . When RFBusl = < ClkON > = HIGH, AND gate 234 turns ON (ON) the Reference Oscillator 250 and the Energy Supply Regulation Circuitry Assembly 240. When RFBusl = < ClkOn > = LOW, gate AND 234 turns off (OFF) the Reference Oscillator 250 and places the Power Supply Regulation Circuitry Assembly 240 in standby. The RF circuitry is placed in a low power mode. There is no activity in the DBus and the RFBus and the BBClk is turned off. It will therefore be appreciated that the RFBus is used for different purposes during different operational modes of the system, as illustrated in Figures 2a, 2b, and 2c and in Table 2. The operation of the LPRF device is described in detail in the Patent Application of the United Kingdom No. 9820859.8, the content of which is incorporated herein by reference. In particular 1 Figure 4 shows the RF components of the LPRF of a transceiver (Tx, Rx and Frequency control), connected to baseband components (the remaining elements in the Figure). In the above described embodiment, the reception path 280 was divided in such a way that the DC Estimation circuitry 282 was in the RF Circuitry Assembly 200. This results in the RFBusl, during the reception mode, the RxData data transfer from RF Circuit Set 200 to circuit set BB 100 through interface 10 and RFBus2 by transferring a control signal, DcTrack, from circuit set BB 100 to RF Circuit Set 200 through the interface 10. This division of the reception path is not essential. In a second contemplated embodiment, the DC Estimation circuitry 282 is located within the baseband circuitry 100. This results in RFBus2 with a different directional flow than described above in the receive mode. In the second embodiment, the DCTrack signal is completely within the circuit set of the baseband 100 and is not provided in the interface 10. The analog demodulator output 284 is converted to a digital signal for example by a sigma-delta converter whose outputs are assigned to the RFBus 1 and RFBus2. Consequently, in this embodiment, the data flows both in the RFBusl and in the RFBus2 from the RF circuitry 200 to the baseband circuitry 100 via the interface 10 during the reception mode. Additionally, it is contemplated that the RF circuitry as described in the first embodiment may have additional circuits that allow its functionality to change to operate in accordance with the second embodiment. Additionally it is contemplated that the circuitry of BB as described in the first embodiment may have additional circuits that allow its functionality to change to operate in accordance with the second embodiment. The present invention includes any novel feature or combination of features described herein either explicitly or implicitly or any generalization thereof. In view of the above description it will be apparent to a person skilled in the art that various modifications can be made to the above description without departing from the scope of the invention. It is noted that in relation to this date, the best method known by the applicant to carry out the aforementioned invention is that which is clear from the present description of the invention.

Claims (27)

2. Having described the invention as above, the content of the following claims is claimed as property. 1. A device that has an interface for the control of a set of radio frequency transceiver circuits, the interface characterized in that it has: numerous connectors for the control of the set of radio frequency transceiver circuits including the provision of control information for the change of the Transceiver operation mode, said mode includes a transmission mode and a reception mode; at least one first and second additional connectors wherein in a first mode, one of said first and second connectors provides data to the transceiver and the other is operable to perform a first function and wherein, in the second mode, one of said first and second second connectors receives data from said RF module and the other is operable to perform a second different function. A device according to claim 1, characterized in that said first function is the provision of a first control signal to said transceiver.
3. 3. A device according to claim 2, characterized in that the first control signal is a critical time control signal.
4. 4. A device according to any of the preceding claims, characterized in that the first function controls the power amplifier of the transmitting portion of the transceiver.
5. 5. A device according to any of the preceding claims, characterized in that said second function is the provision of a second control signal to the transceiver.
6. 6. A device according to claim 5, characterized in that the second control signal is a critical time control signal.
7. 7. A device according to any of the preceding claims, characterized in that the second function controls the estimation of the data received by the receiving portion of the transceiver.
8. 8. A device according to any of claims 1 to 4, characterized in that said second function is the data reception of the transceiver.
9. 9. A device according to any of the preceding claims, characterized in that the first connector is bidirectional and supplies data in the first mode and receives data in the second mode.
10. 10. A device according to any of the preceding claims, characterized in that the critical time control signals are not provided via said numerous connectors.
11. 11. A device according to any of the preceding claims, characterized in that the first mode is a transmission mode for the transceiver.
12. 12. A device according to any of the preceding claims, characterized in that the second mode is a mode of reception of the transceiver.
13. A device according to any of the preceding claims, characterized in that the numerous connectors include a connector for data transfer from and for the device, a connector for the provision of a device enabling signal and a connector for the provision of a device clock signal.
14. A device according to any of the preceding claims, characterized in that the numerous connectors are used to read from and write to the registers in the transceiver.
15. A device according to any of the preceding claims, characterized in that the numerous connectors of a serial interface having at least one connector through which serial data are transmitted, said data include a device address, a bit indicating if the data is for writing or reading, a local address and a variable data portion.
16. 16. A device according to any of the preceding claims, characterized in that it additionally comprises a first set of control circuits and a processor, wherein the first set of control circuits is arranged to control the radiofrequency circuits via the numerous connectors and / or the first and second additional connectors and the processor are arranged to control radio frequency circuits only via the numerous connectors.
17. 17. A device according to claim 15, characterized in that the data portion can have a length varying between 1 and 32 bits.
18. 18. A device according to any of the preceding claims, characterized in that the numerous connectors are connected to at least one other device.
19. 19. A device according to any of the preceding claims, characterized in that it additionally comprises a connector for receiving a transceiver clock signal.
20. 20. A device according to any of the preceding claims, characterized in that it has a third connector (LatenteX) for the reduction of energy in the components of the transceiver.
21. 21. A set of transceiver circuits with an interface for connection to a device having baseband circuits, the interface characterized in that it has: numerous connectors to provide control information for changing the operating mode of the transceiver, said modes include a mode of transmission and a mode of reception; at least one first and second connectors wherein in a first mode, data is received in one of said first and second connectors and the other performs a first function and wherein, in the second mode, the data is provided in one of said first and second connectors to transfer to the device and the other performs a second function different from the first.
22. 22. The set of transceiver circuits according to claim 21 with a power amplifier, characterized in that the first function is the reception of a first control signal for the control of the power amplifier.
23. 23. The set of transceiver circuits according to claim 21 or 22 having a set of DC estimation circuits, characterized in that the second function is the reception of a second different control signal for the control of the set of circuits for estimation of .
24. 24. The set of transceiver circuits according to claim 21 or 22, characterized in that the second function is the provision of received data.
25. 25. A method for establishing an interface of a device having a set of baseband circuits with a set of transceiver circuits, the device having means for controlling when the transceiver is in a transmission mode or in a reception mode and first and second connectors, characterized in that it comprises the steps of: controlling the transceiver to enter the transmission mode; provide data from the device to the transceiver via the first connector; and control of the power amplifier in the transceiver via the second connector.
26. 26. A method for establishing an interface of a device having a baseband engine to a transceiver, the device having means for controlling when the transceiver is in a transmission mode or a reception mode and first and second connectors, characterized because it comprises the steps of: controlling the transceiver to enter the reception mode; reception of data in the transceiver device via the first connector; and control of the estimate of in the transceiver via the second connector.
27. 27. An interface, characterized in that it has connectors that include a first connector arranged to transfer a signal for the control of critical time functions and a second connector arranged to transfer data, said critical time function is dependent on whether the second connector is receiving or providing data.