MXPA01001289A - Interface circuit and method for transferring data between a serial interface and a processor - Google Patents

Abstract

The invention relates to an interface circuit for transferring data from and to a processor via a serial interface, wherein a FIFO memory is disposed between the serial interface and the processor. The invention also relates to an appropriate method for transferring data, wherein said data is received serially bitwise, stored in the memory and read therefrom bytewise by the processor or written bytewise in the memory by the processor and then transmitted bitwise therefrom.

Description

INTERFACE CIRCUIT AND PROCEDURE FOR THE TRANSMISSION OF DATA INTO A SERIAL CUTTING POSITION AND A PROCESSOR FIELD OF THE INVENTION The present invention relates to an interface circuit for data transmission through a serial cutoff position to and from a processor and a method for data transmission between a serial cutoff position and a processor. The present invention should serve for the transmission of wireless data in series to for example a processor arranged on a chip card. The present invention is especially suitable for wireless data transmission between a card reader and a chip card with a contactless processor. In these cases of application the processor must be downloaded with which, a slowly pulse-driven processor can be used. In this way the current expenditure must be reduced (in current processors, it is the current expenditure proportional to the pulse frequency). In addition, the processor must be connected as often and as long as possible in the so-called latent mode in which the processor does not work and therefore consumes essentially less current. According to the current state of the art, data transmission is carried out between a serial cut-off position and a processor by means of a parallel-serial or series-parallel transformation, through a so-called UART (U iversal Asynchronous Treceiver Transmitter) receiver and universal asynchronous transmitter. This is usually done by means of a shift register on the one in which, for example, the transceiver of a wireless transmission is connected. This shift register can be written or read in the form of bits corresponding to the reception or the emission. The processor must collect or make available on the other side of the UART the data parallel and synchronously in time to the data transmission protocol used (see figures 1 and 2). This represents high demands on the processor's real-time capacity. Such high demands on the real-time capacity of the processor are in contradiction to the requirement that the processor must spend as little energy as possible and that it must be as cheap as possible. Exactly in chip cards without contact should be able to use processors that are driven by pulses as simply as possible and as slowly as possible and therefore spend very little current and are very cheap. Such processors can not fulfill among others the demands of real time. Therefore, currently in the state of the art a contactless chip card is used in which the serial information in the form of bits from the processor is removed from the connection of the serial cutoff position or written to the connection of the cutting position in series. This task, however, requires a lot of computing time for the processor, so that again the need to use a faster processor is presented. SUMARr? OF THE INVENTION It is therefore the task of the present invention to present an interface circuit for the transmission of data to you birds from a serial cut-off position from and to a processor in which the data transmission can be performed without the processor be loaded with it. It is also the task of the invention to present a suitable method for the transmission of data between a serial cutting position and a processor. According to the invention, this task is solved by means of an interface circuit in which a memory is arranged for various word lengths of., Bus or of the processor (for example bytes) between the cut-off position in series and the processor. . the task is also solved by a procedure in which the data is received serially in the form of bits and read in the memory and the processor are returned in the form of bytes and the processor in the form bytes are written into the memory and then sent in the form of oits. Here, it is especially preferred that the memory be able to read or write in the form of words or bits, for which it is especially preferred that the memory has a read and write pointer that each bit or word (example byte) can individually address. For greater current saving it is advantageous that the processor is available with a minimum current expenditure by means of a current saving mode (latent mode). It is also advantageous to install a comparator in the memory in this way, the processor can download more. Preferably, the comparator can include a simple logic that automatically compares each bit received or captured with the contents of the memory cell in the memory, on which the bit received must be written. For greater simplicity of the circuit, the memory can be integrated in the CPU module or in the receiver module. Further simplification of the circuit is also possible so that the memory is performed by RAM cells from the normal RAM in the address area of the processor.

For further discharge of the processor, a verification addition module can be additionally provided to the memory. In addition to the verification addition module, a comparator can still be provided which compares the sum of the verification with the received data with a pre-calculated verification amount that is expected. This way the processor can download more. Preferably, the memory can be in the form of an annular structure, and / or provided with an overdrive detection device which, in the event of a threatening overdrive of the memory, activates or awakens the processor. With this data loss can be avoided by overwriting the memory. In the process according to the invention, it can preferably be provided for the discharge of the process! that the write and read pointer of the memory, automatically be established without processor activation. An essentially greater flexibility of the programming, it offers a procedure in which the processor can freely establish the reading and writing pointer of the memory. Still a greater technical flexibility of programming, it is offered by the procedure in which the processor handles the 3 individual memory cells of the memory as constituent parts of the own address area and with this it can read and write it freely selecting it '. Another processor download can be performed by providing an automatic data comparison where the data to be expected must be stored in the corresponding position in the memory and by means of a simple logic each received bit is compared with the contents of the memory cell in the memory on which it is written. Here you can preferably offer the write pointer of the memory, as well as the address of the expected bit with which it should be compared, as well as the address of the received bit that should now be written into the memory. This way there is a simplification of the programming and the circuit structure. Here, after the comparison of all the bits of a byte, it is preferable to set a bit to 0 coordinated to that byte. If all the bits were equal while, if not set to 1. This is especially preferred if the coordinated bits can be accessed in the form of bytes from the processor by unmasking the comparison information can be quickly and easily evaluated a new sequence received bit.

Preferably, the processor can be switched during data transmission to a current saving mode (a latent mode). Here it is especially preferred that the processor be activated or awaken before a threatening memory envelope. Instead of the comparatively complicated comparison of the individual bits, an automatic data comparison can also be provided, where automatically a test sum of the received data is compared to a previously calculated sum of the data to be expected. In this way, the processor can be downloaded over another time in which the comparison, for example the serial number of the contactless chip card, takes place automatically and without support by the processor during the reception of data. With the present invention it is also possible to work with protocols that allow the transmission of fractional parts of a byte (for example, only 3 bits). Both the application of multi-word memories in serial interface of chip cards, as well as the use of such switches and automatic comparison procedures, in combination with a CPU have not been known so far. DESCRIPTION OF THE DRAWINGS The invention will now be explained in detail with reference to the embodiments represented in the attached drawing. Where it shows: Figure 1, the state of the art with the serial transmission between the receiver module and the processor module. Figure 2, the state of the art with connection of the reception module to the CPU bus. 3 shows a solution according to the invention with serial transmission of the data between the reception module and the processor module. Figure 4, a solution according to the invention with connection of the receiver module to the processor bus. Figure 5, a FiFo memory according to the invention with a comparison circuit to test the correction of the expected data. Figure 6, a representation in principle of the First-in-First-out memory (the first one that enters is the first one that comes out). Figure 7, a comparison of data according to the intention with the formation of a test sum. Figure 8, the formation of the test sum in parallel to the loading of the data in the First-in-First-cu memory.

DESCRIPTION OF THE INVENTION. Figures 1 and 2 show once again the problems of the state of the art, or the receiver 10 can be connected by a serial connection 12 with the processor module 14 in which a UART is then provided with an asynchronous receiver and emitter circuit universal. Another solution in the state of the art has a receiver module 20 which in itself carries the UART circuit and then by means of the data bus 22 of the processor 24 is connected to it. Figures 3 and 4 show, on the contrary, the solution according to the invention. In FIG. 3, a receiving module 30 is again found using a cutting position in series. Through the serial connection 32, the receiver module 3U is connected to the processor module 34. However, instead of the UART circuit, a First-m-First-out memory is provided in the processor module 34. Instead of the UART circuit, a First-in-First-out structure with, for example, 32 bytes is used. This is how data is written in the form of bits in the First-in-First-out memory in case of data reception. As soon as one byte is met, the next byte is automatically filled into the First-in-First-out memory until the data block is terminated. The emission is carried out analogously to the reception, that is, the data is read from the First-m-Fist-out memory in the form of a bit, byte to byte. Both the receiver and the transmitter process can run independently of the processor (CPU), preferably the processor can be located here in a latent mode (a current saving mode with negligible current consumption) .The processor can read the contents of the memory. F rst-in-First-out in sequence in the form of a byte or register it in the form of a sequence in the form of bytes With the help of a reading pointer and a writing pointer it is possible to direct each bit to the memory First -m-First-out individually, this way incomplete bytes can also be retired or received, for example only 3 bits, simultaneously the demands on the capacity of the current time of the processor, which in the solution according to the state, become negligibly insignificant. of the technique with a UART circuit.Alternatively to a First-m-First-out memory, you can also use a Last-m-First-out memory (LiFo, last in - first to leave). Here only the serial succession of the data received and issued is reversed. This may be necessary for programming or even desirable. The following solutions are clear that they can be used analogously for a Last-m-First-out memory.

The first-in-first-out memory is also integrated into the CPU module in the present embodiment, according to FIG. 3. The First-m-First-aut memo can then be made up to RAM cells from the working memory Normal RAM in the address area of the processor (for example in the internal RAM). With this? Or no additional memory circuits are needed. Figure 4 shows another embodiment of the invention. Here the First-m-First-out memory is integrated in the receiver module 40. This is then connected to the data bus of the processor 42 with the processor module 44. Both in the embodiment of the invention according to FIG. , as well as the embodiment of Figure 4, it can be provided that the First-m-First-out memory can only be written and read in sequence from the CPU processor. A free selection access of the processor to the First-m-First-out memory is eliminated. This leads in an important way to the data security c if it is to avoid that an application in the form of manipulation tries to change the data of another application. An essentially more flexible programming is without embarking possible, if the processor can be established freely 'to the writing and reading pointer of the First-in-First-ou memory. With this you can also influence which position (to the bit exactly) the processor read or write in parallel as well as in which position (or place the bit exactly), the wireless interface read or write in series. Another increase in the flexibility of access is allowed by the processor considering the individual bits of the First-in-First-out memory as constituent parts of its logical address area and the latter can read or write freely selectable independently from the pointer of writing or reading. This solution is suitable especially in relation to the realization of the First-in-First-out memory by means of physical RAM cells from the processor's normal working memory. In each of the described embodiments of the First-in-First-out memory, a switch circuit in the First-in-First-out memory or an automatic checksum test can additionally be provided. In addition to the First-in-First-out memory, it is also possible to provide a switching or UART circuit according to the state of the art, in order to be able to work for example long protocols (in a First-in-First-out memory of 32 bytes per example 40-byte protocols) in a conventional manner. It is especially preferred to organize the First-m-First-out memory in the form of an annular structure. Then the processor can be activated or awakened by a threatening envelope of the First-m-First-out memory, whereby these data work from the First-m-First-out memory. If necessary, the First-m-First-out memory can also function as a "classic" UART switching of the state of the art. The First-m-First-out memory can also be realized, obviously with processors without current saving mode. For the additional discharge of the processor, an automatic comparator can be realized in the interface circuit. In this way the processor is downloaded from the task of comparing the received data with expected data (for example for authentication). According to the invention, these tasks are performed by means of a memory F. rst-m-First-out with comparator installed, as this is represented in figure 5, in this way can the power requirements be further decreased in the processor and with this the current expenditure. It is also possible, if necessary, to use a processor of a convenient price.

The switching or comparison circuit shown in FIG. 5 requires the expected data, for example, a serial number or a pass word in the memory F Lrst-m-First-out. A simple logic 50 automatically compares each received bit (New Bit, 2) (New Bit 2) with the contents of the memory cell 41 in the First-m-First-out memory 52, on which it must be written. This serves the write pointer 53 as well as the address of the expected bit 1 with which it should be compared, as well as the write position of the received bit 2, which must now be written into the memory First-in-First-out . { - 3) . The new bits are provided with the sending unit - Receiver RFI (Radio Frequency Interface) (Interface of Radio Frequency). After all the bits of a byte are compared and have been written to the First-m-First-out memory, if all the bits were equal, a bit coordinated to that byte is set in a special comparison register 54 in 0, otherwise that bit is set to 1. The function e then the next, if the register 54 is set to 0 before the beginning of the comparison operation, and the logic 50, as soon as the state of an old bit? enter the new bit, the corresponding memory cell of register 54 that sets i. The next bit byte is then continued until the data block has been deleted. In the record content 54 thus the comparison information, can be accessed from the processor in a byte fashion. By unmasking the comparison information, a new received sequence of bits can be evaluated quickly and simply. In general, this comparison circuit can also be implemented in conjunction with a circuit or UART switching according to the state of the art. In this way, an automatic comparator without Fist-in-First out memory can also be realized. The main function of a First-in-First-out memory (first to enter - first to exit) is represented in Figure 6. The First-m-First-out memory consists of a series of memory cells that are cyclically directed during a read pointer and a write pointer. When writing to the First-in-First-out memory, the value to be described in the position in which the write pointer points or displays is written and the write pointer is incremented in one position. In the reading, it is proved that the writing pointer is different from the reading pointer. As long as the value of the memory cell in which the reading pointer is displayed is read, the read pointer will be incremented. If the read pointer is equal to the write pointer, then the First-m-First-out memory is empty. This is determined by means of a corresponding difference difference 62, then either the value 0 is returned or the communication is returned that a reading is not possible. Since the switching differs! 62 Thus always gives the number of bits in the First-in-First-out memory, this switch or circuit can also be used to activate the processor before an over-run of the First-in-First-out memory and allow the elaboration of data with which, it is recreated in the First-in-First-out memory. Another possibility according to the invention for data comparison consists in the automatic adjustment of a test sum (checksum) of the received data, for example according to the CRC procedure that is compared with a previously computed test sum. (for example during the initialization) of the expected data; this procedure however is not as efficient as the comparator described in figure 5, in the First-m-First-out memory since the checksum of the received data and the expected data of the processor must be compared. This loads the processor again. In addition, there can at least be one bit failure per data block with which this will be recognized in a secure manner. In addition, it is logical to differentiate between data and orders-, otherwise the sum of proof of the data received under certain circumstances would be formed through other orders, thus the sum of the test of the expected data. This is represented individually in Figures 1 and 1. From the expected data, the CRC test sum is computed. This consists of bytes. Then the sums of evidence are formed from the data received also according to the CRC procedure. They should then only compare CRC test sums of length of two bytes, and not all of the data. The comparison of these CRC test sums from two bytes is essentially faster than comparing all the data. The test sums of the expected data may already have been calculated much earlier. As shown in figure 8 there is also the possibility of entering First-m-First-out memory and a checksum logic. This generates in the current time of the checksums, so that the processor in the present time only the little calculating time necessary for the comparison of the checksum still has to work, in this way it can by the addition of a First-m-First-out memory as well as in the case of a comparator or a test sum generator which automatically forms a test sum by means of the data received, considerably unloading to the processor in comparison to the usual UAR concept . In this way the frequency can and with this the current cost of the processor can be very low. Low current consumption means a contactless chip card with a particularly large range. It is especially preferred that a processor be used which, during the reception emission or while it is not occupied, is put into a current saving mode. The processor can for example, if finished with the preparation for the transmission / reception, switch to the current saving mode until the transmission / reception ends, then the necessary energy of the processor can be saved or be available to the emission hardware. and reception. In addition, during charging operation, no charging points are presented from the processor over the wirelessly transmitted signal. A low current consumption and a favorable energy distribution on the chip card, as well as a favorable signal behavior, produce a large amplitude of range. In addition, the emission function can also be controlled in time so that it is switched off while the processor is in the current saving mode. In the same way an "Autoreceive function" can be carried out, this is an automatic reception function, here you can use the processor power saving mode after the transmission to automatically switch to reception operation without having to activate the processor.

Claims (26)

1. NOVELTY OF THE INVENTION Having described the invention as above, the content of the following CLAIMS is claimed as property. i. Interface circuit for the transmission of data through a cut-off position in series from and to a processor, characterized in that only one memory is arranged for several word lengths of bus or processor 'between the cut-off position in series and the processor- , where in the memory you can write or read in the form of words or bits. Circuit according to claim 1, characterized in that the memory, especially of the first-in-first-out type, can be written or read in the form of words or bits. Circuit according to claim 2, characterized in that the memory has a write pointer and a read pointer that can be directed individually between each bit or word, for example each byte. Circuit according to claim 1, 2 or 3, characterized in that the processor by means of a current saving means is available with a minimum current consumption. 5. Circuit according to claim 2, 3 or 4, characterized in that a comparative is installed in the memory.:. Circuit according to claim 5, characterized in that the comparator includes a simple logic that automatically compares each received bit with the contents of the memory cell in the memory on which the received bit is to be written. Circuit according to one of claims 1 to 6, characterized in that the memory is integrated in the CPU module. Circuit according to one of claims 1 to 6, characterized in that the memory is integrated in the reception module. Circuit according to one of Claims I to 6, characterized in that the memory is carried out by RAM cells from the normal RAM in the address area of the processor. Switching according to one of Claims 1 to 9, characterized in that, in addition to the memory, a check sum module is provided. 11. Circuit according to claim 10, characterized in that in addition to the check sum module a comparator is provided that compares the checksum of the received data with the pre-calculated check sum that is expected. Circuit according to one of claims 1 to 11, characterized in that the memory is made in the form of an annular structure. 13. Circuit according to one of claims 1 to 12, characterized in that the memory is provided with a device that detects the overcurrent which activates the processor in a threatening memory envelope. 14. Procedure for the transmission of data between a cutting position and a processor, characterized in that the data is received in the form of a bit and read into the memory and from the processor are read again in the form of byte or processor in the form of byte they are written in the memory and from there they are read in the form of a bit. Method according to claim 14, characterized in that the processing memory - can only be written and read in sequence when the pointer of the writing and reading of the memory has been automatically set without processor load. 16. Method according to claim 14, characterized in that the processor can set the pointer of the read and write memory free. 17. Method according to claim 14 or 16, characterized in that the processor treats the memory cells of the memory as constituent parts of the address area itself and with this it can write and read in free selection. Method according to one of the claims 14 to 17, characterized in that an automatic data comparison is provided where the expected data must be stored in the corresponding positions in the memory and by means of a simple logic each received bit is compared with the contents of the memory cell in the memory on which it is written. 19. Method according to claim 16, characterized in that the write pointer of the memory produces the address of the expected bits with which it is to be compared as well as the address of the received bits, which must now be written into the memory. Method according to claim 18 or 19, characterized in that after the comparison of all the bits of a byte a bit is set to 0 coordinated to that byte, if all the bits were equal if or, it would be set to 1. 21. Method according to claim 20, characterized in that the coordinated bits can be accessed from the processor in byte tor. 22. Accessing procedure with one of the claims 14 to 21, characterized in that the processing] is switched during the transmission of data to a current saving mode. 23. Procesoimiento according to claim 22, characterized in that the processor is activated in a threatening memory envelope. Method according to one of claims 14 to 17, characterized in that an automatic data comparison is provided where automatically a test sum of the received data is compared with a previously computed test sum of the expected data. 25. Method according to one of claims 22 to 24, characterized in that the data transmission can be introduced controlled in time from the memory, without the processor thereby activating. 26. Method according to one of claims 22 to 25, characterized in that after the data transmission it can automatically switch to reception operation without the processor having to activate it.