MXPA01001034A - Hardware-efficient transceiver with delta-sigma digital-to-analog converter - Google Patents

Abstract

A hardware-efficient transceiver. The transceiver (80) includes a digital circuit for converting baseband signals to intermediate frequency signals. A signal source provides a first periodic signal of a first frequency. A direct digital synthesizer (84) provides a second periodic signal of a second frequency from the first periodic reference signal. An upconverter circuit digitally upconverts the baseband signals to digital intermediate frequency signals using the second periodic signal. A digital-to-analog converter converts (82) the digital intermediate frequency signals to analog intermediate frequency signals using the first periodic signal.

Description

TRANSCEIVER OF EFFICIENT PHYSICAL COMPONENTS WITH DELTA-SIGMA CONVERTER FROM DIGITAL TO ANALOG BACKGROUND OF THE INVENTION I. FIELD OF THE INVENTION This invention relates to communication systems. Specifically, the present invention relates to transceivers used in communication networks.

II. Description of the Related Art Cellular telecommunications systems are characterized by a plurality of mobile transceivers in communication with one or more base stations. Each transceiver includes a transmitter and a receiver. In a typical transceiver, an analog radio frequency (RF) input signal, received by an antenna, is converted down an RF section to an intermediate frequency (IF). The signal processing circuits perform noise filtering and adjust the magnitude of the signal via the automatic gain control (AGC) circuitry, analog. An IF section then mixes the signal down to the baseband and converts the analog signal to a digital signal. The digital signal is then input to a baseband processor for further processing of the signal to produce speech or data. Similarly, the transmitter receives a digital input from the baseband processor and converts the input to an analog signal. This signal is then filtered and converted upwardly by an IF stage at an intermediate frequency. The gain of the transmission signal is adjusted and the IF signal is converted upwardly to RF in preparation for radio transmission. In both the transmission and reception sections, the gain and mixing of the signal are typically performed in the analog domain. This requires the use of a plurality of local oscillators (LO) for down-conversion of the signal, up-conversion and mixing. Local analog oscillators tend to be bulky and require the use of one or more phase locked circuits. As is well known in the art, phase locked circuits are expensive, large circuits that consume a considerable amount of energy. Therefore, the use of PLL increases the cost, size and energy consumption of the local analog oscillators and the transceivers in which these circuits are used. Therefore, there is a need in the art for an effective transceiver at cost and with efficient use of space with features of low noise and minimal energy consumption.

SUMMARY OF THE INVENTION The need for the technique is addressed by the transceiver of the present invention. The inventive transceiver includes a digital circuit for converting baseband signals to intermediate frequency signals. A signal source provides a first periodic signal of a first frequency. A direct digital synthesizer provides a second periodic signal of a second frequency of the first periodic reference signal. An upconversion circuit digitally upconverts baseband signals to intermediate frequency digital signals using the second periodic signal. A digital-to-analog converter converts the intermediate frequency digital signals to intermediate frequency analog signals using the first periodic signal. In the implementation of the transceiver, the digital circuit up-converts a first transmission signal from a first frequency to a second frequency in response to the second periodic signal and provides a digital transmission signal in response thereto. A second circuit is provided to convert the digital transmission signal to an analogue transmission signal. The transmission and reception circuitry are provided to transmit the analog transmission signal and receive an analog reception signal, respectively. In a specific modality, the analog reception signal is it digitally descends to provide a digital reception signal in response to a second periodic signal. A significant feature of the invention is in the provision of the first and second periodic signals with an individual local oscillator. A direct digital synthesizer is included to generate one of the reference signals from the output of the local oscillator. The transmission circuit includes a digital-to-analog delta-sigma converter having the first periodic signal as an input. The digital-to-analog delta-sigma converter has a low-bit-to-analog digital-to-analog converter and a delta-sigma modulator. In the illustrative mode, the low-bit-to-analog digital-to-analog converter is a one-bit digital-to-analog converter and the delta-sigma modulator is a sixth-order delta-sigma modulator. The delta-sigma modulator includes amplifiers with approximately the following gains: 3/2, -3/4, 1/8. The transmission circuit includes an automatic, digital gain control circuit for adjusting the gain of the first signal. An output of the automatic gain control circuit is input to the digital-to-analog delta-sigma converter. Also included in the transmission circuit is a low pass filter, a digital digital mixer and a digital adder. An output of the digital adder provides an input to the automatic gain control circuit. The new design of the present invention is facilitated by the elimination of a local oscillator via the use of the direct digital synthesizer and the digital-to-analog delta-sigma converter. By eliminating a local oscillator, energy and space savings are achieved.

BRIEF DESCRIPTION OF THE DRAWINGS The features, objects and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which similar reference characters are identified correspondingly to all along and where: Figure 1 is a block diagram of a prior art transceiver. Figure 2 is a block diagram of a transceiver constructed in accordance with the teachings herein and employing a digital-to-analog delta-sigma (? S) converter (DAC) and a direct digital synthesizer (DDS). Figure 3 is a block diagram of the DAC? S of Figure 2.

DETAILED DESCRIPTION OF THE PREFERRED MODALITIES While the present invention is described herein with reference to the illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those skilled in the art and those having access to the teachings provided herein will recognize the modifications, applications and additional embodiments within the scope of the present and the additional fields in which it will be of significant utility to the present invention. The following revision of a traditional transceiver is provided to facilitate the understanding of the present invention. Figure 1 is a block diagram of a transceiver 20 of the prior art. The transceiver 20 is a dual conversion telecommunications transceiver and includes an antenna 21 for receiving and transmitting RF signals. A duplexer 22 connected to the antenna 21 facilitates the separation of the RF signals 24 from receiving the transmission RF signals 26. The reception RF signals 24 enter a reception circuit including a reception RF amplifier 28, an RF to IF mixer 30, a reception bandpass filter 32, an automatic gain control circuit 34 (AGC) of reception, analog, and a circuit 36 of IF processing to baseband, analog. The reception RF signals 24 are amplified by the reception amplifier 28, mixed at intermediate frequencies via the mixer 30 from RF to IF, filtered by the reception bandpass filter 32, adjusted in gain by the AGC 34 of reception, and then converted to baseband digital signals 48 via the analogue baseband IF processing circuit 36. The baseband digital signals 48 are then input to a baseband digital processor 46. The RF transmission signals 26 arrive at the duplexer 22 from a transmission circuit including a transmit RF amplifier 38, an IF to RF mixer 40, a transmit bandpass filter 42, and a band processing circuit 44 base to IF, analog. The output signals 50 of the baseband digital processor are received by the analogue circuit 44 from baseband processing to IF where they are converted to analog signals, mixed to IF signals which are then filtered by the transmission filter 42. The bandpass is mixed with RF by the mixer 40 from IF to RF, amplified by the transmit amplifier 38 and then transmitted via the duplexer 22 and the antenna 21. The receiving and transmission circuits are connected to the digital processor 46 of the transmitter. baseband which processes digital signals 48 received from the baseband and transmits the output signals 50 of the baseband processor. The baseband processor 46 may include functions such as signal-to-speech conversions and / or vice versa. The output signals 50 of the baseband processor are 90 ° out of phase with respect to each other and correspond to the signals in phase (I) and quadrature (Q). The output signals 50 are input to the digital-to-analog converter 52 (DAC) in the analog baseband to IF processing circuit 44 where they are converted to analog signals which are then filtered by the low pass filters 54 in the preparation for the mixed. The phases of the signals are adjusted, are mixed and added via a deviator 56 of 90 °, mixers 58 of baseband to IF, and the adder 60, respectively. The add-on 60 transmits IF signals 62 which are input to an analog automatic gain control (AGC) circuit 64 where the gain of the mixed IF signals 62 is adjusted in preparation for filtering via the bandpass filter 42. transmission, they are mixed up RF and the IF mixer 40 to transmission, they are amplified via the transmission amplifier 38, and the possible radio transmission via the duplexer 22 and the antenna 21. The DACs 52 in the baseband processing circuit 44 to IF are synchronized by a first local oscillator (LOl) 66. The sampling rate of the DACs 52 is determined by the frequency of the local oscillator 66. The local oscillator 66 also provides the clock signal to the analog processing circuit 36 of IF a baseband, which is used by analog-to-digital (ADC) converters 68 in analog circuit 36 from IF to baseband processing. A second local oscillator is required (L02) 70 by the mixers 58 in the analogue to baseband processing circuit 44. The second local oscillator 70 transmits a clock signal having a different frequency than the output of the first local oscillator 66. Typically, the second local oscillator 70 operates at a much higher frequency than the first local oscillator 66. A third local oscillator is required 72 for the operation of the mixer 30 from RF to IF of reception and the mixer 40 from IF to RF of transmission. Typically, the same local oscillator 72 is used for both mixers 30, 40. A fourth local oscillator 73 is used by an analog mixing circuit 75 in the IF baseband analog circuit 36 to facilitate the band IF processing functions. base made by analog mixing circuit 75. All local oscillators 66, 70, 72, 73 require one or more phase locked (PLL) circuits. PLLs are typically large analog circuits that consume excess energy. The design limitations of the transceiver 20 limit the amount of signal processing that can be performed in the digital domain, and require in the use of additional circuits, large analog, power consumers such as local oscillators and analog AGC. For example, multi-bit DACs 52 are implemented prior to the mixing of analog signal infiltrations performed by the baseband to IF processing circuit 48. This is partially adhered to that the DACs 52 will generate an extraordinary amount of unwanted noise if implemented after mixing. This is because the IF signals 62 are higher frequency signals that increase the converter faults, thereby increasing the unwanted noise. Unwanted noise is typically in band and it is difficult to filter via conventional means. Since the conversion from digital to analog must be tamed before the baseband to IF conversion by the circuit 44, the baseband to IF processing circuit 44 must be implemented in the analog domain. The analog mixers 58, the filters 54 the add 60 and the analog AGC 64 are much larger and consume more power than their digital counterparts. Additionally, the imbalances due to the low precision of the analog circuits cause the connection of the oscillator signal 70, which can not be filtered by practical means. In addition, the design of the transceiver 20 requires the use of three local oscillators on the hands, i.e., the first local oscillator 66, the second local oscillator 70 and the third local oscillator 72. Oscillators 66, 70 and 72 include analog, large PLLs , inefficient in energy. Figure 2 is a block diagram of a transceiver 80 constructed in accordance with the teachings of the present invention. The transceiver 80 employs a digital-to-analog converter (? S) (DAC) 82 and a direct digital synthesizer (DDS) 84.

In the transceiver 80, the analog baseband to IF processing circuit 44 of FIG. 1 and the analog circuit 36 of the baseband IF processing are replaced with a re-designed baseband processing circuit to IF and the circuit 88 redesigned from IF to baseband processing, respectively. The replacements eliminate the need for the second local oscillator 70 of Figure 1, greatly reducing the power consumption and the size of the transceiver. The DAC 82? S can convert digital IF signals to analog signals without the problems of unwanted noise from a multi-bit DAC. When using the DAC 82 S? the baseband signal processing can be performed to IF in the digital domain, thereby eliminating the step or connection of the oscillator. The digital baseband to IF processing circuit 86 includes a first low pass digital filter 90 and a second low pass digital filter 92 that filters undesirable signals such as noise from quadrature (Q) 94 and phased signals ( I) 96 received respectively from the baseband processor 46. The filtered phase signals are introduced to a first digital mixer 98, while the quadrature filtered signals are input to a second digital mixer 100. The first mixer 98 is synchronized by a DDS clock signal 102 of the DDS 84. The DDS clock signal is shifted in phase by 90 ° by a phase digital diverter 106, which provides a displaced clock signal 104 in response to this. By synchronizing the mixers 98, 100 with clock signals that are 90 ° out of phase, the I and Q signals are phased. The mixers 98, 100 convert the I and Q signals to IF signals that are combined via a digital adder 108. The added IF signals are then transferred to a digital AGC 110, the construction of which is well known in the art. The digital AGC 110 adjusts the gain of the IF signals and transmits these signals to the DAC 82? S. The DAC 82? S converts these signals into analog signals in preparation for further filtering by the bandpass filter 42, up-mixing to radio frequencies by the mixer 40, amplification by the amplifier 38 and transmission via the duplexer 22 and the antenna 21. The DAC 82 ? S uses an oscillator signal 112 generated by an individual local oscillator 114 to drive a one-bit DAC included in the DAC 82? S (as discussed more fully below). The oscillator signal 112 is also used as a frequency control signal to drive the DDS 84 which synthesizes the DDS clock signal 102. The DDS clock signal 102 has a deferent frequency as the oscillator signal 112. The DDS 84 produces a sinusoidal, digitized signal corresponding to the clock signal 102 of the oscillator signal 112 when accumulating the phase increments of the sinusoidal signal 102, digitized at the highest velocity of the oscillator signal 112. The accumulated phase is converted to the sinusoidal signal 102, digitized via a search table (not shown). The digitized sinusoidal signal 102 is used as a frequency reference by the mixers 98, 100 to translate the baseband signals 94, 96 to IF. The construction of DDS 84 is known in the art and is described in U.S. Patent No. 4,965,533 entitled DIRECT DIGITAL SYNTHESIZER DRIVEN PHASE LOCK LOOP FREQUENCY SYNTHESIZER, assigned to the assignee of the present invention and incorporated herein by reference. Those skilled in the art will appreciate that the DDS 84 can be implemented as a programmable DDS whose output clock signal 102 can be adjusted in response to transmission or reception errors due to an oscillator frequency disorder and / or other related errors. . These error measurements can be detected by a logic circuit in the baseband processor 46 or via additional error detection circuits (not shown). The use of DDC 84 to generate the DDS clock signal 102 eliminates the need for an additional local oscillator with an additional PLL. The DDS 84 is much smaller than a local oscillator and the PLL can be easily implemented in a very large, compact scale integration circuit (VLSI), along with the digital mixers 98, 100, filters 90, 92, add-on 108 , AGC 110 and DAC 82? S. In addition, the DDS 84 consumes relatively small amounts of energy. Also, the use of the low noise DAC 82? S eliminates the need for a multi-bit DAC, additional as required in the transceiver 20 of FIG. 1. With reference to FIGS. 1 and 2, the PLL oscillator 70 The required separate in the conventional transceiver 20 for baseband to IF conversion is replaced, in the transceiver 80 of the present invention by the digital DDS 84. The performance of the baseband to IF processing circuit 44 of Figure 1 is improved , in the present invention. In the present invention, analog processing functions are implemented in digital circuits and DACs 72 of several unwanted bits are replaced with the sigma-delta DAC 82 of a bit io. In the present specific modality, the oscillator signal 112 is also used to synchronize an IF-to-baseband digital processing circuit 88 in the reception circuit. In the present specific embodiment, the digital baseband IF processing circuit 88 includes a high speed analog-to-digital converter (ADC) 116? S, a digital mixing circuit 117, and a frequency multiplier to convert the frequency of the oscillator signal 112 to a second frequency for use by the ADC 116? S. The construction of ADCs, digital mixing circuits and frequency multipliers is well known in the art. In the present embodiment, the frequency multiplier 117 divides the frequency (F) of the oscillator signal 112 by four and provides the oscillator signal, divided, resulting as a clock to a one-bit ADC (not shown) included in the ADC 116? S. The oscillator signal 112 provides a reference frequency to the digital mixing circuit 117 for use by the digital mixing circuit 117 to down-convert the digital IF signals transferred from the ADC 116? S to the baseband signals 48. Those skilled in the art will appreciate that the digital downlink conversion functions performed in the digital baseband IF processing circuit 88 can be implemented in a manner similar to the upconversion functions performed in the digital band processing circuit 86. base to IF. Also, analog AGC 34 can be implemented as a digital AGC after ADC 116? S in digital circuit 88 from I F to baseband. The construction of the reception circuit may be implemented in accordance with the teachings of U.S. Patent Application Serial No. 08 / 987,306, filed December 9, 1997, entitled RECEIVER WITH DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER , assigned to the assignee of the present invention and incorporated by reference herein. Those skilled in the art will appreciate that the digital baseband IF processing circuit 86 can be replaced with a different version, such as the baseband IF processing analog circuit 36 of Figure 1 without departing from the scope of the invention. the present invention. Also, the DDS 84 of the baseband to IF digital processing circuit 86 may be implemented in the baseband IF processing circuit 88 in addition to or instead of being implemented in the digital baseband processing circuit 86 to IF. . That is, the DDS output 102 can be used by downconversion and / or ADC circuitry in the baseband IF processing circuit 88. In addition, the AGC circuit 110 may be implemented in the analog domain after DAC 82? S without departing from the scope of the present invention. Figure 3 is a block diagram of the DAC 82 of S S of Figure 2. The DAC 82 S S includes 1 DAC 120 of a bit at the output of a modulator 122 S S. The modulator 122? S is a modulator? S of the sixth order. The 82? S modulator has three basic construction blocks 124, also called second order resonators, cascaded together. Each basic building block 124 includes a combination of digital delays (z "x) 128, amplifiers 130 having voltage gains ai (where i is an integer ranging from 0 to 5), an adder 132 and a subtracter 134. The adder 132 receives as parallel inputs the outputs of the amplifiers 130. One of the amplifiers 130 has an input provided by a digital delay 128 whose input is also the input of the other amplifier 130. This input is provided by a digital delay 128 in a subsequent resonator 124, or in the case of the basic output block 124, provided by the output 127 in the form of noise of the modulator 82 [sigma] S. The first basic construction block 124 receives the output of the digital AGC 110 in Figure 2 as a third input to the adder 132. Subsequent building blocks 124 receive the outputs of the basic blocks 124, construction previews as third entries to the add-ons 132. Those skilled in the art will appreciate that methods for constructing the basic building blocks 124 are well known in the art and can be implemented using programmable gate arrays. The output of the adder 132 provides an input to the subtractor 134. The output of the adder 132 is sent through a digital delay 128 which provides the output of the resonator 124. The output of the resonator 124 is sent through another digital delay 128 and provides a second input to the adder 132 forming a feedback loop. The quantization noise is modeled as a linear noise element 126 and is presented before the output 127 in the form of noise. The voltage gains of the amplifiers 130 are collected to provide a noise transfer function and the signal transfer function that allow the 82? S modulator to meet the requirements for stability noise formation for a particular application. Methods for collecting the gains a for the amplifiers 130 are well known in the art. In the present specific embodiment, the gains are: a0 = 0, ax = 3/2, a2 = 0, a3 = -3/4, a4 = 0, a5 = 1/8. The one-bit DAC 120 is synchronized by the oscillator signal 112 of Figure 2. Those skilled in the art will appreciate that the one-bit DAC 120 can be replaced by a low bit-count DAC such as a 2-DAC. 3 bits without departing from the scope of the present invention. Constructions of sigma-delta DACs and ADCs are well known in the art. In this way, the present invention has been described with reference to a particular embodiment for a particular application. Those skilled in the art and having access to the present teachings will recognize modifications, applications and additional modalities within the scope thereof. Therefore, it is proposed that the appended claims cover any and all of these applications, modifications and embodiments within the scope of the present invention.

Claims (62)

1. NOVELTY OF THE INVENTION Having described the present invention, it is considered as a novelty and, therefore, the content of the following CLAIMS is claimed as property: 1. A digital circuit for converting baseband signals to intermediate frequency signals, which comprises: a signal source for providing a first periodic signal of a first frequency; frequency synthesis means for providing a second periodic signal of a second frequency of the first periodic signal; ascending conversion means for digitally upconverting the baseband signals to intermediate frequency digital signals using the second periodic signal; and digital-to-analog converter means for converting the intermediate frequency digital signals to intermediate frequency analog signals using the first periodic signal.
2. 2. The invention according to claim 1, wherein the signal source includes a voltage controlled oscillator.
3. 3. The invention according to claim 1, wherein the frequency synthesis means is a digital circuit.
4. 4. The invention according to claim 3, wherein the frequency synthesis means includes a direct, digital synthesizer.
5. The invention according to claim 1, wherein the upconverting means includes a digital filter for removing undesirable signals from the baseband signals and / or the intermediate frequency signals.
6. 6. The invention according to claim 1, wherein the upconversion means includes the first and second digital mixers.
7. The invention according to claim 1, wherein the upconversion means includes an automatic, digital gain control circuit.
8. The invention according to claim 1, wherein the digital-to-analog converter means includes a digital-to-analog delta-sigma converter.
9. The invention according to claim 8, wherein the digital-to-analog delta-sigma converter includes a delta-sigma modulator having an order greater than two.
10. 10. The invention according to claim 9, wherein the delta-sigma modulator is a delta-sigma modulator of the sixth order.
11. The invention according to claim 8, wherein the digital-to-analog delta-sigma converter includes a low-bit-to-analog digital-to-analog converter.
12. The invention according to claim 11, wherein the digital-to-analog converter is a digital to analog bit-to-analog converter.
13. 13. A digital circuit for converting intermediate frequency signals to baseband signals, comprising: a signal source for providing a first periodic signal of a first frequency; frequency synthesis means for providing a second periodic signal of a second frequency of the first periodic signal; downconverter means for digitally descending intermediate frequency analog signals to baseband digital signals using the second periodic signal; and digital-to-analog converter means for converting the intermediate frequency analog signals to intermediate frequency digital signals using the first periodic signal.
14. The invention according to claim 13, wherein the signal source includes a voltage controlled oscillator.
15. 15. The invention according to claim 13, wherein the frequency synthesis means includes a frequency multiplier.
16. 16. The invention according to claim 13, wherein the frequency synthesis means is a digital circuit.
17. 17. The invention according to claim 16, wherein the frequency synthesis means includes a direct digital synthesizer.
18. 18. The invention according to claim 13, wherein the downconversion means includes digital mixers.
19. 19. The invention according to claim 13, wherein the analog-to-digital converter includes a delta-sigma converter from analog to digital.
20. 20. A transceiver comprising: a reception circuit; a transmission circuit; a baseband processor connected to the reception circuit and the transmission circuit; a digital circuit in the transmission circuit for converting baseband signals from the baseband processor to intermediate frequency digital signals; and a delta-sigma converter from digital to analog in the transmission circuit to convert the intermediate frequency digital signals to analog intermediate frequency signals.
21. The invention according to claim 20, further including a signal source for providing a first periodic signal of a first frequency for input to the digital-to-analog delta-sigma converter.
22. 22. The invention according to claim 21, further including a direct digital synthesizer for converting the first periodic signal to a second periodic signal of a second frequency, the second periodic signal is input to the digital circuit.
23. 23. A transceiver comprising: a first means for digitally converting a first signal from a first frequency to a second frequency in response to a first reference signal and providing a first digital signal in response to this: a second means for converting the first digital signal to the second frequency to a first analog signal; a third means for transmitting the first analog signal; a fourth means for receiving a second analog signal; and a fifth means for digitally descending the second analog signal to a second digital signal in response to a second reference signal; and a circuit secured in phase to provide the first and second reference signals.
24. The invention according to claim 23, further including a direct digital synthesizer having the output of the local oscillator as an input and providing the first reference signal as an output thereof.
25. 25. The invention according to claim 23, further including a direct digital synthesizer having the output of the local oscillator as an input and providing the second reference signal as an output thereof.
26. 26. A transceiver comprising: a first means for generating a first periodic signal of a first frequency; a second means for digitally generating a second signal of a second frequency of a first periodic signal; a third means for using the first periodic signal to perform the conversion from digital to analog or the analog-to-digital conversion of the signals in a transmission circuit or a transceiver reception circuit, the third means including a delta-sigma modulator; and a fourth means for using the signal of an additional circuit in the transceiver and / or receiver, the additional circuit that requires a clock signal or reference frequency control signal, the clock signal or the frequency control signal of reference, is provided by the second signal.
27. 27. The invention according to claim 26, wherein the first means includes an oscillator.
28. 28. The invention according to claim 26, wherein the second means includes a direct digital synthesizer.
29. 29. The invention according to claim 26, wherein the third means includes a digital-to-analog delta-sigma converter of low bit rate ios.
30. The invention according to claim 29, wherein the low bit count digital-to-analog delta-sigma converter is a one-bit digital-to-analog converter.
31. 31. The invention according to claim 26, wherein the delta-sigma modulator is a delta-sigma modulator of the sixth order.
32. 32. A transceiver comprising: means for generating a first periodic signal of a first frequency; means for receiving an analog signal, the receiving means including means for using the first periodic signal to convert the received analog signal to a digital signal; means for digitally processing the received signal and for providing a first transmission signal; means for transmitting the first transmission signal, the means for transmitting includes means for using the first periodic signal for converting the first digital-to-analog transmission signal; and means for actuating the digital circuitry in the medium for transmitting and / or the means for receiving with the first periodic signal.
33. The invention according to claim 32, wherein the means for actuating includes a direct digital synthesizer for converting the first periodic signal from a first frequency to a second periodic signal from a second frequency, the second periodic signal is provided as the input to a digital circuit included in the digital circuitry.
34. 34. The invention according to claim 33, wherein the digital circuit is a digital mixer.
35. 35. The invention according to claim 32, wherein the digital circuitry includes a direct digital synthesizer to generate a second periodic signal of the first periodic signal for use by the signal mixing circuitry in the transmission medium.
36. 36. The invention according to claim 1, wherein the direct digital synthesizer is a programmable direct digital synthesizer.
37. 37. The invention according to claim 32, wherein the means for transmitting includes a digital-to-analog delta-sigma converter, the digital-to-analog converter having the first periodic signal as an input.
38. 38. The invention according to claim 37, wherein the digital-to-analog delta-sigma converter includes a low-bit-to-analog digital-to-analog converter and a delta-sigma modulator.
39. 39. The invention according to claim 38, wherein the low bit-count digital-to-analog converter is a one-bit digital-to-analog converter.
40. 40. The invention according to claim 38, wherein the delta-sigma modulator is a sixth order delta-sigma modulator.
41. 41. The invention according to claim 40, wherein the delta-sigma modulator includes amplifiers with approximately the following gains: 3/2, -3/4, 1/8.
42. 42. The invention according to claim 32, wherein the means for transmitting includes a digital automatic gain control circuit for adjusting the gain of the first transmission signal.
43. 43. The invention according to claim 42, wherein an output of the automatic gain control circuit is the input to the analog-to-digital delta-sigma converter.
44. 44. The invention according to claim 43, wherein the means for transmitting includes a low pass digital filter, a digital mixer and a digital adder to provide an input to the automatic gain control circuit.
45. 45. The invention according to claim 32, wherein the means for receiving includes an analog-to-digital delta-sigma converter.
46. 46. The invention according to claim 45, wherein the means for receiving includes a frequency multiplier which receives the first periodic signal as an input and which provides a frequency-adjusted signal in response thereto.
47. 47. The invention according to claim 46, wherein the frequency-adjusted signal has a frequency that is about 1/4 of the frequency of the first periodic signal.
48. 48. The invention according to claim 46, wherein the analog-to-digital delta-sigma converter receives the frequency-adjusted signal as an input.
49. 49. The invention according to claim 32, wherein the means for generating includes a voltage controlled oscillator.
50. 50. The invention according to claim 32, wherein the means for processing includes a baseband processor.
51. 51. A transceiver, high efficient space efficient and energy efficient, comprising: an antenna means to receive and transmit radio frequency signals; a first means of translation for transferring radio frequency signals to intermediate frequency signals and vice versa; a second translation means for transferring the intermediate frequency signals to baseband signals and vice versa, the second translation means having an individual local oscillator; a filtering means for removing undesirable signals from the baseband signals and the intermediate frequency signals; a gain control means in communication with the filtering means for adjusting the gain of the baseband signals and the intermediate frequency signals' to facilitate signal processing; and a means for processing the baseband signals according to the predetermined instructions of the transceiver.
52. 52. The invention according to claim 51, wherein the second translation means translates with a digital mixing circuit.
53. 53. The invention according to claim 52, wherein the second translation means includes a direct digital synthesizer to generate a clock signal of a different frequency than that transferred by the first local oscillator.
54. 54. The invention according to claim 51, wherein the gain control means includes an automatic, digital gain control circuit in communication with the mixing circuit.
55. 55. The invention according to claim 51, wherein the means for processing is a cell phone baseband processor.
56. 56. The invention according to claim 51, wherein the filtering means includes a transmission bandpass filter, a bandpass filter for receiving a low pass filter.
57. 57. The invention according to claim 51, wherein the first translation means includes a first local oscillator.
58. 58. A transceiver with efficient high-performance physical equipment, comprising: an antenna means for receiving reception signals and transmitting transmission signals; an oscillating means for generating a first periodic signal; a signal processor for processing the transmitted signals and the received signals; a receiving circuit having a first analog-to-digital converter having the first periodic signal as an input for converting the reception signals to baseband signals, the baseband signals that are input to the signal processor; a transmission circuit having a mixing circuit for mixing the baseband signals transmitted from the processor is signaled to the intermediate frequency band signals; a direct digital synthesizer for synthesizing a second periodic signal of the first periodic signal to synchronize the mixing circuit; a first digital-to-analog converter in the transmission circuit having the first periodic signal with good input to convert the signals of the intermediate frequency band to analog signals; and a translation circuit for transferring the intermediate frequency band signals to a suitable frequency band for broadcasting and generating transmission signals in response to this.
59. 59. A digital circuit for transferring signals between an intermediate frequency band and a base band comprising: a local oscillator to provide a first periodic signal of a first frequency; a delta-sigma converter for converting analog signals to digital signals and / or vice versa using the first periodic signal; a direct digital synthesizer to provide a second periodic signal based on the first periodic signal, the second periodic signal having a second frequency; and a mixing means for transferring the digital signals and / or analog signals between the intermediate frequency band and the baseband using the second periodic signal.
60. 60. A method for transmitting and receiving signals including the steps of: digitally converting a first signal from a first frequency to a second frequency in response to a first reference signal and providing a first digital signal in response to this; converting the first digital signal at the second frequency to a first analog signal; transmit the first analog signal; receive a second analog signal; converting in a digitally downward manner the second analog signal to a second digital signal in response to a second reference signal; and providing the first and second reference signals via a local oscillator.
61. 61. The invention according to claim 60, further including the step of providing the first reference signal via a direct digital synthesizer having the output of the local oscillator as an input thereof.
62. 62. The invention according to claim 60, further including the step of providing the second reference signal via a direct digital synthesizer having the output of the local oscillator as an input thereof.