MXPA01000676A - Method and device for high speed scale conversion - Google Patents

Abstract

A method and a device for high-speed scale conversion wherein a value N within a range of N1 and N2 is converted into a small value M within a range of M1 and M2. The method 5 includes the step of obtaining an approximate value of M by loading the value (N-N1+2p-1) into a multi-bit shift register and right-shifting p bits. A binary search process is then used to determine the error value between the actual value of M and the approximate value of M. By avoiding actual multiplication processes, the conversion can be carried out using low-cost electronic hardware such as a microprocessor or a PROM to carry out the binary search process, a shift (10) register to obtain the approximate value of M, a multiplexer to receive an analog input data N and an A/D converter to convert the analog input data N into a digital data N.

Description

METHOD AND DEVICE FOR HIGH SPEED SCALE CONVERSION Field of the Invention The present invention relates to a method and a device for carrying out conversion at high speed scale from a numerical value to another numerical value more sticky. BACKGROUND OF THE INVENTION In automation and other numerical control applications, it is usually required to convert an input value to an output value. This scaling process is required to be carried out in a very short time, without the support of fast computing means such as a computer. For example, the escalation scheme of interest is to convert input values in the range of 8000 to 40000 in output values in the range of 0 to 4095. It is preferred that the entire conversion process be accomplished within 0.1 milliseconds. At the same time, it is required that the cost of manufacturing the conversion module be low. The cost restriction requires that the equipment be limited to the use of a single A / D converter, and that there is no numerical equipment support to perform the scale conversion. It is therefore desirable to provide a method and a low cost device for high speed scale conversion where the errors are at sufficiently low levels. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method and a device for performing high-speed scaling without using expensive electronic components. This objective can be achieved by carrying out an approximate division of the digital input data, followed by providing a correction to the approximate result. In particular, the approximate division is carried out by shifting the content in a multiple bit change register to the right, and the correction is performed by a binary search process. The high-speed scaling method, according to the present invention, converts input data having an N value in the range of NI to N2 into output data having a value Mln from Ml to M2, where M, N, Ml, M2, NI and N2 are positive integers, and include the steps of: 1) determining a positive integer p such that | q-2p | ^ | q-2p-1 | and | q-2p | < | q-2p + 1 | , where q = (N2-N1) / (M2-M1); 2) load the value V (N) = (N-N1 + 2P ~ 1) in a register of changes of multiple bits and shift to the right the contents of the change register (towards the least significant bit) per p bits to obtain a reduced value A (N); 3) obtain an error value E (N) from a binary search process; Y 4) obtain the M value of M = A (N) + M1 + E (N). Where the binary search process includes the steps of: I) obtaining an integer D such that D = R. { (N2-N1) * | (1 / q - l / 2p) | } where R { x} is the rounded value of x (for example, R { 2.57.}. = 3 and R { 2.49.}. = 2); II) establish a list of correction values C (n) for n = 0 and n = D, such that C (n) = R. { (2n-l) * Q} where Q = (N2-N1) / 2D; and III) assign E (N) = m, where C (m) < (N-Nl) ^ C (m + 1) It should be noted that, for simplicity, it is possible to use the value V (N) = (N-N1), instead of V (N) = (N-nl + 2" 1), in step 2. The method described above will be easier to appreciate with the following explanation: When an N value within a range of NI to N2 is required to be converted to an M value within a smaller range of Ml to M2, the usual way would be to calculate M according to the following equation: M = R { (N-Nl) * (1 / q).}. + Ml M-M1 = R { (N-Nl) * (1 / q).}.

The usual way to convert N into M involves the actual multiplication of two numbers, namely (N-Nl) and l / q, which requires support equipment and / or a long calculation time. Alternatively, the value of (M-Ml) can be roughly approximated by (N-N1) / 2P and an error value is added to or subtracted from the approximate value to correct the discrepancies. The approximate value can be obtained by loading the value of (N-Nl) in a register of multiple bit changes and shifting the contents of the change register by p bits to the right. This approximation leads to an error approximately equal to: E (N) = (N-N1) * | (1 / q - 1 / 2P) | In the digital process, E (N) is approximately equal to E (N) = R. { (N2-N1) * | (1 / q - l / 2p) | } It should be noted that when N = N1, there is no error and therefore E (N1) = 0. When N = N2, the error is the largest and is approximately equal to: E (N2) = R. { (N2-N1) * | (1 / q - l / 2p) |} = D In order to estimate the error value E (N) for any value N without real multiplication, a binary search process can be used to obtain an approximate value of E (N). To facilitate the binary search process, the range of input data (N2-N1) is divided into D approximately equal sections. Each of the sections D is denoted by an index number n, from n = 0 to an = D, such that each section n is limited by C (n) and C (n + 1), where C (n) is approximately same a (n / D) (N2-N1). However, in order to minimize errors resulting from rounding decimal numbers, it is preferred that the range be divided into D + l sections and C (n) be calculated according to C (n) = R. { (2n-l) * Q} where Q = (N2-N1) / 2D The goal of a binary search is to locate the section that contains the value (N-N2). In other words, the search is to locate the same section where C (m) < (N-Nl) ^ C (m + 1) and to assign the error value for N such that E (N) = m. Furthermore, in order to reduce the discrepancies between this approximation method and the actual multiplication, it is desirable to load the value of (N-Nl + 2p "1), instead of (N-Nl), in the change log This is due to the fact that, after moving to the right, the value after the decimal point will be lost regardless of its magnitude, for example, if the value N-Nl = 15 is loaded in the change register and moved to the right three bits, the result is 1 although 15/8 = 1875. This is different from the rounded value of 1875, which is 2. Therefore, it is preferable to load the value (N-Nl + 4) in the change register instead of N-Nl. With all the values of C (n) being pre-calculated and stored electronically, the binary search process start at level 1 to compare the Z value (= N-N1) with C (K) where K is the average index number between 0 and D + 1 to determine which half (approximately) of the input data range (N2- N1) contains the Z value. After knowing which half of the range (N2-NI) contains the Z value, the next search will be carried out only in that half of the range. In this way, in level 2, the search range is reduced to approximately half, and the goal is to determine which quarter (approximately) of the range (N2-N1) contains the Z value. Thus, in the next level, the search range is further reduced to approach a quarter of the range. The search continues in a similar way until the section in which the Z value falls is finally identified. The main advantages of the binary search are that it usually requires only a small number of search steps to obtain the error value E (N) for a given N value, and that the search process can be implemented in relatively cheap electronic components such as microprocessors. If D is less than or equal to (2k-l), the binary search will take more k steps to complete. With the scaling method, according to the present invention, the total conversion time is the sum of (1) the time required to subtract NI (or, preferably, Nl-2pX from N, (2) the time required to load the value (N-Nl), or preferably (N-Nl + 2pX, to the change register and move to the right the record, (3) the total number of steps in the binary search, which is equal to or less than k when D is less than or equal to (2k-l), and (4) the time required to add the value of error and Ml to the value shifted to the right. The scale conversion method will be demonstrated in the present using the following example, with N = 8783, NI = 40000, N2 = 8000, M2 = 4095 and Ml = 0. I) q = 32000/4095 = 7.8144078 ol / q = 0.1279687 p = 3 I) (1 / q - 1 / 2P) = 0.0029687 D = R. { 32000 * 0.0029687} = R { 95.00} = 95 II) Q = 32000/190 = 168.42105 C (n) = R. { (2n-l) * 168.42105} , where n = 0 to n = 95. C (0) = 0 C (1) = R. { 1 * 168.42105} = 168 C (2) = R. { 3 * 168.42105} = R { 505.26316} = 505 C (3) = R. { 5 * 168.42105} = R { 842.10526} = 842 C (14) = R. { 27 * 168.42105} = R { 4547.36} = 4547 C (15) = R. { 29 * 168.42105} = R { 4884.21} = 4884 C (16) = R. { 31 * 168.42105} = R { 5221.05} = 5221 C (17) = R. { 33 * 168.42105} = R { 5557.89} = 5558 C (91) = R. { 181 * 168.42105} = R { 30484.21} = 30484 C (92) = R. { 183 * 168.42105} = R { 30821.05} = 30821 C (93) = R. { 185 * 168.42105} = R { 31157.89} = 31158 C (94) = R. { 187 * 168.42105} = R { 31494.74} = 31495 C (95) = R. { 189 * 168.42105} = R { 31831.58} = 31842 2) V (N) = 8783-4000 + 4 = 787 In the change register: 787 = 1 1 0 0 0 1 0 0 1 1 shifted to the right (3) = 0 0 0 1 1 0 0 0 1 1 = 98 A (N) = 98 3) As C (2) = 505 and C (3) = 842, we have C (2) <; 783 ^ C (3). Consequently, E (8783.) = 2 4) M = 98 + 0 + 2 = 100 The value of M obtained from steps (1) to (4) above can be compared to the value obtained from the actual multiplication: M = R { (4095/32000) (8783/8000)} + 0 = R (100.199) = 100 If N = 38781, V (N) = 38781-4000 + 4 = 30785 2) In the change register: 30785 = 111100001000001 shifted to the right (3) = 000111100001000 = 3848 A ( N) = 3848 3) As C (91) = 30484 and C (92) = 30821, we have C (91) < 30781 ^ C (92). Consequently, E (30781) = 91 4) M = 3848 + 0 + 91 = 3939 Actual multiplication: M = R. { (4095/32000) (38781-8000)} + 0 = R. { 3939,006} = 3939 The two previous examples used to demonstrate the method of scaling at high speed yield a perfect equal value with the actual calculation. It should be noted, however, that not all N values within the range of NI and N2 will give an exactly correct value M. The preferred version of the high-speed scaling method, according to the present invention, uses a microprocessor with adequate memory to store all the C (n) values and carry out the binary search process using a BSX search function, with respect to an input value N and the error value E (N). The BSX search function, for example, can be represented by: BSX = BS (U, V, W), and is defined as follows: 1) the search is based on the reference value C (X); Y 2) if Z = C (X), go to U; if Z «C (X), go to V; and if Z > -C (X), go to W. Here, Z = N-N1. Furthermore, another EX function is also used in the search process, which is defined to assign E (N) = X. For example, for X = 54, BSX means that the search is based on the reference value C (X) = 9095 and the search function is BS54 = BS (E54, BS51, BS57). If Z equals 9095, then E (N) = 54. If Z is less than 9095, the search will be carried out to the next level with BS51 = (E51, BS50, BS52) and based on the reference value C (51). If Z is greater than 9095, then the search will be carried out to the next level, with BS57 = BS (E57, BS56, BS58) and based on the reference value C (57). In the case of D = 95, the search starts at level 1 with X = 48. -Level 1 BS48 = BS (E48, BS24, BS72) -Level 2 BS24 = BS (E24, BS12, BS36) BS72 = BS (E72, BS60, BS84) -Level 3 BS12 = BS (E12, BS6, BS18) BS36 = BS (E36, BS30, BS42) BS60 = BS (E60, BS54, BS66) BS84 = BS (E84, BS78, BS90) -Level 4 BS6 = BS (E6, BS3), BS9) BS18 = BS (E18, BS15 , BS21) BS30 = BS (E30, BS27, BS33) BS54 = BS (E54, BS51, BS57) BS66 = BS (E66, BS63, BS69) BS78 = BS (E78, BS75, BS81) BS90 = BS (E90, BS87 , BS93) -Level 5 BS3 = BS (E3, BS2, BS4) BS9 = BS (E9, BS8, BS10) BS15 = BS (E15, BS14, BS16) BS21 = BS (E21, BS20, BS22) BS27 = BS ( E27, BS26, BS28) BS33 = BS (E33, BS32, BS42) BS39 = BS (E39, BS38, BS40) BS45 = BS (E45, BS44, BS46) BS51 = BS (E51, BS50, BS52) BS57 = BS (E57, BS56, BS58) BS63 = BS (E63, BS62, BS64) BS69 = BS (E69, BS68, BS70) BS75 = BS / E75, BS74, BS76) BS81 = BS (E81, BS80, BS82) BS87 = BS (E87, BS86, BS88) BS93 = BS (E93, BS92, BS94) -Level 6 BS2 = BS (E2, BS1, E2) BS4 = BS (E4, E3, BS5) BS8 = BS (E8, BS7, E8) BS10 = BS (E10, E9, BS11) BS14 = BS (E14, BS13 , E14) BS16 = BS (16, E15, BS17) BS20 = BS (E20, BS19, E20) BS22 = BS (E22, E21, BS23) BS26 = BS (E26, BS25, E26) BS28 = BS (E28, E27, BS29) BS32 = BS (E32, BS31, E32) BS34 = BS (E34, E33, BS35) BS38 = BS (E38, BS37, E38) BS40 = BS (E40, E39, BS41) BS44 = BS (E44, BS43, E44) BS46 = BS (E46 E45, BS47) BS50 = BS (E50 BS49, E50) BS52 = BS (E52 E51, BS53) BS56 = BS (E56 BS55, E56) BS58 = BS (E58 E57, BS59) BS62 = BS (E62) BS61, E62) BS64 = BS (E64 E63, BS65) BS68 = BS (E68 BS67, E68) BS70 = BS (E70 E69, BS71) BS74 = BS (E74 BS73, E74) BS76 = BS (E76 E75, BS77) BS80 = BS (E80 BS79, E80) BS82 = BS (E82 E81, BS83) BS86 = BS (E86 BS85, E86) BS88 = BS (E88 E87, BS89) BS92 = BS (E92 BS91, E92) BS94 = BS (E94 E93) , BS95) -Level 7 BSK = BS (EK, EL, EK) where L = K-1 for K = 1, 5, 7, 11, 13, 17, 19, 23, 25, 29, 31, 35, 37 , 41, 43, 47, 49 53,55,59,61,65,67,71,73,77,79,83,85,89,91,95 The following is an example of a binary search with N = 10783 or Z = (N-Nl) = 6783. At level 1, C (48) = R. { 95 * 168.42105} = 16000 and BS48 = BS (E48, BS24, BS72). Because Z < C (48), or the value (N-Nl) falls in the range of 0 to 16000, the search in level 2 will be carried performed in accordance with BS24. At level 2, C (24) = R. { 47 * 168.42105} = 7916 and BS24 = BS (E24, B12, B36). Because Z ^ C (24), or the value (N-Nl) falls in the range from 0 to 7916, the search at level 3 will be carried out according to BS12. At level 3, C (12) = R. { 23 * 168.42105} = 3784 and BS12 = BS (E12, BS6, BS18). Because Z C (12), or the value (N-Nl) falls in the range of 3874 to 7916, the search at level 4 will be carried out in accordance with BS18. At level 4, C (18) = R. { 35 * 168.42105} = 5895 and BS18 = BS (E18, BS15, BS21). Because Z-C (18), the value of (N-Nl) falls in the range of 5895 to 7916, the search at level 5 will be carried out in accordance with BS21. At level 5, C (21) = R. { 41 * 168.42105} = 6095 and BS21 = BS (E21, BS20, BS22). Because Z-C (21), or the value of (N-Nl) falls in the range of 5895 to 6905, the search at level 6 is carried out in accordance with BS20. At level 6, C (20) = R. { 39 * 168.42105} = 6568 and BS20 = BS (ES20, BS19, E20). Because Z C (20), or the value of (N-Nl) falls in the range of 6565 and 6905, the search at level 7 is not necessary because the next step is E20, or assign E (6785) = 20. The scale conversion method, according to the present invention, has the advantage of being capable of being carried out in a low cost device, as shown in Figure 1. Brief Description of the Drawing Figure 1 illustrates the preferred embodiment of electronic equipment that can be used for high-speed scale conversion. Detailed Description of the Preferred Embodiment Form Figure 1 illustrates the preferred embodiment of the electronic equipment (hardware) that can be used to carry out the required scale conversion at high speed. In Figure 1, a multiplexer (MUX, 10) having a data input terminal for receiving input data 108 from a plurality of analog input channels is shown. The input data is then provided to an A / D converter 20 which converts the input analog data 110 into digital data 112. The digital data 112 is transferred to a storage device 30 to be processed further by processing means (PRR, 40). ). The processor means may comprise a PROM (read-only programmable memory) and a change register (SR, 60) to perform the approximate division. A program BSR 50 may be programmed in the processor means 40 to perform the binary search and other control functions. As shown in Figure 1, the processor means sends the command 114 to the multiplexer 10 to receive input data 108 and provide I 10 data when converting A / D 20. In order to receive analog input data in the range from 0 to 40000 from the sixteen analog input channels, the multiplexer 10 can be a 16 to 1 multiplexer. The data storage means 30 can be a RAM (random access memory). The result of the scale conversion of the processing means 40 can be provided to a digital device such as PLC (programmable logic controller). The scale conversion method, according to the present invention, can be implemented by appropriately programming the processing means 40. For example, as Ml, M2, NI and N2 are data in a particular application, the positive integer p, in step 1, can be pre-calculated and then programmed in the processing means 40. Moreover, the values for q, D and C (n), where n = 0 an = D + l, can be calculated with any such calculation means like a calculator. With 1, D, and C (n) being known, the binary search function BSX is then programmed in the program module BSR 50. The equipment (hardware) sketched in figure 1 is the preferred embodiment of the present invention. It should be noted that the method of scaling at high speed, according to the present invention, can be implemented in other hardware embodiments as well. Therefore, although the invention has been described with respect to a preferred embodiment and its embodiment, those skilled in the art will understand that the foregoing and various other changes, omissions and deviations in its form and detail may be realized. without departing from the spirit and scope of this invention.

Claims (7)

1. CLAIMS 1. In a digital control application where a device is being controlled by a first signal having an M value within a first range defined by a lower limit Ml and an upper limit M2, a method to obtain the first signal from of a second signal having an N value within a second range defined by a lower limit NI and an upper limit N2, where the second range is greater than the first range, said method comprising the steps of: 1) determining a positive integer p such that | q-2p | ^ | q-2p-1 | and | q-2p | < | q-2p + 1 | , where q = (N2-N1) / (M2-M1); 2) divide a value V (N) = (N-Nl + 2p_1) between 2p to obtain a reduced value A (N); 3) obtain an error value E (N) from a binary search process; 4) obtain the M value of M = A (N) + M1 + E (N), and 5) use the M value as the first signal. The method of claim 1, wherein the binary search process comprises the steps of: I) obtaining an integer D such that D = R. { (N2-N1) * | (1 / q - l / 2p) | } where R { x} is the rounded value of x; II) establish a list of correction values C (n) for n = 0 to n = D, such that C (n) = R. { (2n-l) * Q} where Q = (N2-N1) / 2D; III) assign E (N) = m, where m is an integer such that C (m) < (N-Nl) C (m + D 3. The method of claim 1, wherein the binary search process comprises the steps of I) obtaining an integer D such that D = R. { (N2-N1) * | (1 / q - l / 2p) | } where R { x} is the rounded value of x; II) divide the second rank into D sections, each section denoted by an index number n with n = 0 an = D, such that each section is limited by C (n) and C (n + 1), where C (n) is approximately equal to (n / D) (N2-N1); III) determine an integer such that C (m) < (N-Nl) - < C (m + 1); IV) obtain the error value E (N) substituting the same in the equation. The method of claim 1, wherein the binary search process comprises the steps of: I) obtaining an integer D such that D = R. { (N2-N1) * | (1 / q - l / 2p) | } where R { x} is the rounded value of x; II) divide the second rank into D + 1 sections, each section denoted by an index number n, with n = 0 to n = D, such that each section is limited by C (n) and C (n + 1), where C (n) = R. { (2n-l) * Q} , where Q = (N2-N1) / 2D; III) determine an integer m such that C (m) < (N-Nl) ^ C (m + 1); IV) obtain the error value E (N) substituting m into the equation. The method of claim 1, wherein the division in step 2 is accomplished by loading the value V (N) = (N-N1-2P "1) into a register of multiple bit changes and shifting the content to the right. of the register of changes per p bits to obtain the reduced value A (N) 6. A method of scaling to obtain a first M value within a first range defined by a lower limit Ml and an upper limit M2 from a second value N within a second range defined by a lower limit NI and an upper limit N2, where a register of multiple bit changes is used to carry out the division of approach, said method comprising the steps of: 1) determining a positive integer p such that | q-2p | - < | q-2p_1 | and | q-2p | < | q-2 + 1 |, where q = (N2-N1) / (M2-M1);
2. 2) obtain an integer D such that D = R { (N2-N1) * | (1 / q - l / 2p_1) |.} Where R (x) is a rounded value of x;
3. 3) store a series of correction values C (n) for n = 0 to n = D, such that C (n) = R. { (2n-l) * Q} where Q = (N2-N1) / 2D;
4. 4) divide a value V (N) = (N-N1 + 2P'1) between 2P to obtain a reduced value A (N);
5. 5) use a binary search process to compare (N-Nl) with the stored values of C (n) in order to obtain an integer such that C (m) < (N-Nl) -C (m + l)
6. 6) assign an error value E (N) to be equal to m obtained in step 5; and
7. 7) obtain the M value from M = A (N) + M1 + E (N). The method of claim 6, wherein the division in step 4 is accomplished by loading the value V (N) = (N-N1 + 2P_1) into a register of multiple bit changes and shifting to the right the content of said register of changes by p bits to obtain the reduced value A (N). 8. A device for converting a first digital signal having an N value into a first range defined by a lower limit NI and an upper limit N2 in a second digital signal having an M value within a second range defined by a limit lower Ml and an upper limit M2, comprising: means for storing the first signal; means to recover the first signal and divide the first signal between a positive integer p to obtain a reduced value A (N), where p is defined by | q-2p | - | q-2p_1 | and | q-2p | < | q-2p + 1 | , and where q = (N2-N1) / (M2-M1); and means for obtaining an error value E (N) between the reduced value A (N) and R { (N-Nl) * (1 / q)} + Ml, where R { } is defined such that, for any number x, R { x} is equal to a rounded value of x. The device of claim 8, wherein said storage means is a RAM (random access memory). The device of claim 8, wherein said means for recovering and dividing comprises a multiple bit change register for dividing the first signal. The device of claim 8, wherein said means for obtaining the error value comprises a PROM (programmable read-only memory). The device of claim 8, wherein said means obtaining the error value comprises a microprocessor. The device of claim 8, wherein said means for obtaining the error value is programmed to obtain a binary search. 14. The device of claim 8, further comprising an A / D converter for receiving analog signals, converting the analog signals to said first digital signal, and providing said first digital signal to said storage means. The device of claim 14, further comprising a multiplexer, wherein said A / D converter receives analog signals via said multiplexer.