MXPA00005480A - Method and apparatus for variable bit rate clock recovery - Google Patents

Abstract

Methods and apparatuses consistent with the present invention recover a clock signal from a variable bit rate data signal by estimating, in the time domain, the bit rate of the data signal, and based on the estimated variable bit rate, determining a center frequency of a narrow-band filter for extracting the clock signal from the data signal. A clock recovery circuit consistent with the present invention extracts a clock signal from a variable bit rate data signal by estimating a minimum time interval between transitions in the data signal, generating a plurality of pulses that correspond respectively to transitions in the data signal, adjusting the duration of each of the pulses based on the estimated minimum time interval and inputting into a narrow-band filter the adjusted pulses, determining a center frequency of the narrow-band filter based on the estimated minimum time interval, and extracting in the narrow-band filter the clock signal from the adjusted pulses.

Description

METHOD AND APPARATUS FOR THE RECOVERY OF BIT VARIABLE SPEED CLOCK The present invention relates in general to the recovery of the elapsed clock time of signals in communication networks, and more particularly, to methods and apparatus for the recovery of elapsed clock time of variable bit rate signals in communication networks .

BACKGROUND OF THE INVENTION High reliability networks, which handle various types of traffic from different sources, monitor and manage the quality of digital transmission in the domain of time. 'Failure to detect and deteriorate in the correct transmission results in unacceptable erroneous link speeds and unexpected network failures. Therefore, networks must extract from a transmitted data stream a clock signal to perform the necessary measurements and correction to avoid degradation of the transmission. REF .: 120326 To carry out time domain measurements, an extracted clock signal such as an eye pattern aperture and temporal instability is needed. The extracted clock signal is also essential for distinguishing the individual data bits in the transmitted data stream before further processing, such as digital multiplexing, protocol conversion, packet switching, and bit error percent measurement (BER).

Clock recovery has traditionally been referred to as a specific speed process, and as a result, point-to-point transmission systems typically use one or two line speeds. Emerging network technologies, for example photonic switching and Wavelength Division Multiplexing (WDM), however, have made complex optical network topologies possible, where the links carry various types of traffic, such as the Protocol of Internet (IP), Asynchronous Transfer Mode (ATM), Fibrocanal, Synchronous Optical Network (SONET), and Gigabit Ethernet, these emerging networks must employ clock recovery circuits that are adaptable to the variable speeds of the transmitted data.

A closed phase cycle is a type of tracking filter regularly used in a clock recovery circuit to extract a clock signal from a data input signal. Figure 1 illustrates the primary components of a clock recovery circuit 100 of the prior art, including a closed phase cycle. The closed phase cycle includes a phase comparator 120, a low pass filter 130, a controlled voltage oscillator 150 (VCO), and a feedback loop 165.

As shown, a transmission detector 110, for example of a single triggered dual edge trip, receives a non-return to zero (NRZ) input signal 155, and generates a single pulse of duration tED for each transition in the input signal 155. The closed phase cycle, whose bandpass frequency fc is centered on the bit rate frequency fb t of the input signal 155, extracts the clock signal from the flow of pulses generated by the transition detector 110. Phase comparator 120 compares the phase of the signal at the output of the closed phase cycle with the pulse flow, and generates a phase difference signal. The low pass filter 130 filters and amplifies the phase difference signal to generate a correction signal to adjust the phase of the VCO 150.

For a variable bit rate input signal NRZ, two velocity-dependent parameters must be set appropriately in the clock recovery circuit 100 to recover an associated clock 160. A speed dependent parameter is the width of the clock. pulses generated XED by the transition detector 110. While the input signal 155 generally does not contain energy at its bit rate frequency _b_t. the series of pulses generated by the transition detector 110 contains energy at the bit rate frequency. £ ___ • The amount of energy at the bit rate frequency Xit is maximum when the width of the generated pulses XED is equal to 1 /(2 The central frequency of the VCO 150 is the second rate-dependent parameter, which must be appropriately set to recover the clock signal 160 from the input signals 155. Initially, an active or passive stabilization signal 170 sets the center frequency of the VCO 150 at a value _fc in the absence of a signal from the phase comparator 120. The feedback loop 165 causes the center frequency of the VCO 150 to change from the initial frequency fc to the bit rate frequency fblt of the input signal 155. The VCO 150 will close the bit rate frequency f_? T when its center frequency is close to the bit rate frequency f__t. When the center frequency of the VCO 150 equals exactly the bit rate frequency __? T, VCO 150 will close the phase in the input signal 155.

In addition to the closed phase cycle, the clock recovery circuits may also include a closed frequency cycle for adjusting the center frequency _TC of the VCO 150 to the bit rate frequency f__t. Figure 2 illustrates the basic components of a clock recovery circuit 200, which includes a transition detector 210, a phase comparator 220, a frequency comparator 260, low pass filter 230, and a VCO 250. The comparator frequency compares the flow of the pulses generated by the transition detector 210 with the output of the VCO 250, and generates a closing signal that reflects the difference between the center frequency of the VCO 250 and the bit rate frequency ___t. An adder 270 combines the closing signal with the output of the phase comparator 220. The feedback cycle 265 causes the center frequency of the VCO 250 to change from its initial value of _fc to the bit rate frequency _b_t. resulting in a closing signal with transition to zero. At this point, the phase comparator 120 continues to control the center frequency and phase of the VCO 250.

The flow of pulses generated by the transition detector 210 also contains energy at multiples of the bit rate frequency i__t, whose relative amplitude increases when tED decreases. As a result, regular patterns in the coded input signals can produce harmonics and sub-harmonics of the bit rate frequency. ____ • Consequently the existing clock recovery circuits track the harmonics and sub-harmonics of the data signal input when the center frequency of the VCO 250 is inappropriately set to a multiple of the bit rate frequency ___t. In this way, a false closing can take place when the clock recovery circuit searches for the bit rate frequency jfb? T when traversing the center frequency of the VCO 250 through the harmonics. In addition, the recurrent patterns in common block code signals also increase the susceptibility to sub-harmonic closure of a clock recovery circuit.

Although several techniques are known for sweeping the center frequency of the VCO 250 to determine the bit rate frequency, it is very slow and / or lacks sufficient precision for variable bit rate applications. An example of applications of Variable bit rate is the Wavelength Division Multiplexing (WDM), where a data input signal can have a wide range of bit rates. In addition, existing techniques can cause a clock recovery circuit to easily close to the harmonics and sub-harmonics of the bit rate frequency ____ • Therefore, it is desired to have methods and apparatus that do not have the above or other disadvantages of the clock recovery circuits of the prior art for the recovery of a clock signal from a variable speed input data signal. of bit.

DESCRIPTION OF THE INVENTION The methods and apparatuses corresponding to the present invention recover a clock signal from a variable bit rate data signal by estimating the minimum time interval between transitions in the data signal, and the determination of a central frequency of a Narrowband filter that extracts the clock signal from the data signal, based on the estimated minimum time interval. For example, a clock recovery circuit consistent with the present invention The clock signal is extracted from the variable bit rate data signal by estimating a minimum time interval between the transitions in the data signal. The clock recovery circuit generates a plurality of pulses corresponding to transitions in the data signal, and adjusts the duration of each of the pulses based on the estimated minimum time interval. The clock recovery circuit introduces the pulses set within a narrow-band filter, determines a center frequency of the narrow-band filter based on the minimum time interval, and extracts the clock signal from the narrow-band filter. tight pulses.

The methods and apparatuses consistent with the invention estimate the bit rate of the data signal independently of a closed primary phase cycle and a closed frequency cycle. Such methods and apparatus directly estimate the minimum time interval between transitions of the data signal, and therefore, eliminate the problems of harmonic and sub-harmonic closure presented by the clock recovery circuits of the prior art. in bit variable speed applications.

The description of the invention and the following description for carrying out the best embodiment of the invention should not restrict the scope of the invention claimed. Both provide examples and explanations that allow others to practice the invention. The accompanying drawings, which form part of the description for carrying out the best embodiment of the invention, show various aspects of the invention, and together with the description, explain the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a clock recovery circuit of the prior art, including a closed phase cycle; Figure 2 is a block diagram of a clock recovery circuit of the prior art, including a closed frequency cycle and a closed phase cycle; Figure 3 is a block diagram of a clock recovery circuit, in accordance with one embodiment of the invention; Figure 4 is a block diagram of a variable bit rate clock memory circuit, including a calibration means, in accordance with an aspect of the invention; Figure 5 is a circuit diagram of a forward speed detector, which performs a discrete interval pulse width autocorrelation, in accordance with one embodiment of the invention; Figures 6a, 6b, 6c, 6d, and 6e illustrate the time diagrams of an input signal as it propagates through a set of delay segments, in accordance with an aspect of the invention; Figure 7 is a circuit diagram of a delay segment, in accordance with an aspect of the invention; Figure 8 is a block diagram of a forward speed detector, which performs a continuous pulse width autocorrelation, in accordance with an embodiment of the invention; Figures 9a, 9b, 9c, and 9d illustrate the time diagrams of an input signal from an interval generator of time, and the output of an edge transition comparator, in accordance with one embodiment of the invention; Figure 10 is a circuit diagram of a minimum interval correlator, in accordance with one embodiment of the invention; Figure 11 illustrates a coupled logical implementation of the emission of a unipolar minimum correlator, in accordance with one embodiment of the invention; Figure 12a, 12b, 12c, and 12d illustrate an analogous implementation of a feedback loop and associated signals in a forward speed detector, in accordance with one embodiment of the invention; Figures 13a, 13b, 13c, 13d, and 13e illustrate a digital implementation of a feedback loop and associated signals in a forward speed detector, in accordance with one embodiment of the invention; Y Figures 14a and 14b are block diagrams of an implementation of a speed selector, in accordance with two aspects of the invention.

THE BEST WAY TO CARRY OUT THE INVENTION Reference will now be made in detail to preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts.

BIT VARIABLE SPEED CLOCK RECOVERY Figure 3 is a block diagram of a variable bit rate clock recovery circuit 300, in accordance with an aspect of the invention. The clock recovery circuit 300 comprises a forward speed sensor 301, a speed selector 300, a transition detector 320 and a narrow band filter 330. The clock recovery circuit 300 includes a programmable clock extraction path and a speed selection route. The clock extraction path includes a transition detector 320 and a narrowband filter 330. The speed selection path includes a forward speed detector 301 and a speed selector 310.

The transition detector 320 and the forward speed detector 301 receive a variable bit rate input data signal 155. From the input signal 155, the transition detector 320 generates a pulse in response to each transition in the signal of input 155. In the same manner, forward speed detector 301 estimates the minimum time interval between transitions in input signal 155, and generates a speed estimate signal RE. The speed selector 310 then converts the speed estimate signal RE to control signals RSi and RS2, which set the TED width of the pulses generated by the transition detector 320 and the center frequency _fc of the narrowband filter 330, respectively . The speed selector 310 can set TED and fc. for example to 1 / (2 -f__t) and J_.it, respectively. When the speed selector 310 sets the appropriate XED and fc, the narrow band filter 330 extracts the clock signal 160 from the pulse flow.

The speed estimate signal RE can be represented as follows: RE = fblt • Kfrd (fb_.t) (1) where f_? t is the bit rate frequency of the input signal 155 and Kfrd is either a constant or a slow variation function of fb_t- The pulse width tED of transition detector 320 can be represented as follows: 1 - ED (RSI), (2: TED) where KED is a monotonic function of the RSi control signal. The center frequency fc of the narrow band filter 330 may be represented as follows: fc - KfC (RS2) (3) where Kfc is a monotonic function of the RS2 control signal. In one embodiment, the speed selector 310 may perform a one-to-one assignment of the speed estimate signal RE to predetermined values of tED and r "c as follows: where Gi is a monotonic function of the speed estimate signal RE and satisfies the relationship: Kfc fbit - Gi (-bit "Kf r (fb t), and (5) RS2 = G2 (RE), (6) where G2 is a monotonic function of the speed estimate signal RE and satisfies the following relationship: K ED 2 fbxt) - G2 (f_? T * Kfrd (fbit)); 7) In one embodiment, KED and Kfc may have an approximately linear dependence on the speed estimate signal RE, while Kfrd may be close to constant. In this modality the solutions to the equations (5) and (7) can be represented as follows: G? (RE) gil + giz RE + e? (RE) (8) G2 (RE; g2? + G22 RE + e2 (RE! where gll r g12, zx, and gzz are parameters, which may depend on the temperature or interval of the speed estimate signal RE. Similarly, the functions ei (RE) and e2 (RE) can be functions of slow variation of the speed estimate signal RE and the temperature. The parameters gn, g? 2, g2 ?, g22, ßi, and e2 can be selected to satisfy, for example, the equations (5) and (7). Alternatively, ex, and e2 can be set to zero.

Figure 4 is a block diagram of a circuit of variable bit rate clock recovery 400, includa calibration means, in accordance with one embodiment of the invention. The clock recovery circuit 400 comprises a forward speed sensor 301, a speed selector 410, a transition detector 320, and a narrow band filter 330, a selector 420, a programmable calibration source 430, and a monitor response 450. The calibration source 430 generates, for example, a signal path "1010" with predetermined bit rates fre? r for example, (1 / m) x 2488 MHz, where m is a programmable integer between 1 and 32 , inclusive. The response monitor 450 generates a first control signal at the output 454, which controls the particular frequency value f "ref of the calibration source 430.

The selector 420, which is controlled by the calibration permission line 421, receives the input signal 155 and the calibration source 430 at the input ports 422 and 424, respectively. The speed selector 410 accepts the speed estimation RE of the front speed sensor 301 and releases a control signal RSi for the control of the transition detector 320 and the control signal RS2 for the control of the narrowband filter 330. calibration enable line 421 activates the calibration mode, in which the time selector 420 connects the calibration source 430 to forward speed detector 301, while outputs 416 and 418 of speed selector 410 close to their normal values. This inhibits incidental changes in the clock extraction path, which includes the transition detector 320 and the narrowband filter 330.

The response monitor 450 receives at the input 452 a speed estimate signal RE from the output 303 of the forward speed sensor 301. In the autocalibration mode, the response monitor 450 compares the speed estimate signal RE with each speed default bit fret - The response monitor 450 generates, at output 456, a second control signal RM, which corresponds to the difference between the speed estimate signal RE and a predetermined bit rate f_ef. The speed selector 410 receives an RM control signal at the parameter update input 412, and based on the control signal RM, it adjusts, for example, its speed selection algorithm or entries in a look-up table to set the RSi and RS2 control signals. for example, the speed selector 410 can use parameters gu, g12, g2 ?, g22 and / or functions ei and e2 to adjust the assignments of Gi and G2 in equations (8) and (9).

FRONT SPEED DISCREET DETECTOR The time interval between the transitions in the input signal 155 can be represented as? T = n.bit where n is an integer greater than or equal to 1 and tb? T is the period of the bit of the input signal 155. In other words tj.it is equal to the multiplicative inverse of the bit rate frequency _fb? T of the input signal 155. The forward speed sensor 301 can estimate the bit rate in the input signal 155 from a plurality of consecutive transitions in the input signal 155, which could represent a set. { n} of values for the run length n. From this set of transitions, the forward speed detector 301 can determine the minimum interval detected between the transitions t_j.nf which can be represented as follows: Xmin = min? T. { n} In addition, tmm can represent an estimate without deviation from Bit bit rate as follows: lim tbit P (n = l) -0 Digital signals such as input signals 155 may have random bit patterns or may have prescribed bit patterns restricted by block cod For a random sequence of bits, the discrete probability density for a run length n is P (n) = 2 ~ n. The run length distribution for the signals, which are encoded usblock cod can be approximately 2_n for small values of n, for example n <; 5. This indicates that simple bit intervals with n = 1 occur very often with this type of digital signals, for example 50% of the time. Based on the high incidence of simple bit intervals in the input signal 155, the front speed detector 301 can estimate fbit quickly and reliably from tmm measurements. In addition, the preamble of a packet represented by the input signal 155 may include a "1010" pattern, allowing near instantaneous detection of the signal of the speed of the input signal 155.

Figure 5 shows a circuit diagram of a front speed detector 301, which carries out the autocorrelation of the discrete interval pulse width, in accordance with one embodiment of the invention. How I know shows, the forward speed detector 301 comprises delay segments of N gates from Si to SN, type D reversing devices of rising edge driver 530? at 530N, locks R-S 550? at 550N, buffers 560 and 570, a counter 540, and a line priority encoder N 590, where N is an integer greater than one.

The delay segments S? ~ SN are connected to one another in series, where each delay segment S? ~ SN successively delays for time ti, the falling edge initiated by the input signal 155, where 1 = i = N Depending on the mode, the particular values of you may differ between the delay segments S? -SN. As shown in Figure 5, the delay segments S1-S3 include restart edge edge delay elements 5101-5103 and OR / NOR gate (or / ni) 5201-5203, respectively. The outputs of each edge drive delay element 510? -51? 3 are connected to a respective first input 524 ^^ - 5243 of OR / NOR (or / ni) 520- ^ 5203 gates. The last SN segment includes however, a delay element 514N and an inverter 580 instead of an OR / NOR gate (o / ni).

The damper 560, which receives the input signal 155, directs the delay segment Si. The delay segment Si includes a delay element 510 ?, whose output 524x is detected by a first gate OR / NOR (or / ni) 520-L, which includes a complementary output 526? and an output 528- ^ The output 528? of the OR / NOR gate (o / ni) 520? directs the next segment of delay S2. Consequently, the falling edge transition of the input signal 155 passes consecutively through each delay segment S? -SN > For example, the delay element 510? delay output 528? of the delay segment If for time tl r and delay elements 510? and 5102 delay the output 5282 of the delay segment S2 by the time tx + t2. Therefore the total delay through the delay segments k can be represented as k S Ti, i = l When the input transition propagates through the delay segments S? -SN, the consecutive outputs 528? -5283 pass through the transition from an elevated state to a low state, while the corresponding complementary outputs 5261-5263 and 584 they can go through the transition from a low state to a high state. Each falling edge transition in the input signal 155 initiates a series of pulses, which are then compared with the arrival of subsequent increasing transitions in the input signal 155. The reversing devices type D 530? -530N carry out the comparison closing the state of the delayed outputs 526? -526N and 584 in the increasing transition in the input signal 155.

The locks R-S 550? ~ 550N receive and store the status of the outputs of the D type reversal devices 536? -536N via the "SET" ("fixed") inputs 552? -552N, respectively. The outputs 556? -556N of the line priority encoder N 590, which generates at output 598 the binary equivalent of the number of active outputs 536] _- 536N.

The clock input 542 of the counter 540 is connected to the input signal 155. The counter 540 generates at the output 544 a pulse, which resets the locks RS 5501-550N after a predetermined number of transitions, for example 32, in the 155 entry sign.

High speed operation is achieved by dividing the net time delays into small intervals t? -tN, and simultaneously restarting each delay element 51? 2-510N via a common control line 574 of the 570 buffer. The 570 damper delays the simultaneous restart signal, Such a way that the time retention requirement of the reversing devices type D 530? -530N is satisfied.

The operation of the front speed detector 301 may be initiated at the rising edge transitions in the input signal 155 as well as in the falling edge transitions in the input signal. The front speed sensor 301 may, for example, include a duplicated circuit, which is directed by an inverted replica of the input signal 155, for the detection of the length of each pulse in the input signal 155 followed by an increasing transition in the input signal 155.

Figures 6a-e illustrate time diagrams of the input signal 155 as it propagates through the delay segments S? ~ SN, in accordance with one embodiment of the invention. Figures 6a-c show a falling edge transition in the input signal 155 as it propagates through the delay segments S? -SN. At the end of a pulse 155, the delayed edge may pass through a portion or all of the delay segments S? ~ SN. Because a pulse with the shortest duration in the input signal 155 should pass through the smallest number of SL-SN delay segments, the 528k output of the kéS? Mo delay segment Sk is in a high state when the sum of the times of delay you satisfy the restriction ntb? t < ti i = l where tb? t is equal to the multiplicative inverse of the bit rate frequency ____t of the input signal 155.

As shown in Figures 6b-e, the outputs 528, 5, and 5282 of the delay segments Si and S2, respectively, are activated in the period ntb? T of the input signal 155, while the outputs 5283 and 584 of the delay segments S3 and SN are not activated in that period of time. The waveforms indicated by the dotted lines in Figures 6d-e show the state of the outputs 5283 and 584, respectively, for a longer duration input pulse. After a small number of transition input signals 155, depending on the run length distribution P (n), a pulse with n = 1 appears in the input signal 155, after which time of the state of the outputs 556? -556N represents an upper and lower limit in tbit- The state of the outputs 556? -556N track "the increasing and decreasing values of tb? t when the pulses of the 540 counter, for example, occasionally reset the locks R-S 550? ~ 550N. The priority encoder 590 derives from the output 598 a binary representation of tb? T of the state of the outputs 556? -556N. This binary representation of t? is the speed estimate signal RE, which is determined uniquely by Xit and the particular values of t? -tN. The resolution of the tbit estimate can be improved by performing multiple sweeps with different combinations of values for ti-t ...

Table 1 lists several common line speeds in input signals 155 and delays in Di segments, which can be used to make the distinction between line speeds. The first two columns list some common line speeds -fbi and the corresponding bit interval tbxt for the input signal 155, respectively. The third column lists the net delays to make the distinction between consecutive velocities, which is the average of tb? T for two consecutive velocities. Since the net delay through the delay segments of k can be represented by i = l The net delays listed in the third column. The segment delays, which are listed in the fourth column and which can be easily obtained, demonstrate the feasibility of operation of the discrete speed detector 301 over a wide range of line speeds.

TABLE 1 Period Speed _b_t Delay Time Delay Line f_t (nseg) Net Segment t (MHz) (nseg) 2488. 32 0.402 1250 0.829 0.349 800 1.250 1.095 0.225 622.08 1.608 1.429 0.334 531 1.833 1.746 0.317 265 3.744 2.829 1.083 194 5.144 4.459 1.630 155.52 6.430 5.787 1.328 132.5 7.547 6.989 1.202 125 8.000 7.774 0.785 51.84 19.29 13.645 5.871 DELAY SEGMENT Figure 7 is a circuit diagram of the delay segment S2 (shown in Figure 5), in accordance with one embodiment of the invention. Although Figure 7 shows a circuit diagram of the delay segment S2, generalization can easily be made to the delay segments Si and S3-SN. High-speed performance can be optimized by joining the threshold function found in a traditional 5102 delay circuit implementation with OR / NOR gate (o / ni) 5202 using a gate differential amplifier. Input 5122 of delay segment S2 directs the base of transistor o2, which serves as a voltage follower. The emitter of Q702 and a source of programmable current I708 are connected to capacitor C70. at output 5142 by means of resistor R7oe- The emitter current of Q702 quickly charges C7o_ to a preset value while the current of I (_8 discharge C704 at a controlled rate.) The voltage at output 5142 is detected by means of a gate difference amplifier, which includes Q720 and Q722.The bases of Q20 and Q722 are connected to the output 5142 and a reference voltage V740, respectively The emitters of the transistors Q720 and Cb22 are connected via a node 730 to a source of fixed current I7o.

The base of a gate transistor Q724 is connected to a common control line 574 via the second input 5222. The collector and the emitter of Q724 are connected to the output 5262 and the node 730 respectively. The amplifier has inverted and non-inverted outputs on outputs 5262 and 5282, respectively. The output 5282, which is connected to the collector of Q722 is obtained from the voltage drop along R72s- The output 5262, which is connected to the collectors Q72o and Q724, is obtained from the voltage drop along of R726- The value of reference V740 can be altered by positive feedback via control node 742, which is connected to output 5262 to provide a threshold level hysteresis. A voltage greater than that set by reference V40 either at output 5142 or common control line 574 forces output 5262 at a low state and output 5282 at an elevated state. In the last segment of delay SN, the gate transistor corresponding to Cb24 can be omitted.

In the inactive initial state, the input 5122 and the common control line 574 may be in a high state, and the output 526 may be in a low state. In this state, the high signal at input 5122 controls Q702 to prefix the voltage across capacitor C704. A high signal on the common control line 574 activates Q72 and forces the output 5282 to direct the next delay segment S3 to an elevated state even before the voltage at C704 reaches the preset value. When the input signal 155 passes through the transition from an elevated state to a state under the common control line 574 it becomes low and deactivates Q72. The initial state is maintained by the preset voltage through C7o, which controls Q72o- Depending on the time constant of the preceding delay segment Si and the duration of the low state, the voltage at input 5122 can pass through the transition to a low state at some time after the input signal 155 passes through the transition from an elevated state to a low state. This deactivates O7o2 and allows C70 to discharge by the I7oe-current. If the duration of the low state is still sufficient, the voltage at output 5142 falls below the reference voltage set by V740 and causes output 5262 to pass. by the transition to a high state and the 5282 exit through the transition to a low state. The low state at output 5282 activates delay element 5103 in the subsequent delay segment S3.

The response time following the detection can be improved by means of positive feedback from output 5262 to slightly vary V740. The time delay ti associated with the delay segment S2 it is governed by the conservation of the load at output 5142. The value of time delay t2 can be determined by the difference between the voltage preset through C704, VPREFUED the value V740? Ms of the reference voltage V740 when the control 742 is in a low state, the differential amplifier bypass the voltage V0sés; LIno in the threshold of change, the value of the capacitor C7o4, the deviated capacitance Cs associated with the output 5142, the current I7os, the base current Ib of Q72o and the charge Q _ (I7o8) stored in the emitter of Q72o- This relation can be represented as follows: (I 08 + Ib) t2 - (VPRE FI ADO_V74O -Vos) (C7o + Cs) -Qe (I 708! 10 ' The resolution of the discrete speed detector depends on the selection of the time delays t? -tN, which can be programmed, for example, through the current value I7os for each corresponding delay segment SI ~ SN- CONTINUOUS ADVANCED SPEED DETECTOR Figure 8 is a block diagram of the forward speed detector 301, which performs a continuous pulse width autocorrelation in accordance with with one embodiment of the invention. As shown, the forward speed detector 301 comprises a minimum interval correlator 840, a feedback circuit 830, and an output 303. The output 303, whose value is the speed estimate signal RE, receives the output 836 of the circuit of feedback 830.

The minimum interval correlator 840 includes an adjustable (or programmable) controlled time interval generator 810 and an edge transition comparator 820.

The time interval generator 810 receives the input signal 155 and the output 836 of the feedback circuit 830, respectively, at the inputs 812 and 816. In response to a transition in the input signal 155, the interval generator 810 generates at the output 814 a corresponding transition delay for the time t, which is controlled by the speed estimation signal RE. Alternatively, in response to a transition in the input signal 155, the time slot generator 810 may generate at output 814 a set of corresponding transitions delays by a set of times t, which may have different values and which are controlled by the speed estimate signal RE.

The value of t is related to the speed estimate signal ER by means of a known relation t = t (RE). The interval generator 810 can, for example, be implemented in such a way that the product of the speed estimate signal RE and t (RE) is closely constant to a first order.

The edge transition comparator 820 receives at input 822 and 824 the input signal 155 and output 814 of the interval generator 810, respectively. The output 826 of the edge transition comparator 820 generates a signal, which is monotonically related to the difference between t and tb? T- The edge transition comparator 820 generates a positive pulse at the output 826 when a subsequent transition in the signal input 155 takes place before the time t has elapsed. The output 826 is received via the input 832 of the feedback circuit 830, which releases the speed estimate signal RE at the output 836 to set t, such that a prescribed speed of pulses is generated at the output 826. The time constants in the feedback circuit 830 can be controlled via the input 834 by the speed of the transitions in the input signal 155. The prescribed pulse rate of the output 826 can have a constant duty cycle. Alternatively, the Prescribed speed may depend on the speed of the transitions in the input signal 155.

In one embodiment, the relationship between the velocity estimation signal E and 1 / t can, for example, be linear. The output 836 of the feedback circuit 830 controls t via a negative feedback to the input 816 of the interval generator 810. The negative feedback establishes the speed estimate signal RE such that t (RE) is equal to tb? T- Thus, the bit rate frequency _b? t of the input signal 155 can be determined based on the speed estimate signal RE, since the bit rate frequency f_? t is closely proportional to the speed estimate signal RE. In addition, to reduce the noise in the speed estimate signal RE, the forward speed sensor 301 may also include, for example, analog or digital means in the feedback circuit 830 or in the speed selector 310 to filter the noise in the speed estimate signal RE.

In accordance with another aspect of the invention, the front speed detector 301 can estimate Xbit using a pulse width autocorrelation method. Figures 9a-d illustrate the time diagrams of the input signal 155, the output 814 of the time interval generator 810, the output 826 of the edge transition comparator 820, in accordance with this embodiment. Figure 9e illustrates the distribution of the values at output 826 for different values of x and an arbitrarily set value of X_.t- Figure 9a shows the input signal 155 with a transition occurring at time x x = 0 and a subsequent transition at x x = tblt. The transition to? X = 0 triggers the time interval generator 810, whose output pulse is delayed by x. Three values of? X are indicated as fast F (from Fast), slow S (from Slow) and aligned A (from Aligned).

Figures 9b and 9c illustrate the state of the output 814 of the time interval generator 810 for two different modes. Figure 9d illustrates the state of the output 826 of the edge transition comparator 820 for the two modes.

In the first embodiment, the time interval generator 810 includes one or more edge actuator reset delay elements, for example, the 510? -510N delay elements shown in Figure 5. As shown in Figure 9bm , in this mode, the interval generator of time 810 generates a pulse at output 814, which starts after the time x has elapsed and is restarted by the next transition in the output signal 155.

In the second aspect, the time slot generator includes a single edge drive shot, which is described in detail below. As shown in Figure 9c, in this embodiment, the time interval generator 810 generates at output 814 a simple pulse starting at time x x = 0, which has duration x.

In both modes, if the time x is set smaller than Xbi as indicated by F, the next transition in the input signal takes place at? X =? Xb ± t after the time x elapses, and the output ' 8-26 is set to a high state.

There is a perfect alignment between the pulse generated at the output 814 of the time interval generator 810 and the input signal 155 when x = Xb ± t, as indicated by A, and a transition in the input signal 155 takes place with the overlaps of x in? xb ± t. The output 826 may be in a high or low state when there is a perfect alignment. Transitions in the input signal 155 that occur long after x can be ignored since they can represent a run of bits with? x = nxbit and n = 2.

Figure 9e illustrates the distribution of values assumed by the output 826 for different values of x and a given bit value. This distribution represents the transfer function of the minimum interval correlator 840, which includes a time slot generator 810 and a edge transition detector 820. Based on the statistical interpretation of relative frequency, the graph in Figure 9e also illustrates the average value at output 826 that could be observed after many instances of transitions of input signal 155. The graph in Figure 9e has a steep slope at x = Xb ± t, which distinguishes between the conditions of F and S. The shape of the transition between F and S can be determined by, for example, the distribution P (n) of run lengths n.

The edge transition comparator 820 compares the interval between the trailing edge of the input signal 155 and the output 814 of the time slot generator 810, and via the feedback circuit 830, adjusts x to the value it = 1 / fb ? t- After setting the time of the feedback circuit 830, the adjusted x represents a bit estimate. Therefore, in this mode, the closing of the harmonic does not take place because the estimated Xbit is relates exclusively to ____.

MINIMUM INTERVAL CORRELATOR Figure 10 shows a circuit diagram of a minimum interval correlator 840 (shown in FIG.

Figure 8), in accordance with one embodiment of the invention.

In this mode, the response to edge transitions • descending and rising edge transitions in the input signal 155 are effected through two separate routes. The minimum interval correlator 840 is divided into a minimum falling edge correlator driven 1090 and a minimum edge correlator of driven rising edge 1092. The minimum interval correlators 1090 and 1092 each perform the functions of the interval generator of 1090 and 1092. time 810 and the transition comparator shown in Figure 8.

The minimum interval correlators 1090 and 1092 include outputs 826? and 8262, which collectively form output 826 of the minimum interval correlator 840. Although the minimum interval correlators 1090 and 1092 include separate outputs 826? and 8262, their respective entries 302? and 3022 are connected with the input signal 155.

The minimum interval correlator 1090 includes a non-reversing buffer 1010, a Cioiß capacitor. a programmable current source Iioiß. a comparator 1030, a voltage reference V? 038, a non-reversing damper 1050, and a positive-driven edge reversing device type D 1070. The minimum interval correlator 1092 includes an inversion damper 1020, a capacitor C? o28 , a programmable current source I? o26, a comparator 1040, a voltage reference V? 04o, a reversing damper 1060, and a positive edge reversing device driven type D 1080.

Entry 302, which includes nodes 302? and 3022, receives the input signal 155. The node 302? it is connected to the non-reversing inputs 1012 and 1Q52 of the buffers 1010 and 1050, respectively, in the minimum interval correlator 109 * 0. The output 1014 of the shock absorber 101Q. It is connected via node 1003 with a Cioiß capacitor. with the priogrammable current source Iioiß, and the input 1032 of the comparator 1030. The reference input 1034 of the comparator 1030 is connected to the voltage reference V? 038. The output 1036 of the comparator 1030 is connected to the input D 1072 of the type D reversing device 1070, whose clock input 1074 is directed by the output 1054 of the shock absorber 1050.

The node 3022 is connected to the reversing inputs 1022 and 1062 of the dampers 1020 and 1060, respectively, in the minimum interval correlator 1092. The output 1024 of the damper 1020 is connected via the node 1004 to the capacitor C? 028 ^ the programmable current source I? o2e, and the input 1042 of the comparator 1040. The reference input 1044 of the comparator 1040 is connected to the voltage reference V? 048- The output 1046 of the comparator 1040 is connected to the input D 1082 of the device of reversal type D 1080, whose clock input 1084 is directed by the output 1064 of the damper 1060. The outputs 1076 and 1086 of the reversing devices type D 1070 and 1080 form the output 826? and 8262, respectively. Programming inputs 1017 and 1027 control via input 816 current sources Iioie and I1026, respectively.

The operations of the minimum interval correlators 1090 and 1092 are similar except that all processing is active in opposite transitions in the input signal 155. The operation of the minimum interval correlator 1090 is as follows: The output port 014 assumes a state of low impedance with a preset output level of VPREFIXED when input 1012 is in a high state, and assumes a high impedance state when input 1012 It is in a low state. For example, VPBEFIJADO can be more positive than the reference voltage V? 038. A high state in the input signal 155 causes the 1010 damper to charge the Cioiß Capacitor to V PREFIXED - When the input signal 155 undergoes a transition from a high to a low state, the current flow of the output 1014 of the damper 1010 is inhibited, and the LOIS s capacitor discharges freely by means of the programmable current of Iioiß- Si the duration of the state low in the input signal 155 is long enough, the voltage in the node 1003 falls below the level set by? o38. and the output 1036 of the comparator 1030 passes through the transition to a low state. The D-type reversal device 1070 captures via the rising edge transition at the output 1054 of the buffer 1050, the state of the output 1036 at time? X = nxbit, when the input signal 155 undergoes a subsequent transition from low to high .

The time required by the Ciois capacitor to discharge from VRUFIX V? 048 is t (I? Oi6.) • Output 826? May be in a low state if? X> x (I? Oi6 .. and may be in a state high if? x <x (I? oi6) «The output 826? can always be smaller when t> bit- If x> bit, there may be small values of the run length n for whose output 826? in a been high The exit 826? It can, however, be in a low state for a large n.

Figure 9e shows the distribution of the output values 826? averaged from typical run length values n. The time constant x (I? O? ß) can be represented as follows: (Il016 + Ib) t - (V RBFI ADO-Viosß-Vos) (C? Oi8 + Cs) -Qo? O? (Iioie) (11) where V0s? is the voltage counteracted at a threshold of comparator 1030, Cs is the bypass capacitance associated with node 1003, Ib is the input deviation current of comparator 1030, and Q0_? o? _ (Iioie) is the load removed by the outlet 1014 when the damper 1010 is turned off.

A similar operation occurs in the minimum interval correlator 1092 for rising edge transitions in the input signal 155. The outputs 826? and 8262 indicate whether x is greater or less than Xbit- In accordance with one modality, outputs 826x and 8262 can be used to control x by means of Iioie and I1026 using negative feedback. The speed estimation signal RE can be determined from the value of the control signal 816 necessary to achieve that x = Xbit.

The minimum interval correlator 1090 of Figure 10 constitutes a mode of a unipolar minimum interval correlator, which is active at the falling edge of the input signal 155. The unipolar minimum interval correlator 1090 may include a programmable gate delay, which includes the 1010 damper, the Cioiß capacitor. the current source 11017. the comparator 1013, and the reversing device type D 1070. The reversing device type D 1070 can include two locks (not shown), which are controlled by the node 302? via clock input 1074. In one embodiment, one of the locks at 1070 can be shared with the programmable gate delay to create a single, non-re-actuable, triggered edge trigger. By performing several closures and comparison operations in parallel, higher operating speeds can be achieved in this mode.

Figure 11 illustrates an coupled logical emitter (ECL) implementation of a unipolar minimum interval correlator 1090, in accordance with one embodiment of the invention. The unipolar minimum interval correlator 1090 comprises an edge transition comparator 1104 and a single non-re-operable, driven edge trigger 1102. The edge transition comparator 1104 includes reversing devices 1110 and 1156, a non-reversing buffer 1114, OR gates (ni) 1130 and 1150, and node 1138. Node 1138 performs a wired operation OR (or).

The single non-actionable downstream trigger 1102 includes a comparator 1160, a time-taking capacitor Cu6, programmable current sources Iioie and I? I79, diodes D? 75 and DU76, reference voltages VREF and CCLAM, an operational amplifier 1170, gates OR (ni) 1120 and 1140, a reversing device 1146, a buffer 1124, and nodes 1128 and 1166. The nodes 1128 and 1166 each perform an OR (or) cabling operation.

The input 1111 of the reversal device 1110 and the node 1144 of the single shot 1102 receive the input signal 155. The falling edge of the input signal 155 activates the single shot 1102 to generate an output pulse of duration x (I? Oi6) at the output 1127 of the buffer 1124. The duration x is controlled directly by the controlled current source Iioiß. Exit 1127 of a shock absorber 1124 is in a high state in the reset state, and transitions to a low state during time x. The single shot 1102 can not be reactivated by a subsequent change in the state of the input signal 155 until after both the time x has elapsed and the input signal 155 returns to its high state.

The input node 1144 is connected to the input 1142 of the gate OR (ni) 1143 and to the input 1121 of the gate OR (ni) 1120. The open-emitting output 1143 of the gate MOR (ni) 1140 is connected via the node 1128 to the input 1122 of the gate ÑOR (ni) 1120 to the input 1147 of the reversing device 1146, and to the output of the open non-inverting transmitter 1126 of the buffer 1124. The output 1148 of the reversing device 1146 is connected to the input 1141 of gate ÑOR (ni) 1140 to create an RS lock.

A high state at node 1144 places node 1128 in a low state when output 1126 is low, while a high state at output 1126 exceeds output 1144 to set node 1128 -in a high state. The output 1126 of the damper 1124 may be in a high state for the time x, and may inhibit the gate OR (ni) 1120 from the response to changes in the input signal 155. The output of the open emitter 1123 of the gate ÑOR ( ni) 1120 is connected via node 1166 to the open output of comparator emitter 1160, capacitor Cn6, and input 1125 of buffer 1124.

The capacitor Cne is connected to the non-inverting input 1161 of the comparator 1160, to the cathode of the diode Dn75, and to the programmable current source Iioiß- The output 1173 of the opamp 1170 directs the anode of the Dips- diode The opap p 1170 can be configured, for example, as a voltage follower with the diode Dn76, in the feedback loop between the output 1173 and the reversal input 1172.

The diode Dn76 can be diverted to the same current density as D1175 by the programmable current source In78- The node 1179 controls the current I ?? 78 and the node 1017 controls the current I1017. Both control nodes 1017 and 1179 are connected to the input 816. The inverting input 1162 of the comparator 1160 is connected to the voltage source VRBF. The non-inverting input 1174 of the opamp 1170 is connected to the voltage source VCLAMP- The inversion output 1127 of the buffer 1124, which is controlled by the node 1166 forms the output of the single trigger 1102, and is connected to the input 1134 of the gate 1130 in the edge transition comparator 1104. In the steady state, the input signal 1155 and the input node 1144 may be in the high state, the nodes 1128 and 1166 may be in the low state, and the voltage in the node 1165 may be maintained in VCLRMP - when the node input 1144 goes through a transition to a low state due to a negative transition in input signal 155, output 1123 of gate ÑOR (ni) 1123 goes through a transition to a high state. Coupling through capacitor Cn6 forces node 1165 to a high state. Positive feedback through comparator 1160 and Cues keeps node 1166 in a high state until the voltage at node 1165 decreases to VREF.

When the node 1166 goes through a transition to the high state after the input signal 155 passes through a transition to a low state, the buffer 1124 directs the node 1128 to a high state, activating a first lock, which includes a device inversion 1146, and a gate ÑOR (ni) 1140. The output 1123 of gate OR (ni) 1120 can be subsequently inhibited when node 1128 goes through a transition to a high state. The first lock continues to keep node 1128 in a high state, and inhibits output 1123, which can only be restarted until node 1166 goes through a transition to a low state at time x. The first lock is restored to a low state by the gate ÑOR (ni) 1140 when the node 1166 returns to a low state and the input signal 1155 passes through a transition to a high state, restoring the single shot 1102 to the steady state.

The voltage on the capacitor C? N2 has sufficient time to reach the steady state since the single shot 1102 is activated only at the descending edge transitions.

The pulse duration x can be related to the capacitor discharge current Ic by conserving the load at node 1185. This relationship can be represented as follows (I? Oi6 + Ib) t = [? n66 (I1016 / O + VCIAMP-V EF-VOS s? mo] C? 6 (12) + (Vc ñMP - VREF - V0 s) ° Cs +? QB s? mc '- Qd (Iioie), where Cs is the deviation capacitance associated with node 1165 and Qd is the load stored in diode Dn75. Vn66 represents the waveform of the rising voltage at 1166 after the decay transition in the input signal 155 activates the single shot 1102.

In accordance with one embodiment of the invention, the parameters associated with the comparator 1160 are as follows: it is the input deviation current, V, th is the input imbalance in the threshold and AQ i is the input load required to switch comparator 1160. This expression shows that Iioie can be near proportional to -f_it when x = Xbit- The non-reversing damper 1114 receives the output 1112 of the reversing device 1110, which corresponds to the firing delay of the single shot 1102. The gate OR (ni) 1130 compares the outputs 1116 and 1127 of the damper 1114 and the single shot 1102 respectively. The open output of the transmitter 1136 of the gate ÑOR (ni) 1130 may be a current pulse, which may, for example, be a function of the time interval between the subsequent rising edge in the input signal 155 and the rising edge of the input signal. the output 1127 of the single shot 1102 after the delay time x.

The node 1138 goes through a transition to a high state when the input signal 155 goes through a transition to a high state while the output 1127 of the single trigger 1102 is in a low state. The gate ÑOR (ni) 1150 and the reversing device 1156 are connected to each other to form a second lock, which is activated by a high state at node 1138. If node 1138 is sufficiently raised, then the feedback loop around the gate 1150 and the reversing device 1156 keep the node 1138 in a high state until the input signal passes through a transition to a low state and the output 1116 of the gate 1114, which is connected to the gate ÑOR (ni) 1150, goes through a transition to a high state, The relation between the current pulse of the output 1136 of the gate 1130 and x-xb ± t can be represented as follows: the load Qo_? I36 in the current pulse of the gate 1130 is proportional to x - Xbi -? tcompuerta, where? ^ gate is a fixed fraction of the response response time. The probability that the node 1138 can be set to a high state depends on Q0_? I36 through a function F gate (Qo_? I3e), whose characteristics are shown in Figure 9e. The average time that node 1138 remains in a high state, once activated, can be approximately n "? Xmin + tmin -? Gate- The signal at node 1138 can be used to control x by means of Iioiß using negative feedback .

ANALOGUE FEEDBACK CIRCUIT Figure 12a illustrates an analog implementation of the feedback circuit 830 in accordance with one embodiment of the invention. In this embodiment the feedback circuit 830 comprises an addition circuit 1210, a low pass filter 1220, a differential amplifier 1230, and a reference voltage V? 250. The low pass filter 1220 includes an output 1224, and a differential amplifier 1230 includes an output 1236. Figures 12b-d illustrate a change in the bit rate of the input signal 155, a change in the output of the low pass filter 1224. and a change in the output of the amplifier 1236.

The feedback circuit 830 receives at nodes 832? and 8322, which collectively forms input 832, outputs 826? and 8262 respectively of the minimum interval correlator 840. The node 832? it is connected to the input 1212 of the addition circuit 1210, and the node 8322 is connected to the input of the addition circuit 1214. The low-pass filter 1220 filters the output 1216 of the addition circuit 1210, which is applied to the input No. 1232 of the differential amplifier 1230. The reference voltage V1250 is connected to the reversing input 1234 of the differential amplifier 1230. The output 1236 of the amplifier 1230 forms the output of the feedback circuit 836.

Entries 1212 and 1214 of addition 1210 receive from nodes 832? and 8322, pulses of the outputs 826x and 8262 of the unipolar minimum interval correlators 1090 and 1092, respectively, when xb ± t < x. The "low pass 1220" filter removes high frequency variations of the combined signal at the output 1216 of the addition 1210. The differential amplifier 1230 amplifies the difference between the filtered signal at the output 1224 of the filter 1220 and the reference voltage V? 2so. The amplified difference between V? 24 and V1250 appears at the input 1236 and can be used to control the period x of the time interval generator 810. The differential amplifier 1230 can incorporate a marginal phase compensation, which may be necessary to maintain the total dynamic stability of the feedback loop.

Figure 12b illustrates an increase in the bit rate jftat of the input signal 155 of _b_t? a f__t_ > f -ti that takes place at time t = 0. The change in bit rate is detected by the minimum interval correlator 840, which generates a change in the speed of the pulses that appear at inputs 1212 and 1214 of the addition 1210 and _ consequently at the output 1216. The level at the output 1224 for t < 0 can be maintained by a constant pulse rate of the minimum interval correlator 840. The horizontal dotted line in Figure 12c illustrates that before the change to t = 0, a negative feedback maintains the output 1224 at about V? 250. A change in the speed of the pulses at t > 0 at output 1216 generates a transient change at output 1224. The amplified signal appearing at output 1236 changes until the period x of time interval generator 810 is set to a new value of l / ___ t2- The minimum interval correlator 840 can generate an output pulse when isolated "ones" and "zeros" occur in the input signal 155. The input 1212, which is connected to the output of the falling edge transition comparator 826? via node 832? can then be active from high to low transitions in the input signal 155. The probability that the output 826? passing from a transition to a high state followed by an isolated "zero" can be represented by F (x - x_? t). as shown in Figure 9e.

Let Po (n) and P? (N) denote the distribution of the run lengths n for consecutive "zeros" and "ones", respectively, in the input signal 155. The probability that an isolated "zero" will occur then a high to low transition is therefore P0 (n = l). The speed of occurrence of the isolated "zeros" can be represented as follows: speed of 0 isolated = Po (l) where n0 and ni represent the average length for a run of "zeros" and "ones", respectively. The average time interval in which output 8261 remains in a high state before the subsequent transition high to low can be represented as follows: persistence of time = (ni +? n0) Xbit. the conservation property of the edge transition detector 820 can be represented by the parameter?. In a mode in which the minimum interval correlator 1090 includes the type D reversal device,? may be equal to 1. Alternatively in a mode wherein the minimum interval correlator 1090 includes a single non-re-activatable downstream trigger 1102,? can be equal to 0. If the durations of the consecutive runs are independent the average value of the input 1212 can be represented as follows: V1212 ct (speed of 0 isolated) x F (x - xb? T) x (13) (persistence time) An expression analogous to equation (13) is used for the input 1214 of the rising edge transition comparator of the output 8262. The filtered output 1224 may be represented as follows: V1224 a (no -? N?) P? (1) + (np -? N?) P9 (1) F (x - xbit) (14) According to one embodiment, the average value Vi224 of the low pass filter of the output 1224 can be used to control x using a negative feedback. The gain in the small signal has the desirable characteristic of being independent of x_it.

DIGITAL FEEDBACK CIRCUIT Figure 13a illustrates a digital implementation of a feedback circuit 830, according to one embodiment of the invention. In this embodiment, the feedback circuit 830 comprises locks RS 1310 and 1320, reversing devices type D positive 1330 and 1340 and gates AND (y) 1350 and 1360, counter up / down stage N 1370, binary counter stage M 1390 , and digital to analog converter (DAC) 1380. The up / down counter 1370 includes an up counting clock input (Clku) 1372 and a down counting input (ClkD) 1374. Figures 13b-e illustrate changes in the bit rate fbít of the input signal 155, the signal applied to the Clku 1372 input, the signal applied to the ClkD 1374 input, and the Analog output 1384 of DAC 1380.

The feedback circuit 830 receives inputs 832? and 8322 the outputs 826? and 8262 of the minimum interval correlator 840. The input 834 of the feedback circuit 830 receives the input signal 155. The node 832? is connected to "set" the input 1312 of the lock 1310, and the node 832 is connected to "set" the input 1322 of the lock 1320. The lock outputs 1316 and 1326 are connected to the inputs 1332 and 1342 of the reversal devices type D 1330 and 1340 respectively. The clock input 1392 of the counter 1390 receives the input signal 155 via the input 834. The output of the terminal count (TC) 1396 is switched to "reset" the inputs 1314 and 1324 of the locks 1310 and 1320, respectively. The clock inputs 1334 and 1344 of the D-type reversal devices 1330 and 1340 are connected to the output of the second stage (Qi) 1394 of the 1390 counter.

The gate (AND) 1350 receives inputs from the non-reversing outputs 1336 and 1346 of the D-type reversal devices 1330 and 1340, respectively, and the TC-1396 output of the 1390 counter. The AND gate (y) 1360 receives inputs from the investment outputs 1338 and 1348 of the reversal devices type D 1330 and 1340 respectively, and the TC output 1396 of counter 1390. Output 1358 of gate AND (y) 1350 is connected to input Clku 1372, and output 1368 of gate AND (y) 1360 is connected to input ClkD 1374.

In one embodiment, the up / down counter 1370 generates a parallel binary expression that is monotonically related to the difference between the number of pulses applied to the Clku 1372 input and the ClkD 1374 input. In another aspect, the up / down 1370 counter generates a parallel binary signal representing a successive approximation for the speed estimate signal RE using a succession of stage sizes, which may, for example, vary with the pulse pattern applied to the Clku 1372 input and the ClkD 1374 input. "set" inputs 1312 and 1324 of locks 1310 and 1320 receive pulses from outputs 826? and 8262, respectively, of unipolar minimum interval correlators 1090 and 1092 when x > tb_t is detected by the edge transition comparator 820 via nodes 832? and 8322.

A pulse generated by unipolar minimum interval correlator 1090, which is active in descending edge transitions in input signal 155, sets output 1316 in a high state. Similarly, a pulse generated by the unipolar minimum interval correlator 1022, which is active in the rising edge transitions in the input signal 155, sets the output 1326 in a high state.

The counter 1390 counts the number of transmissions on the input signal 155 module 2M, where M is equal to, for example, 4. The output of the second stage (Qi) 1394 records the time of the D type 1330 reversing devices and 1340 of each transitional room goes down to high in the input signal 155, storing the prevailing state of the locks 1310 and 1320 respectively.

The TC 1396 output passes from a transition to a high state after each of the low to high 2M transitions in the input signal 155, and goes through a transition to a low state after the next low to high transition in the signal input 155. The rising edge of the TC 1396 output can be close to the center of the pulses of the Qi 1394 output. A high state on the TC 1396 output allows the AND (and) 1358 and 1368 gate outputs, and resets the locks 1310 and 1320 in a low state.

The 1358 output goes through a transition to a high state when the TC 1396 output is in a high state if the Non-reversing outputs of the D-type reversal devices 1336 and 1346 are in a high state, bringing the state of the up / down counter 1374 forward by a count. The 1368 output goes through a transition to a high state when the TC 1396 output is in a high state if the reversal outputs of the D type 1338 and 1348 reversing devices are in a high state, decreasing the status of the up / down counter 1370 for a count. The state of the up / down counter 1370 increases when the unipolar minimum interval correlators 1090 and 1092 detect that x > Xit, and decreases when no unipolar minimum interval correlation 1090 and 1092 detect that x > xb_.t- The status of the up / down counter 1370 is maintained when only one of the unipolar minimum interval correlators 1090 and 1092 detects that x > bit- The binary signal at the output of the up / down counter 1376 can be used to control x using negative feedback.

The feedback circuit 830 can generate a digital signal at the output 836 using, for example, the output 1376 of the up / down counter 1370. Alternatively, the feedback circuit 830 can generate an analog signal at the output 836 using, for example, the output 1384 of the DAC 1380, whose input 1382 is connected to the output of the counter 1376.

Figure 13b illustrates an increase in the bit rate of the input signal 155 of .f __. T? a, f__t2 > fbii at time t = 0. Before t = 0, the negative feedback must keep the period x of the interval generator 810 close to 1 / __t ?. The minimum interval correlator 840 can detect the change in bit rate, which results in a change in the speed of the pulses appearing in both inputs of the locks 1312 and 1324. The presence of pulses in both inputs of the locks 1312 and 1324 cause the non-reversing outputs of the D-type reversal devices 1336 and 1346 to pass through a transition to a high state, connecting with the Clku input 1372 as shown in Figures 13c.

In Figure 13d, the ClkD 1374 entry does not connect immediately, after t = 0 since x > 1 / f__t2- Figure 13e illustrates the analog output 1384 of the DAC 1380 which is driven by the digital expression generated by the up / down meter 1370 with, for example, monotonic count states. In the counter up / down the count up proceeds while x > 1 / ___t2, and stops when x = 1 / f "b_t2 • SPEED SELECTOR The speed selector 310 tracks changes in the bit rate frequency of the input signal 155 while rejecting transient errors in the speed estimate signal RE, which can be accounted for by a vibration and a path dependent variation in the input signal 155. Figures 14a-b are block diagrams of implementations of a speed selector 310, in accordance with two embodiments of the invention.

In the first embodiment, which is shown in Figure 14a, the speed selector 310 comprises a speed translation 1402, which includes a function block 1410 and a function block 1420. The speed translation 1402 may receive in the signal of the input speed estimate RE, which is generated by the discrete speed detector 301 of Figure 5. The speed estimate signal RE can also be filtered before translation by 1402.

In a second aspect, which is shown in Figure * 14b, the speed selector 310 comprises the speed translation 1402 and a speed estimation filter. The speed estimation filter includes a block of speed correction 1430, an adaptive filter 1440, a filter control 1450, a speed change detector 1460, an expected speed comparator 1470, and an addition 1480. The correction block 1430 receives the estimated signal at input 1432 of speed RE which can be generated by, for example, the continuous speed detector 301 of Figure 8. The adaptive filter 1440 receives at the input 1442 the output 1434 of the speed correction block 1430. The output of the filter 1440 can be applied as an alternative entrance to the speed translation 1402.

The speed translation block performs a one-to-one mapping of an estimated line speed on the control signals RSi and RS2 that appear at the output nodes 316 and 318 respectively. The input 1412 of the function block 1410 and the input 1422 of the function block 1420 receive an estimate of the line speed, for example the speed estimate signal RE of the discrete velocity detector 301 or the output of an adaptive filter 1430. Function block 1410 generates control signals RSi at node 316. Function block 1410 can implement, for example, the function represented implicitly by equation (5) or the relation represented by equation (8).

Function block 1420 generates the control signal RS2 at node 318. Function block 1420 can implement, for example, the function represented implicitly by equation (5) or the relationship represented by equation (8).

Several conventional techniques can be used to carry out the one-to-one mapping. For example, an analog computer can be used to convert the speed estimate signal RE to control signals RSi and RS2. Alternatively, the speed detector 301 or speed selector 310 may be implemented using an A / D converter whose binary outputs select an appropriate input from a lookup table for control signals RSi and RS2. The search table can include specific speed parameters for xED and fc.

In yet another implementation, the speed selector 310 may include a finite state machine for converting a digitized rate estimate signal RE to control signals RS3, and RS2 using, for example, an appropriate allocation algorithm.

When used in conjunction with, for example, the continuous speed sensor 301 of Figure 8, the speed correction 1430 and the adaptive filter 1440 can improve the accuracy of the speed estimation line, which is received by the speed translation 1402. The speed estimation signal RE is applied to the input 1432 of the speed correction block 1430. The output 1434 of the correction block 1430 goes to the input 1432 of the adaptive filter 1440, the input 1462 of the speed change detector 1460, and input 1472 of the expected speed comparator 1470.

Input 1444 controls the response of filter 1440.

The input signal 155 is also applied via node 314 to inputs 1464 and 1474 of the speed change detector 1460 and the expected speed comparator 1470, respectively. The speed at which operations are performed at the speed change detector 1460 and the expected speed comparator 1470 can be controlled by means of the input signal 155 via the input 314.

The speed change detector 1460 includes the output 1466, and the expected speed comparator 170 includes the output 1476. The outputs 1466 and 1476 are combined in addition 1480, and are applied to the 1452 input of the 1450 control filter. control 1450 includes the output 1454, which is applied to the input 1444 of the adaptive filter 1440. The output of the adaptive filter 1446 connects to inputs 1412 and 1422 of the function block 1410 and 1420, respectively.

The estimated speed signal RE appearing at input 312 of speed sensor 301 may include predictable and measurable error. The correction block 1430 can implement an algorithm, which compensates for the discrepancy between the signal for estimating the speed RE and the bit rate of the input signal 155 measured or predicted.

The adaptive filter 1440 generates a modified speed estimate REF, which depends on the current value of the speed estimation signal RE and the relationship of the current values with the past behavior of the speed estimation signal RE. Considering the behavior of the speed estimation signal RE and the modified speed estimation signal REF at a set of discrete times, the current and past values of the speed estimate signal RE can be represented by the set of values. { Ei} while the corresponding values of the modified velocity estimate signal REF can be represented by the set of values. { REF;)} . The adaptive filter 1440 can, for example, construct a modified rate estimate signal REF from the speed estimate signal RE using the following relationship: k k-1 REpic =? ak_i REi + S b k-j RE Fj (15)? = - ° _ = - where a. and bj are coefficients that can be programmed by means of the argument of input 1444.

Filter 1440. which includes an implementation of equation 15, reacts quickly to change the speed estimate signal RE when the coefficient ai is large, and conversely, reacts slowly when the coefficients ai are large for i »1. Bj coefficients can be selected to affect the persistent memory of a particular estimate. The restriction S? Ai = 1 can prevent the deviation in the modified velocity estimation signal REF, while the constant? bj < 1 can prevent instability. The coefficients ai and bj can be selected based on patterns in the variation of the speed estimate signal RE following a correction by the speed correction 1430.

The speed change detector 1460 can distinguish small or insignificant fluctuations in the speed estimate signal RE, which is applied to input 1462, of rapid or significant changes in the speed estimate corrected. The speed change detector 1460 can construct a histogram of the speed change values, and calculate the probability that a change in current speed is significantly different from the speed changes in the recent past. The magnitude of the output 1466 may reflect the magnitude or duration of a change in the current speed estimate relative to previous changes. The response time to perform the speed change discrimination can be established by the speed of the transitions at input 1464.

The expected speed comparator 1470 can compare the speed estimate signal RE with known common line speeds or previous values of. { REj ..}. that have persisted for a significant time interval. The magnitude of the output 1476 may reflect the proximity of the speed estimate signal RE at known speeds or persistent previous speeds. The response time for comparing the speed estimate signal RE against expected speeds can be established based on the transitions at input 1464.

Although what is currently considered to be the preferred embodiments and methods of the present invention has been illustrated and described, it should be understood by those It is well known to those skilled in the art that various changes and modifications can be made, and that elements can be replaced by their equivalents without departing from the true scope of the invention.

In addition, various modifications may be made to adapt a particular element, technique or implementation of what is described by the present invention without departing from the central scope of the invention. Therefore, it is intended that this invention is not limited to the particular embodiments and methods described herein, but that the invention includes all modalities that fall within the scope of the claims.

It is noted that in relation to this date, the best method known by the applicant to carry out the said invention in practice, is that which is clear from the present description of the invention.

Having described the invention as above, the content of the following is claimed as property.

Claims (21)

1. A method for recovering a clock signal from an input signal having a variable bit rate, said method characterized in that it comprises the steps of: estimating a minimum time interval between the transitions in the input signal; determination of a central frequency of a filter. narrowband based on the estimated minimum time interval; and extraction, at the determined central frequency, of the clock signal of the input signal.

2. The method according to claim 1, characterized in that it further comprises the steps of: after the extraction step, generating a first plurality of pulses corresponding respectively to transitions in the input signal; adjusting the duration of each of the first pluralities of pulses based on the estimation of the variable bit rate; and introducing into the narrow band filter the first plurality of adjusted pulses. ~~

The method according to claim 1, characterized in that the estimation step further comprises the step of: determining the variable bit rate of the input signal based on the estimated minimum time interval.

The method according to claim 1, characterized in that the estimation step comprises the steps of: generating a second plurality of pulses that correlate with the transitions in the input signal; and adjusting the duration of each of the plurality of second pulses, such that the minimum time intervals between the transitions in the input signal correspond to the durations of the corresponding second plurality of pulses.

The method according to claim 2, characterized in that the extraction step comprises the steps of: generating a phase correction signal proportional to a difference between a phase of the clock signal and a phase of the first plurality of pulses; Y adding a phase correction signal to a center frequency of an oscillator that generates the clock signal.

The method according to claim 2, characterized in that the extraction step comprises the steps of: generating a frequency correction signal proportional to the difference between a clock frequency and a frequency of the first plurality of pulses; and adding the frequency correction signal to a center frequency of an oscillator that generates the clock signal.

The method according to claim 4, characterized in that the adjustment step comprises the steps of: generating a voltage signal corresponding to the determined difference; and generating a current signal proportional to the voltage signal, wherein the current signal centers the duration of each of the second plurality of pulses.

A method for recovering the clock signal of an input signal having a variable bit rate, characterized in that said method comprises the steps of: estimating a minimum time interval between transitions in the input signal; generating a first plurality of pulses corresponding respectively to the transitions in the input signal; adjusting the duration of each of the first plurality of pulses based on the minimum time interval and the introduction of the first plurality of pulses adjusted in a narrow band filter; determination of the center frequency of the narrowband filter in the estimated minimum time interval; and extracting in the narrow band filter of the clock signal from the first plurality of adjusted pulses.

The method according to claim 8, characterized in that the estimation step comprises the steps of: generating a set of delayed input signals by passing the input signal serially through a set of delayed segments, wherein the set of delayed segments delay the input signal based on a set of predetermined delay times, respectively; comparison of the input signal with the set of delayed signals generated; and generating a control signal based on a sum of predetermined delay times that are less than the minimum time interval between transitions in the input signal.

. The method according to claim 8, characterized in that the estimation stage comprises the steps of: generating a set of delayed input signals by passing the input signal serially through a set of programmable delayed segments, wherein the set of programmable delayed segments delay the input signal based on a set of predetermined delay times, respectively; comparison of the input signal with the set of delayed signals generated; and generating a control signal based on a sum of predetermined delay times that are less than the minimum time interval between transitions in the entrance sign,

. The method according to claim 8, characterized in that the estimation stage comprises the steps of: generating one or more delayed transitions by passing the input signal through a programmable time interval generator, wherein the transitions are delayed they are generated based on a set of delayed time values, respectively; comparison of the transitions in the input signal with the delayed transitions generated; and adjusting one or more values of delay times, such as one of the time values that correspond to the minimum time interval between transitions in the input signal.

An apparatus for recovering a clock signal from an input signal having a variable bit rate *, said apparatus characterized in that it comprises: a speed detector for estimating a minimum time interval between the transitions in the entry signal; a transition detector for the generation of a first plurality of pulses corresponding respectively to the transitions in the input signal; a narrow band filter for extracting the clock signal from the first plurality of adjusted pulses; and a speed selector for adjusting, based on the estimated minimum time interval, the duration of each of the first plurality of pulses and a center frequency of the narrowband filter receiving the first plurality of adjusted pulses.

The apparatus according to claim 12, characterized in that said speed detector comprises: a set of delayed segments connected in series for the generation of a set of delayed input signals based on a set of predetermined delay times, respectively; and a set of locks connected to the set of delayed segments, respectively, for the comparison of the set of delayed signals with the input signal and the generation of a control signal based on a sum of the predetermined delay times that are less than the minimum time interval between transitions in the input signal.

The apparatus according to claim 12, characterized in that said speed detector comprises: a time interval generator for the generation of a set of delayed transitions based on a set of delay time values, respectively; and an edge transition comparator connected to the programmable time interval generator for comparing the set of delayed transitions with the transitions in the input signal and for adjusting one or more of the delay time values, such that one of the delay time values corresponds to the minimum time interval between the transitions in the input signal.

The apparatus according to claim 12, characterized in that it further comprises: a calibration source for the generation of a calibration signal having a set of predetermined bit rates, wherein the velocity detector estimates the reference bit rate of the calibration signal; and a response monitor for the determination of differences between the predetermined reference bit rates and the estimated bit rate and for the speed selector setting until one of the differences is equal to zero.

16. The apparatus according to claim 12, characterized in that the speed detector comprises: a interval generator for the generation of a second plurality of transitions that correlate to the transitions of the input signal; a transition comparator for determining a difference between the duration of each of the second plurality of transitions and a time interval between each of the transitions in the input signal; and a feedback means for adjusting the duration of each of the second plurality of transitions until the determined difference is equal to zero.

17. The apparatus according to claim 12, characterized in that the narrow band filter comprises: a phase comparator for the generation of a phase correction signal proportional to the difference between a phase of the clock signal and a phase of the first plurality of adjusted pulses; and a first adder to add the phase correction signal to a center frequency of an oscillator that generates a clock signal.

. The apparatus according to claim 12, characterized in that the narrow-band filter further comprises: a frequency comparator for the generation of a frequency correction signal proportional to the difference between a frequency of the clock signal and a frequency of the first plurality of adjusted pulses; and a second adder for the addition of the frequency correction signal to a center frequency of an oscillator that generates the clock signal.

. The apparatus according to claim 16, characterized in that the interval generator comprises: a single activated edge trigger for the generation of a second plurality of pulses that correlate with the transitions in the input signal.

. The apparatus according to claim 16, characterized in that the interval generator comprises: one or more activated edge delay elements of restart for the generation of a second plurality of pulses that correlate with the transitions in the input signal.

21. An apparatus for recovering a clock signal from an input signal having a variable bit rate, said apparatus characterized in that it comprises: a speed detector for estimating a minimum time interval between the transitions in the signal of entry; a speed selector connected to the speed detector; a transition detector connected to the speed selector; and a narrow band filter connected to the transition detector and the speed selector, such that the speed selector adjusts, based on the estimated minimum time interval, the duration of each of a plurality of pulses generated by the transition detector and a center frequency of a narrowband filter for extracting a clock signal from an input signal.