MXPA00004173A - Method and apparatus for automatically reducing cross-talk between wires coupled to a common network device - Google Patents

Abstract

A method of adjusting the sensitivity of a receiver requires the association of a network address of a remote network device (16), such as a computer, with a first port (62) of a multiport network device (60), such as a switch. The reception of the network address of the remote network device at a second port of the multiport network device indicates the possible occurrence of a cross-talk condition between networks coupled to the first and second ports. Accordingly, the sensitivity of a receiver associated with the second port is reduced in an attempt to reduce the sensitivity thereof to a point at which cross-talk signals, generated as a result of the cross-talk condition between networks coupled to the first and second ports, are no longer detected. The sensitivity of the receiver may be reduced by increasing anoise threshold level below which signals are not detected.

Description

METHOD AND APPARATUS TO AUTOMATICALLY REDUCE DIAPHONY BETWEEN WIRES COUPLED TO A COMMON NETWORK DEVICE FIELD OF THE INVENTION The present invention relates generally to the field of network communications and more particularly to reducing crosstalk between separate network wires coupled to respective gates of a multi-port network device. BACKGROUND OF THE INVENTION In a typical network environment, a switch can be used to facilitate communications between various segments of a single network, or between different and separate networks, in an intelligent and accordingly efficient manner. Specifically, a switch can, over time, learn the network addresses of the various network devices in segments of the same or different networks, coupled to the respective switches of the switch by respective wires. These wires may include copper wires in the form of twisted pair wires or coaxial cables. The wires can further be classified as comprising Category 1-5 cabling in accordance with the EIA / TIA 568 specification. By examining each packet received in the switch, the switch is capable of making a determination as to whether the received packet should be propagated outside. of a particular gateway and on a particular segment or network, with oase in the destination address information associated with the received packet. Figure 1 illustrates an exemplary packet switching environment 1010, wherein packet communication between three different networks ie the networks 1014, 1016 and 1018, is facilitated by a switch 1012. Of course, the switch 1012 can include any amount of gates and in this way to connect any number of networks. The network 1014 is coupled to a gate 1020 of the switch 1012 by a cable 1022, the network 1016 is coupled to a gate 1024 by a wire 1026, and the network 1018 is coupled to the gate 1028 by the wire 1030. Each of the gates 1020, 1024 and 1028 are coupled to a switching core 1032 (also known as "switching fabric") through which the packets between the gates propagate or direct. The switching core 1032 is illustrated coupled to a memory resource in the form of a Dynamic Random Access Memory (DRAM) 1034, which provides a buffer resource to the buffer core 1032. All valid packets received in the switching core 1032 are propagated to the DRAM 34 in a conduit 1035 coupled to the DRAM 1034 and the switching core 1032. An address search device 1036 is illustrated investigating the conduit 1035 for the purpose of learning address information and constructing an address lookup table that maps network device addresses to gateways of switch 1012. In packet switching environment 1010 illustrated in FIG. 1, wires 1026 and 1030 are illustrated physically distant from each other. Accordingly, a transmission of packets 1038 between networks 1014 and 1016 can occur without generating any crosstalk on wire 1030. Figure 2 on the other hand illustrates an alternate packet switching environment 1040 where wires 1024 and 1030 are crammed together into a common cable 1342. In this situation, so-called "near-end" crosstalk (or signal leakage) may occur between the wires 1026 and 1030. Crosstalk will likely occur in immediate proximity to the gates 1024 and 1028, when a packet is transmitted from one of the gates, while the other listens on its respective wire. Consider, for example, the transmission of a packet from network 1014 to network 1016 as illustrated at 1044. As the packet is transmitted from gate 1024, the signal strength is at maximum. As the wire 1026 is brought into immediate proximity with the 1030 wire while propagating-a high-power transmission signal, there is the possibility that a crosstalk signal is generated as indicated at 1046 on the wire 1030. A gate receiver 1028 may be in a state of maximum sensitivity for the purposes of reception, and accordingly, the signal Crosstalk may be received at gate 1028 and addressed to switching core 1032. Since the address search device 1036 may previously have learned the source address of a packet, incorporated by the crosstalk signal associated with a device in the network 1014 , an incorrect modification to an address search table may occur. Specifically, the address search device 1036 may indicate the source address of the crosstalk signal belonging to a device in the network 1018. This in turn may result in "packet-switching errors". The previously identified problem discussed with reference to Figure 2 may be exacerbated when the wires 1026 and 1030 are not well insulated. For example, when wires 1026 and 1030 comprise unpaired twisted pair or unshielded (UTP = Unshielded T isted Pair) wires of Category 1, the possibility of generating crosstalk signals may be increased. In addition, in certain network environments, the power and frequency levels of the transmission signals may increase the susceptibility of the network to wire crosstalk.

COMPENDIUM OF THE INVENTION According to the invention, a method for adjusting the sensitivity of a receiver is provided. When detecting the reception of a network address, identifying a remote network device, in a gate of a multiple gate network device, a determination is made as to whether the network address is associated with an additional gate of the network device of the network. multiple floodgates If so, the sensitivity of a receiver associated with the gate automatically depletes from a first level of sensitivity to a second level of sensitivity. Other features of the present invention will be apparent from the accompanying drawings and the detailed description that follows: BRIEF DESCRIPTION OF THE DRAWINGS The present invention is illustrated by way of example and is not limited to the accompanying drawings in which similar references indicate similar elements. Figures 1 and 2 are block diagrams, which indicate exemplary packet switching environments. Figure 3 is a diagrammatic representation of a multi-resident unit (MDU = Multi-Dwelling Unit) within which the present invention may be employed.

Figure 4 is a diagrammatic representation of an access concentrator, according to an exemplary embodiment of the present invention. Figure 5 is a block diagram showing structural details of a line card, in accordance with an exemplary embodiment of the present invention. Figure 6 is a block diagram illustrating a switch, in accordance with an exemplary embodiment of the present invention. Figure 7 is a block diagram illustrating the structural details of a receiver, in accordance with an exemplary embodiment of the present invention, which may be incorporated within the physical layer device. Figure 8 is a flow diagram illustrating a method, in accordance with an exemplary embodiment of the present invention, for initiating and implementing an interrupt service routine (ISR = Interrupt Service Routine) that identifies with doors in which has detected a crosstalk condition. Figure 9 is a flow chart illustrating a method, in accordance with an exemplary embodiment of the present invention, for implementing a polling loop that adjusts the sensitivity level of a receiver. DETAILED DESCRIPTION A method and apparatus for adjusting the sensitivity of a receiver used in the reception of data transmissions within a communications network are described. In the following description, for the purpose of explanation, numerous specific details are set forth to provide a complete understanding of the present invention. It will be evident, however, for a person skilled in the art, that the present invention may be practiced without these specific details. Figure 3 is a diagrammatic representation of a multi-residence unit (MDU) 10 within which the present invention may be employed. The MDU 10 is illustrated to include two constructions 12 and 14 and it is illustrated that each of the constructions 12 and 14 includes a number of units 16 which can be apartments, hotel rooms, offices or cabins. The units 16 may be located on multiple floors within each of buildings 12 and 14. The MDU 10 may be a high-rise apartment complex, garden-style apartment complex, hotel or any other structure that includes discrete residential facilities. The present invention may also be employed within office complexes, factories, showrooms or any other environment within which two or more devices may require networks. Each unit 16 is illustrated to include a network connection, in the exemplary form of an RJ-11 socket 18, which is coupled to a carrier medium, in the exemplary form of the old simple telephone service cabling (POTS = Plain Old) Telephone Service) 20 comprising a bundle of wire pairs. The wiring 20 may include unshielded twisted pair (UTP = Unshielded Twisted Pair) wiring which is used to establish a telephone connection network through constructions 12 and 14. In this case, the cabling 20 can be category 1 or category 2 cabling, as defined by the EIA / TIA 568 specification. The cabling 20 can further comprise a number of cable pairs, each pair is for a specific unit 16, which are packed together as a single cable inside a liner. ~~ Within each unit 16, a regular telephone unit 22 and a computer 24 (via a network interface card (NIC), or other adapter) are illustrated attached to the cabling 20 by a RJ-socket 11 18, respective. The wiring 20 within each of the constructions 12 and 14 is illustrated coupled to a main distribution frame panel (MDF = Main Distribution Frame) 26 within a wiring cabinet 28 of the construction 14. The MDF panel 26 engages the wired 20 to the public switched telephone network (PSTN = Public S itched Telephone Network) 30. The MDF panel 26 is also illustrated. coupled to an access concentrator 32, which is constructed in accordance with the teachings of the present invention, for providing access to the Internet 34 to devices coupled to the cabling 20 such as the illustrated computers 24. While the present invention is described below within the context of an implemented network, using POTS 20 cabling as a carrier medium, it will readily be appreciated that the teachings of the present invention can be implemented within any network environment within which switching occurs, such as a network using a carrier medium which supports higher transmission speeds such as, for example, Category 5 cabling in the form of twisted pairs of four wires that can transmit data at 100 Mbps to support technologies such as Ethernet or ATM Asynchronous Transfer Mode. Figure 4 is a schematic representation of the access concentrator 32 that illustrates additional details regarding the construction of this unit. A first computer 24 within the construction 12 is illustrated coupled by an external adapter 38 with a respective RJ-11 socket, the adapter 38 includes a physical layer (PHY) device that allows reliable network communication over the POTS 20 cabling. In an exemplary embodiment, adapter 38 is the HomeRun adapter developed by Tut Systems, Inc. of Pleasant Hill, CA. A second computer 24 is illustrated to include an internal network interface card (NIC) 40, which similarly includes a physical layer (PHY) device to facilitate communication over the POTS cabling 20. Especially passing the concentrator 32, a rack or chassis 42 houses a series of line cards 44 which are coupled to a multiplexer card (MUX) 46. The chassis 42 includes 17 slots in which the line cards 44 can be inserted. In a basic configuration, a collection of 8 line cards 44 is coupled to a single MUX card 46 by an lOBaseT connection. The MUX card 46 can concentrate up to sixty-four 1 Mbps LANs coupled to respective gateways of the 44 line cards in an aggregated LAN of 10 Mbps or 100 Mbps. The added LAN can be connected to a local router 48, local server 50, or a Wide Area Network (WAN) using a WAN TI card 52. Figure 5 is a block diagram illustrating additional structural details of a line card 44, in accordance with an exemplary embodiment of the present invention. . The line card 44 includes a switch 60, which may be an Ethernet switch based on a Texas Instruments TNETX3100 switch. The switch 60 can provide 8 gates of 10 Mbps and two gates 10/100 Mbps. The switch 60 also has a direct interface between each gate 62 and a physical layer (PHY) device 66. In an exemplary embodiment of the present invention, the PHYs 66 can be PHYs HomeRun, developed by Tut Systems, Inc. to facilitate POTS cabling of the communication server. The PHYs 66 can also be conventional Ethernet PHYs, depending on the carrier medium of networks supported by the various gates of the switch 60. Eight of the gates 62 are illustrated coupled by the physical layer devices 66 LANs 68. In one embodiment, a LAN 68 it can be implemented in each of the units 16 illustrated in Figure 3 using the POTS cabling 20. In this case, the twisted pair cabling of each of the units 16 will be coupled to a respective PHY. Two of the gates 64 and 65 are illustrated coupled to respective LOBaseT PHYs 70. Conveniently, gates 62 and 64 may be gates labeled "downstream" and gate 65 labeled an "upstream" gate. The gate 64 allows the line card 44 to be connected in series with additional line cards 44, while the gate 65 is considered as an "output" gate. As illustrated at 72, the gates 64 and 65 can optionally be coupled to an additional line card, a MUX card, or an external lOBaseT gate. The line card is also illustrated which includes a power supply 74 and a microprocessor 76. In an MDU 10, such as that illustrated in the Figure 3, the users on the LANs 68 (coupled to each of the gates 62 of the switch 60) are typically individual users without affiliation to users coupled to the other LANs 68. This can create security considerations, since a user on a LAN can supposedly be able to investigate network traffic transmitted from and to a user in another LAN 68 coupled to switch 60. Furthermore, it is conceivable that a user in a first LAN 68 is able to configure "a network server, which can be accessed by users of the other LANs without using the services of an Internet Service Provider (ISP = Internet Service Provider) .This may be undesirable in certain situations.For data security purposes, it is desirable that a user coupled to any one of LANs 68 does not see traffic transmitted to and from users connected to other LANs 68. In addition, data transmissions must be secured in both directions (ie in the it is upstream and downstream indicated by arrows at 78). Figure 6 is a block diagram illustrating an exemplary implementation of the switch 60, shown in Figure 5. A switching core 80 (also known as a switch fabric) is illustrated to include gates 62, 64 and 65, a set of gates for media access control (MAC = Media Access Control) 82 and an interface for external address matching (EAM = External Address Match) 84. An external physical layer (PHY) device 66 is coupled to each gate. Each of the PHYs 66 may be a PHY lOBaseT or a specialized PHY to facilitate communications over POTS cabling 20. In an exemplary embodiment, this specialized PHY may comprise the PHY HomeRun, developed by Tut Systems, Inc. of Pleasant Hill, California. The switching core 80 also includes a data path, switching logic, network statistics logic and internal simple address comparison (none shown). The switching core 80 can support both connection addressing that allows transmission at a destination gate before full reception of a packet and store-and-send addressing, which requires that the entire packet be received before it propagates to a packet. destination gate. Connection addressing reduces total switching latency, while store-and-forward addressing provides the ability to filter out frames that contain errors. Three packet sending modes are also implemented by the switching core 80, i.e., an internal simple address comparison mode, or an external address matching mode (EAM = External Address Match) and a frame taking mode. The EAM 84 interface facilitates multi-address support per gate, as opposed to the simple address mode comparison that only supports one gate address. Accordingly, in order to support multiple users in a LAN 68 coupled to each gate 62/64/65, the switching logic in the form of an address search device 86 provides a power in the form of an indication signal of gate (EAM) 90 to the EAM interface 84 of the switching core 80. The EAM signal 90 is a multi-bit signal (e.g., a 16-bit EAM signal [0., 15]) indicating the switching core 80 to which gate (s) a packet must be sent inside the switch. The EAM signal 90 can also indicate whether the switching core 80 will implement the simple address comparison. For example, EAM [15] can already be adjusted or readjusted to select between single direction or external address coupling modes. In the case that EAM [15] is readjusted (ie, low), the external address matching mode is implemented and EAM [0., 14] represents a mask of the gates to which the packet will be sent. For example, if the packet is to be sent to gates 00.07 and 14, the signal EAM 90 would be "100000010000001". A memory resource in the form of a Dynamic Random Access Memory (DRAM) 92 is coupled to the switch core 80 via a DRAM 94 conduit. The DRAM 92 implements a packet buffer and activates the core of the packet. switching 80 to support both simple access operation and access-burst-location operation. Specifically, all valid packets are passed through the DRAM conduit 94 to the DRAM 92. The address search device 86 is illustrated coupled to the DRAM conduit 94 and actively investigate the DRAM conduit 94 to implement the external address coupling functionality of the switch 60. The address search device 86 captures the destination address of a packet placed in the DRAM conduit 94 by the switching core 80 for the purpose of generating the EAM signal 90. In an exemplary embodiment of the present invention, the device 86 it comprises the TNETX15AE address search device manufactured by Texas Instruments of Dallas, Texas. The address search device 86 implements a number of state machines 98 (e.g., search state, deletion, addition, find and age machines) to manage and maintain a look-up table of address 100, in a memory of Static Random Access Memory (SRAM) associated external 102. The address search table 100 maps the source addresses (eg MAC addresses) of packets that are received in the switch 60 to the gates 62/64/65 of the switch 60 in which the respective received packets, as determined by the address search device 86. The process of constructing address search table 100 is referred to as the "learning" of addresses by switch 60. Once an address / gate register has been created in the address search table 100, the switch 60 is able to make a determination as to which gate will be addressed a package that has a "learned" destination address. In one embodiment, the address search device 86 may be coupled to an EEPROM (not shown) that stores a sequence of initialization codes that allow the address search device 86 to be auto-configured. In an alternate embodiment, the initialization data may be downloaded from a microprocessor 120 coupled to the address search device 86. As mentioned above, all valid packets received in the switch 60 are passed through the DRAM 94 conduit. switch 80 can write data to the DRAM 92 in a specific format that is recognized by the address search device 86, to determine the correct destination address and source of the packet. The address search device 86 is capable of detecting the start of a new packet of information from a flag octet included in the packet transmission. For example, a row-direction selection (DRAS) signal and a column-direction selection (DCAS) signal can be used to identify the position of a sending pointer, a top-level one-byte flag (byte) and if the middle of the byte contains the start of a frame code. The data bit 35 can be de-estimated (ie set to 0), to denote the start of a packet. In the first speech transmission in the DRAM conduit 94, the data bits 27-24 of a line may indicate an active gate number and the marking signal or column address reference may also be used to identify the address data of the gate. destination and source in the DRAM conduit 94. Accordingly, in an exemplary embodiment for determining the start of a frame, the address search device 86 tests the data bit 35 of a direct pointer and decodes the first half of the byte. of flag in DRAM 94 conduit. In this case, the data bit 35 must be zero, indicating a valid start of packets as opposed to a link buffer. Using the address-column mark, the destination address and the source address of the packet are extracted for external processing by the address search device 86. The address search device 86 then performs a search cycle when accessing the table address search 100, chooses an appropriate EAM code to send output to the EAM interface 84 of the switching core 80 and then outputs this EAM code. Further details regarding the investigation procedure are provided in the published data sheets for the TNETX3100 Ethernet switch and the Texas Instruments TNETX15AE address search device. The address search device 86 implements interrupts to indicate changes to the address search table 100. Specifically, interrupts are generated by the address search device 86 to indicate when a new address is added to the Table 100 (i.e. interrupt NEW (NEW)) when an address changes gates (ie an interruption CHANGE), when an address changes gates and is safe, and when an address is eliminated by an aging or aging process. To indicate an interruption to an external device, such as a micro-processor 120, the address search device 86 estimates an interrupt signal 122 (e.g. signal EINT). The address search device 86 further includes an interrupt register 124, an interrupt mask register 126 and a new gate register 128. The interrupt register 124 is accessible and readable at all times by an external device and contains reference information to all current interruptions. The interrupt mask register 126 facilitates the masking of interrupts, by only allowing the interrupt signal 122 to be estimated without the interruption condition corresponding to a mask value stored there occurring. For example, interrupt signal 122 can only be estimated if there is a 1-to-1 correspondence between bits stored in interrupt register 124 and interrupt mask register 126. In the case of a NEW (NEW) or a CHANGE interrupt ( CHANGE), the identification of the new gate with which the address is associated, is provided in the new gate register 128. The contents of the registers 124, 126 and 128 are accessible by an external device such as the microprocessor 120 for a data feed / output conduit (DIO = data input / output) 130. The microprocessor 120 is illustrated coupled to an associated memory such as a random access memory (RAM = Random Access Memory) 132, which stores a service routine of interrupt (ISR = Interrupt Service Routine) 134, a poll loop 136, a set of global variables 138 and a set of local variables 140. The microprocessor 120 is capable of accessing and executing the sequences of instructions comprising the ISR 134 and the polling loop 136, which according to this is illustrated to reside completely or at least partially, within the local memory (e.g. cache memory) of the microprocessor 120. The global variables 138 and the local variables 140 are similarly illustrated capable of residing within registers in the microprocessor unit 120. The logic and functionality of the present invention, however, may reside in software, physical equipment or any combination thereof. For the purposes of the present specification, the term "machine-readable medium" will be taken to include any memory resource (e.g. RAM 132), both internal and external to a machine, that is capable of storing a sequence of instructions that they can be executed by a machine (for example the microprocessor 120) and that causes the machine to perform the substance of any of the functions specified in the present specification. Agree with this, the term "machine-readable medium" should be taken to include but not be limited to solid state memories, magnetic memories, optical memories, chemical memories or carrier wave signals. The microprocessor unit 120 is also illustrated to include a general purpose serial interface (GPSI = General Purpose Serial Interface) 142 by which the microprocessor 120 is capable of propagating data to any of the PHYs 66, whereby the data may transmitted from the PHYs 66 to the microprocessor 120 over the connection 144. In an exemplary embodiment of the present invention, each of the PHYs 66 operates in a slave mode and the microprocessor unit 120 accordingly is able to control the operation of the PHYs 66 through GPSI 142. Each of the PHYs 66 supports a variety of control and status registers. Specifically, each PHY 66 includes an interference threshold register 146 that is implemented within an interference follower 148 within a PHY 66 receiver. Figure 7 is a block diagram illustrating additional structural details of an exemplary receiver 150 that they can be incorporated within each of the PHYs 66. The receiver 150 is illustrated to include a socket 160 that receives a female connector coupling with the receiver 150 with a POTS 152 wiring network. Multi-loop waveform comprising a received signal, it propagates from the socket 160 to a Butterworth filter 162, which implements a spectral mask that limits the bandwidth of the received signal between 5.5 and 9.5 MHz. The filtered signal is then propagated from the Butterworth filter 162 to a differential amplifier 164 and then to an envelope detector 166 that outputs an envelope signal derived from the received, amplified signal and f. iltrada. This envelope signal is then fed through a unipolar operational amplifier (opamp) 168, where it is supplied to the pulse detector logic 170, which is illustrated sends and receives signals from the threshold logic 172. Specifically, the logic of threshold 172 propagates signals to the pulse detector logic 170, which indicates an interference threshold level with comparators included within the pulse detector logic 170. For this purpose, the threshold logic 172 includes an interference follower 148 which it implements an interference threshold level state machine and includes the interference threshold register 146. The interference threshold register 146 stores an 8-bit sequence, which may be increased or decreased among others, by the state level machine. interference threshold. The 8-bit sequence is propagated to a digital-to-analog converter which transforms the 8-bit sequence into an analog signal indicating the interference threshold level to the comparators of the pulse detector logic 170. The output of the The pulse detector logic 170 is then propagated to a decoder within the PHY 66. Referring again to Figure 6, the microprocessor 120 is illustrated capable of increasing the 8-bit sequence stored in the interference threshold register 146 by the connection 144. The operation of the exemplary switch 60 shown in Figure 6 will now be described with reference to the flow charts shown in Figures 8 and 9. Specifically, Figure 8 is a flow chart illustrating a method 200 in accordance with an exemplary embodiment of the present invention, for initiating and implementing the ISR 134. The method 200 is initiated in step 202 wherein the address search device 86 interrupts the micropr ocessor 120 when estimating interrupt signal 122. In an exemplary embodiment, interrupt mask register 126 is configured such that only NEW (NEW) or CHANGE interrupts cause the interrupt signal 122 to be estimated. It will be appreciated that an interruption of change will be generated in the situation described above with reference to Figure 2, where a crosstalk signal is received at gate 1028, the source address of a packet incorporated within this crosstalk signal has previously been associated with another gate such as gate 1020. In response to the estimation of the interrupt signal in step 202, the microprocessor 120 initiates the ISR 134 in step 204. The ISR 134 interrogates the address search device 86 by the relevant MAC address that generates the interrupt for the reason of interruption (i.e. if it has been detected a new address or if a change of address has been detected). This information is provided in the interrupt register 124 which is accessible by the microprocessor 120. In step 206 the ISR 134 accesses the new gate register 128 of the address search device 86. The ISR 134 according to this, is capable to identify the new gate 62, 64, 65 with which a medium access control address (MAC = Media Access Control) is to be identified (for example gate 1028). In step 207, the ISR 134 stores the relevant MAC address and information of the determined interrupt ratio. In the decision box 208, the ISR 134 makes a determination of whether the interruption is generated as a result of a known MAC address appearing in a new gate (and therefore in a new network) or if the interruption was generated as a result from an unknown MAC address that appears in a gate. In the event that the interruption is generated as a result of a known MAC address appearing in a gate (i.e. a CHANGE interrupt is generated), method 200 proceeds to step 210, where ISR 134 eliminates the relevant MAC address of address search table 100. Specifically, as a communication path becomes inoperative when the MAC address changes gate, the step of eliminating the MAC address preemptively chooses the MAC address removed by a process of aged. The communication path in this way can possibly be restored before a relevant layer can terminate a relevant protocol. In step 212, the ISR 134 confirms that the new gateway in which the MAC address was viewed is coupled to a predetermined network type. Specifically, the ISR 134 is able to identify the new gate using the contents of the new gate register 128. The ISR 134 may also have access to a gate / network type mapping according to which the ISR 34 is able to identify the type network associated with the new gate. In an exemplary embodiment, the ISR 34 can determine whether the new gate is coupled to a local area network HomeRun (LAN) operating in accordance with protocols developed by Tut Systems, Inc., or the like. In step 214, the ISR 134 updates a global variable 138 associated with PHY 66 of the new gate, to indicate that the crosstalk event has occurred with respect to the new gate. For example, a respective global variable can be set to a logical one (1), to indicate the crosstalk event. Method 200 then ends in step 216. Accordingly, it will be appreciated that method 200 is controlled by interruption. Turning now to Figure 9, a flow chart illustrating a method 240, in accordance with the exemplary embodiment of the present invention, for implementing the polling loop 136, is illustrated. Method 240 operates in a continuous loop, and is not controlled by interruption. Method 240 starts at step 242, where a numeric variable, which has a maximum value equal to the number of gates (and according to this PHYs) within switch 60, is readjusted to zero (0). In step 244, a global variable under consideration B copies an associated local variable and the relevant global variable is released in step 246. In step 248, a determination is made as to whether a local variable under consideration fits a one logical, and accordingly indicates that an associated gate receives a crosstalk signal and that a network or line coupled to the gate experiences a crosstalk condition. Otherwise, the numeric variable is increased by one in step 250, such that a subsequent successive global variable and local variable associated with an additional gate and PHY will be processed and considered during a subsequent iteration of the steps 244- 248 Alternatively, in case the relevant local variable is set to a logical one (1), the polling loop 136 interrogates the associated PHY 66 in step 252, to determine the interference threshold level ^ as indicated by the interference threshold register content 146 of the PHY 66. In step 254, the interference threshold level for the PHY 66 is increased by a predetermined value (for example 10 mV), in order to decrease the sensitivity of the receiver within which the PHY 66 is incorporated. Specifically, the microprocessor 120 can output a serial signal on the connection 144, which is received by the interference follower 148 and results in the 8-bit sequence, stored in the interference threshold register 146 which is incremented by an amount default Accordingly, the propagation threshold level propagated to the comparators of the detected pulse logic 70 is increased. By increasing the interference threshold level and decreasing the sensitivity of the PHY 66, the polling loop 136 seeks to do the PHY 66 less susceptible to detect crosstalk signals that typically have a lower voltage amplitude than the valid signals. In decision box 256, a determination is made as to whether the revised interference threshold level of PHY 66 is greater than a predetermined maximum interference threshold level. If so, the relevant PHY 66 is not reconfigured to implement the revised interference threshold level and the method proceeds directly to the decision box 262. Alternatively, the PHY 66 under consideration is reconfigured to use the threshold level of revised interference in step 260. A determination is then made in decision box 264 where the numeric variable indicating any of the PHYs of switch 60 has reached a predetermined maximum number (i.e. the total number of PHYs included within the switch 60). If so, the numeric variable is reinitialized again in step 242 and method 240 performs another iteration. Otherwise, the variable number is increased by one and the next iteration begins in step 244. In summary, the present invention proposes to detect a crosstalk condition, when a network address appears in a gate of a network device. multiple gates that, under normal operating conditions, will not receive packets with the relevant network address. The present invention seeks to address the crosstalk condition by dynamically lowering the sensitivity of a receiver of a gate for a network or line in which the crosstalk condition occurred. Accordingly, a method and apparatus for dynamically adjusting the sensitivity of a receiver to reduce crosstalk conditions have been described. Although the present invention has been described with reference to specific exemplary embodiments, it will be apparent that various modifications and changes may be made to these embodiments, without departing from the broadest scope and spirit of the invention. Accordingly, the specification and drawings should be considered in an illustrative rather than restrictive sense.

Claims (40)

1. CLAIMS 1. A method for adjusting the sensitivity of a receiver, the method is characterized in that it includes the steps of: associating a network address of a remote network device with a first gate of a multiple gate network device; detecting the reception of the network address in a second gate of the multiple gate network device; and automatically adjusting the sensitivity of a receiver, associated with the second gate, from a first level of sensitivity to a second level of sensitivity, in response to the reception of the network address in the second gate. The method according to claim 1, characterized in that the step of automatically adjusting the sensitivity includes the step of automatically raising an interference threshold level by a predetermined increment to decrease the sensitivity of the receiver. 3. The method according to claim 1, characterized in that it includes the steps of determining whether the second level of sensitivity of the receiver exceeds a minimum sensitivity level and, if so, then retaining the first level of sensitivity for the receiver. The method according to claim 1, characterized in that the step of associating includes the step of constructing an address search table that records the association between the first gateway and the network address. The method according to claim 4, characterized in that the network address comprises a media access control address (MAC = Media Access Control) of the remote network device. The method according to claim 1, characterized in that the step of detecting includes the steps of receiving a packet in the second gate of the multiple gate network device and extracting the network address from the packet. The method according to claim 4, characterized in that the step of detecting includes the step of accessing the address search table to identify the first gate associated with the network address of the remote network device. The method according to claim 1, characterized in that the step of detecting includes the steps of initiating an interrupt notification to a processor and executing an interrupt service routine within the processor in response to the interrupt notification. The method according to claim 1, characterized in that it includes the step of indicating the reception of the network address in the second gate using a global variable associated with the second gate. The method according to claim 9, characterized in that it includes the step of cycling through a plurality of global variables, each associated with a respective one of a plurality of gates of the multiple gate network device and adjusting the sensitivity of at least one of a plurality of receivers associated with the plurality of gates according to an indication that is provided by at least one global variable. The method according to claim 1, characterized in that it includes the step of determining whether a network coupled to the second gate is a predetermined network type. The method according to claim 11, characterized in that it includes the step of determining whether the network coupled to the second gate is implemented over old simple telephone wiring (POTS). The method according to claim 4, characterized in that it includes the step of removing the network address from the address search table, in response to receiving in the second gate of the multiple gate network address. The method according to claim 1, characterized in that the multi-gate network device comprises a switch. 15. A method for adjusting the sensitivity of a receiver, the method is characterized in that it includes the steps of: detecting the reception of the network address, identifying a remote network device in a gate of the multiple gate network device; determining whether the network address is associated with an additional gate of the multiple gate network device; and if so, then automatically adjust the sensitivity of a receiver associated with the gate from a first level of sensitivity to a second level of sensitivity. The method according to claim 15, characterized in that the step of automatically adjusting the sensitivity includes the step of automatically raising an interference threshold level by a predetermined increment to decrease the sensitivity of the receiver associated with the gate. The method according to claim 15, characterized in that it includes the steps of determining whether the second level of sensitivity of the receiver exceeds a minimum level of sensitivity and if so, then retaining the first level of sensitivity for the receiver. 18. The method according to claim 15, characterized by including the step of determining which includes the step of accessing address search information that records respective associations between network addresses of remote devices and gates of the multi-gate network device . The method according to claim 15, characterized in that it includes the step of retaining the first sensitivity level of the receiver associated with the gate, if the network address is not associated with the additional gate of the multiple gate network device. 20. The apparatus for adjusting the sensitivity of a receiver, the apparatus is characterized in that it includes: a memory for recording an association of a network address of a remote network device with a first gate of a multiple gate network device; a detector for receiving the network address in a second gate of the multiple gate network device; and an adjuster, coupled to be a detector for automatically adjusting the sensitivity of a receiver, associated with the second gateway from a first level of sensitivity to a second level of sensitivity, in response to the network of choice of the network address in the second gate . 21. The apparatus according to claim 20, characterized in that the detector comprises a direction search device. 22. The apparatus according to claim 20, characterized in that the adjuster comprises a processor. 23. The apparatus according to claim 20, characterized in that the adjuster automatically raises an interference threshold level by a predetermined increment to decrease the sensitivity of the receiver. 24. The apparatus according to claim 20, characterized in that the adjuster determines whether the second level of sensitivity of the receiver exceeds a minimum sensitivity level and, if so, then retains the first level of sensitivity of the receiver. 25. The apparatus according to claim 20, characterized in that the memory stores an address search table that records the association between the first gate and the network address. 26. The apparatus according to claim 20, characterized in that the network address comprises a media access control (MAC) address of the remote network device. 27. The apparatus according to claim 20, characterized in that the detector detects the reception of a packet in the second gate of the multiple gate network device and extracts the network address from the packet. 28. The apparatus according to claim 25, characterized in that the detector accesses the address search table to identify the first gate associated with the network address of the remote network device. 29. The apparatus according to claim 20, characterized in that the detector initiates an interrupt notification to the adjuster and the adjuster executes an interrupt service routine within the adjuster in response to the interrupt notification. 30. The apparatus according to claim 20, characterized in that the adjuster indicates the reception of the network address in the second gate using a global variable associated with the second gate. The apparatus according to claim 30, characterized in that the adjuster cycles through a plurality of global variables, each associated with a respective one of a plurality of gates of the multiple gate network device and adjusts the sensitivity of at least one of a plurality of receivers associated with the plurality of gates according to an indication that is provided by at least one global variable. 32. The apparatus according to claim 20, characterized in that the adjuster determines whether a network coupled to the second gate is a predetermined type of network. 33. The apparatus according to claim 32, characterized in that the adjuster determines whether the network coupled to the second gate is implemented over the simple old telephone wiring. (POTS). 34. The apparatus according to claim 25, characterized in that the detector removes the network address from the address search table in response to its reception in the second gate of the multiple gate network address. 35. The apparatus according to claim 20, characterized in that the multi-gate network device comprises a switch. 36. Apparatus for adjusting the sensitivity of a receiver, the apparatus is characterized in that it comprises: detection means for receiving the address of the network, identifying a remote-network device in a gate of the multi-gate network device; determining means for when the network address is associated with an additional gate of the multiple gate network device; and adjustment means for automatically adjusting the sensitivity of a receiver, associated with a gate, from a first level of sensitivity to a second level of sensitivity, in response to reception of the network address in the additional gate, if the address of network is associated with the additional gate of the multiple gate network device. 37. The apparatus according to claim 36, characterized in that the adjustment means automatically raise an interference threshold level by a predetermined increment to decrease the sensitivity of the receiver associated with the gate. 38. The apparatus according to claim 36, characterized in that the adjustment means determine whether the second level of sensitivity of the receiver exceeds a minimum level of sensitivity and, if so, then retains the first level of sensitivity for the receiver. 39. The apparatus according to claim 36, characterized in that the determination means access address search information that registers respective associations between network addresses of remote devices and gates of the multiple gate network device, to determine whether the address of network is associated with the additional gate of the multiple gate network device. 40. A machine readable medium that stores a sequence of instructions that, when executed by a machine, cause the machine to perform the steps of: detecting the reception of the network address, associated with the first gate in a second gate of a multi-gate network device; and automatically adjusting the sensitivity of a receiver, associated with the second gate, from a first level of sensitivity to a second level of sensitivity, in response to the reception of the network address in the second gate.