MXPA00002044A - Switching system for telecommunications network - Google Patents

Abstract

A switching system for a telecommunications network, including a switching matrix, a transport interface for receiving signals from a plurality of I/O ports, the signals being arranged in channels of at least a first and a second format, a plurality of cross-connections for switching the signals between the I/O ports via the switching matrix;and a server operatively associated with the switching matrix and including format exchanging circuitry operable to receive a signal arranged in the first format and to rearrange the signal into the second format, thus producing a converted signal, and to transmit the converted signal to the switching matrix for eventual output.

Description

SWITCHING SYSTEM FOR TELECOMMUNICATIONS NETWORK Field of the Invention The present invention relates to switching systems for telecommunication networks. Background of the Invention The public public switched telephone network (PSTN) operates worldwide under different standard values. These standards indicate among other things, methodology to make digital signals compatible and to multiplex these digital signals in the carriers. The majority of the world has digitalized traffic traveling between the central offices. There are two widely used standards for compatibilizing digital signals, known as the standards of law A and the law μ. There are also two basic standards for multiplexing voice signals, generally known as DS-A and CEPT-1 for the lowest level of multiplexed bearers. Generally, the μ and DS-1 laws are used in North America and the A and CEPT-1 laws in Europe. The North American and European systems can also be called the American hierarchy (asynchronous hierarchy) and the ITU digital hierarchy (plesiochronic digital hierarchy). The individual voice channels are digitized using the law A or the law μ in what is called digital currents DS-0. These currents are then multiplexed in the carriers using time division multiplexing (TDM) techniques. For North America, the carrier DS-1 is the carrier multiplexed at a lower level, having up to 24 DS-0 channels per carrier, while in Europe CEOT-1 is the smallest multiplexed carrier, having up to 30 DS-0 channels per carrier with two additional channels reserved for the frames and optionally the signaling or as an additional DS-0 channel. Each of the aforementioned multiplexed characters has its own control and synchronization functions, carried as excess bits that have been added to the stream, or as previously described in a control channel selected for this purpose. Higher order multiplexing exists when multiple DS-1 / CEPT-1 currents are being multiplexed into even larger carriers such as DS-3 for North America and CEPT-3 for Europe. In Japan, a different hierarchy is used. The fiber optic transmission systems use DS-3 or CEPT-3 as the basis for transmission, with an additional control for control and synchronization, and here there is also higher order multiplexing. In North America, the standards for fiber optic transmission are known as the North American synchronous optical network (SONET), while in Europe, the synchronous digital hierarchy (SDH) standard is used. There is often a need to interconnect between two transmission standards, for example when a telephone call is made from Europe to North America, a transatlantic call. In order to achieve this, the signal decays a signal up to the individual DS-0 level, converting from one compatibilization method to another and remultiplexing using the appropriate techniques for the destination. Digital interconnections are well known in the art. In the United States, they are covered by several standards including Bellcore TR-N T-000233, which is incorporated herein by reference. Digital interconnections are generally used to interconnect a large number of multiplexed transmission streams, such as DS-1 or CEPT-1 currents over a long period of time. Some of the individual DS-0 channels that are part of the current can be interconnected to the destinations in that case the interconnection that is capable of performing this function is known as a 1/0 interconnection. In the case that higher order currents can be interconnected this would be designated in the description of the interconnection, in such a way that an interconnection can connect individually with DS-3, DS-2, DS-1, and its signals DS-0 Individuals will be described as an interconnection 3/2/1/0. The Bellcore standard TR-nwt-000233, mentioned earlier, describes the generic criteria for these interconnections. In a standard arrangement of the generic digital interconnections of the prior art, as shown in Figure 1, the signal first goes to a transport interface 10 and then proceeds through the interconnection matrix 1 to another transport interface 10 in the destination side. The transport interfaces on each side perform the physical layer and logical layer functions. Thus, any physical or logical transformation is carried out in the transport interface, before entering the interconnection matrix, or after leaving it. In the case of the typical transatlantic call mentioned above, the previous conversion method would have to be done at the transport interface. It should be noted that each input and output signal must be connected to a transport interface and therefore the conversion function must be duplicated in each and every transport interface that the function must perform. While other functions such as marking, monitoring of logical errors and data link between facilities in extended DS-1 superframe format (ESF) can be handled in the transport interface, it would be more economical not to duplicate the function of conversion, or other functions, in each and every transport interface. A digital interconnection for SONET is described in the US patent no. 5,365,518 and consists of an interface layer, an interconnection flask, and a command server. The general server combines a multiplexer / demultiplexer and slot exchange circuits with server controls and a switching module to handle both the high speed command and the data in the matrix. Thus the server is able to achieve the interconnection of the individual DS-0 currents. The system uses a signal similar to SONET throughout the matrix, and as a result the system can not be used to transfer North American standards to European servers, since the matrix operates only under one standard. All conversions and other transport functions must be performed in the transport interface before entering the matrix. An electronic digital interconnection system is known from US Patent No. 5,193,087. In this system the digital interconnection is a spatial matrix, in which any input can be interconnected to any output without significant time delay. The matrix uses an encoded electronic signal to allow all aspects of the input signal to be recreated at the output, including any bipolar variation. However, again any conversation has to be done in the transport interface. A pulse width modulation (PWM) coding technique is also described in US Patent 5,193,087. A digital interface between the different formats of the digital signal is described in: Digital Interface Between the SLC96 Digital Loop Carrier System and a Local Digital Switch, TR-TSY-000008, edition 2, August 1987. The interconnection of the IT access signals and El are governed by the following standards respectively: Bellcore TR-170 and ITU-T G .796. This has been the need for a long time for a method to perform the functions of the transport interface in a more economical way. The descriptions of all the references mentioned above and throughout the present description are incorporated by reference. SUMMARY OF THE INVENTION A switching system for a telecommunications network, including a switching matrix, a transport interface for receiving signals from a plurality of ports 1/0 is provided in accordance with a preferred embodiment of the present invention, arranging the signals in channels of at least a first and a second format, a plurality of interconnections to switch the signals between the 1/0 ports by means of the switching matrix and a server operatively associated with the switching matrix and which includes circuits of exchange of format used to receive a signal arranged in a first format and to rearrange the signal in the second format, thus producing a converted signal, and for transmitting the converted signal to the switching matrix for its eventual output. Further in accordance with a preferred embodiment of the present invention the first format and the second format each include the following: at least a part of the North American hierarchy (asynchronous hierarchy), at least a part of the ITU digital hierarchy (Plesynchronic digital hierarchy) ) and at least part of the Japanese hierarchy, where the first and second formats are not identical. Further in accordance with a preferred embodiment of the present invention the first and second formats each have a tributary, and each tributary includes one of the following: a tributary E-1, and a tributary T-1. Additionally according to a preferred embodiment of the present invention the interconnections are operable to demultiplex channels in the first format and remultiplex channels in the second format. In addition, according to a preferred embodiment of the present invention, the interconnections are operable to perform, in demultiplexed channels, at least one of the following: conversions from law A to law μ and conversions from law μ to law A. In addition, according to a preferred embodiment of the present invention, the plurality of interconnections are included in the switching matrix, the interconnection matrix serves as a pair for carrying signals of the first format and of the second format. In addition, according to a preferred embodiment of the present invention, the interconnections also include a converter matrix that serves to demultiplex the channels, perform at least one of the conversions from law A to the law μ and conversions from the law μ to law A in the demultiplexed channels and to remultiplex the channels. Additionally in accordance with a preferred embodiment of the present invention, the converter matrix serves to perform demultiplexing independently of demultiplexing. Further in accordance with a preferred embodiment of the present invention, the channels received at the interface in one of the first and second formats are passed to the switching matrix in the same first or second format. Also provided in accordance with another preferred embodiment of the present invention, a switching system for a telecommunications network, including a switching matrix, a transport interface for receiving signals from a plurality of 1/0 ports, the signals are assigned to mutiplexed channels, a plurality of interconnections to switch the signals between the I / O ports by means of the switching matrix, and a server operatively associated with the switching matrix and including circuits that serve to receive a signal arranged in the format multiplexing and to perform the functions of the logical layer in the multiplexed channel, and to transmit the converted signal to the switching matrix for the eventual output. Further in accordance with a preferred embodiment of the present invention, the logical layer function includes at least one installation data link in the extended superframe DSl format. Also provided in accordance with another preferred embodiment of the present invention is a method for converting arranged signals into multiple channels of a first format to signals arranged on multiple channels of a second format and route signals, including the steps of receiving the signals of a plurality of I / O ports, route the signals through a matrix to a central converter, demultiplex the channels of a first format into individual voice channels, convert the individual voice channels into channels of the second format, remultiplex the channels of the second format, and route the remultiplexed channels through a matrix to the appropriate output ports. Also in accordance with a preferred embodiment of the present invention the first and second formats include each, one of the following: at least a part of the American hierarchy (asynchronous hierarchy), at least a part of the ITU digital hierarchy (plesiochronic digital hierarchy), and at least part of the Japanese hierarchy, where the first and second formats They are not identical. Additionally according to a preferred embodiment of the present invention the first format is El and the second Ti format. Further in accordance with a preferred embodiment of the present invention the step of demultiplexing the channels of a first format into individual voice channels is followed by a step of converting the law A to the law μ. Also provided in accordance with another preferred embodiment of the present invention is a method for realizing the logical layer functions in a switching system for a telecommunication network, including receiving signals from a plurality of 1/0 ports, arranging the signals in the multiplexed channels, providing a plurality of interconnections to switch the signals between the I / O ports through the switching matrix to receive an arranged signal in the multiplexed format to perform the logical layer functions in the multiplexed channel, and transmit the converted signal to the commutation matrix for the eventual output. Still in accordance with a preferred embodiment of the present invention, the logical layer function includes at least one installation data link in the extended superframe format DSl. BRIEF DESCRIPTION OF THE DRAWINGS For a still better understanding of the invention and to show how it can be carried out, reference will be made, only by way of example, to the attached drawings in which: Figure 1 shows a switching system of the prior art that includes conversion functionality between the standards; Figure 2 is a simplified block diagram of a switching system according to an embodiment of the present invention. Figure 3 is a simplified block diagram of the switching system of the embodiment of Figure 2, showing in greater detail three of the elements of Figure 2; and Figure 4 is a simplified block diagram of the central converter of Figure 2 showing switching, control and conversion circuits. Detailed Description of the Invention Reference will now be made to Figure 1, which shows a switching system of the prior art that allows conversion between the formatted signals according to the different standards, and more specifically, one that allows conversion between the signals formatted according to European and North American standards. Without being limiting in any way, the invention and the prior art will be described using the lowest order multiplexing for each standard, it being understood that the same techniques are applied to higher order multiplexed signals. A transport interface 10 and a switching matrix 12 are shown in the switching system of Figure 1. The operation is controlled by means of a central processor 14, known as a common unit. The interface layer 10 is adapted to receive arranged input signals either as signals DS-1 or CEPT-1 which are carried on a transmission line TI or El respectively, or as higher order multiplexed signals complying with European standards, American or Japanese. As explained above, each multiplexed DS-1 or CEPT-1 channel can contain up to 24 individual voice channels in the North American standard and up to 31 individual voice channels in the European standard. The incoming channels may have been compatibilized using the standards of Law A and the law μ. The interface layer consists of a logical layer 16 and a physical layer 18. The logical layer 16 performs the functions that include framing, logical error monitoring, multiplexing, demultiplexing, and various command functions. The physical layer 18 performs the functions that include the coding of the fill, the monitoring of physical errors, and the monitoring of the loss of signal. In addition to the above, the logic layer 16 of FIG. 1 comprises a converter 20. The converter 20 provides the interface level 10 with additional functionality for converting the signal formats. The conversion between the signal formats is done at the DS-0 level. Thus after demultiplexing the signal the required conversion will be performed. The converted signal will then be converted to the interconnected hue transport format and sent to the matrix. Alternatively, the conversion can be performed at the transport interface on the output side. In any case, the final signal format must match that which is connected to the physical layer before being sent for transmission to the transmission line. For example, if the transport interface 10 is connected to an EW-1 line, the transport interface 10 must ensure that the signals at the output of the physical layer 18 coincide with the CEPT standard. The central processor 14 issues control signals to ensure that conversion to the appropriate format is performed in a logical layer (either before or before the array) before it is received in the physical layer of the interface. All logical layer functions that are required including clipping, framing and error monitoring are duplicated on all transport interfaces that are connected to similar transmission fills. Thus if the 100 Tl and 100 El are connected to an interconnection of the type shown in Figure 1, and each line requires conversion, at least 100 type 20 converters will be required. The switching matrix 12 receives signals from the interface layer and it routes them to their final destinations. The matrix is usually designed to handle a specific matrix transport format signal, and therefore the conversion will be made in all signals first to the matrix transport format. In case this signal allows the coding of the original framing format, such as DS-1 and CEPT-1, the conversion of the framing formats will be done in one of the two transport interfaces (input or output) and then it is carried through the interconnection matrix. The transport layer comprises a plurality of ports (not shown). A disadvantage of the prior art is that each port (not shown) of the interface must contain additional circuits (hardware) in order to perform the conversion. This adds costs and makes a digital interconnection using such equipment difficult to update, since each individual transport interface must be updated.

Reference will now be made to Figure 2 which is a simplified block diagram of a switching system 20 according to a first embodiment of the present invention. In Figure 2 the switching system 30 consists of a transport interface 32, a switching matrix 34 and a central converter 36. The operation of the switching system is controlled by a central processor 38. The interface layer 32 preferably comprises a layer physical logic 40 and a physical layer 42 as above, but or comprises a converter. In contrast, the signals are converted to the matrix transport format and sent to the switching matrix 34 preserving the framing, and preferably the line code in the format in which they are received. This can be achieved using various methods, including a pulse width modulation (PWM) coding technique described in US Pat. No. 5,193,087, the description of which is incorporated by reference. The switching matrix 34 is thus adapted to transfer signals of all formats as will be explained in more detail below. If conversion is required, the switching matrix 34 preferably routes the input signals to the central converter 36 which serves to convert between signals formatted according to different standards, as will be described in detail below. This conventive signal is then returned to the switching matrix 34, and then routed to another transport interface 32 which is connected to the destination. Reference will now be made to Figure 3 which is a simplified block diagram of the switching system 30 of the embodiment of Figure 2 which shows in great detail, the interface layer 32 and the connections between the transport interface 32, the matrix switch 34 and the central converter 36. A plurality of interface units 32.1..32.n, each consisting of a plurality of ports (not shown) receive the input signals, preferably in the form of IT and El or higher data streams and can perform physical layer functions and some logical layer functions on those signals. The signals are converted to a matrix transport format, maintaining the original framing and coding formats. The switching matrix 34, preferably a space matrix, consists of interconnections for two-way connections of these data streams between the transport interface 32 and the central converter 36. The central converter 36 is a central converter with a DS interconnection capacity. -0 / E0 also here called "narrowband interconnection server" which has I / O ports 40 for connection to the EI-TI 38 channel coded in two directions. The terms "ti" and "El" are used in this context to indicate that the coding and framing of the original signals are preserved in the matrix transport format, and have not been converted but only encoded. 36 operates to demultiplex channels El and input IT into individual voice channels, hereinafter referred to as DSO The converter comprises DS-0 interconnections (not shown) that preferably allow DS-0 channels to be individually interconnected between ports 1 / 0 The DS-o channels can be routed through the interconnections, to appropriate 1/0 ports where they can be remultiplexed to return to the switching matrix 34. In the previous arrangement, it is observed that remultiplexing in the output is independent of the demultipelxed in the input.These partially populated multiplexing channels can be eliminated the output demultiplexer channels are formed from the DS-0 channels that are d available regardless of their origin. Reference will now be made to Figure 4, which is a simplified block diagram of a mode of the central converter 36 of Figure 2. The central converter 36 of this embodiment preferably comprises up to eight units of narrow band 50.1..50.8. (NBU) each of which operates to process multiplexed channels. The NBUs are from each of one of the four types, a TNBU, an ENBU, an ANBU, and a UINBU. A TNBU supports IT channels. An ENBI supports IT channels. An ANBU is an ENBU that means that it supports El channels, but has the additional function of supporting the conversion of law A to the law μ. An UNBU is a TNBU, this means that it supports IT channels, and has the additional function of supporting the conversion of the μ law to the A law. The channel DS-P channels can be remultiplexed directly to an IT channel and contrary to DS-0 channels of an IT channel can be remultiplexed directly to an El channel. Thus the TNBU and ENBU do not perform conversions of the law A to the μ law, but convert between El and Tl formats. This feature allows data communication to be transported from one format to the other, since in the transport of data a conversion from law A to law μ should not be performed, since this coding is only for voice transmission. NBU 50.1-50.8 may include at least two, and in some cases four of the NBU types mentioned above.

The exact numbers of each type will be selected by the experts according to the circumstances of each switching system. Optionally in a preferred embodiment only seven of the NBU 50.1..50.8 are used and the eight serves as a backup. The backup NBUs should preferably be an ANBU or U? BU such that they can provide backup protection for a maximum possible number of functions. The central converter 36 comprises two narrow band control units 52.1 and 52.2 to control the operation. The second unit 52.2 is preferably a backup unit. Two power supply units 54.1 and 54.2 preferably energize the unit with a 1 + 1 protection by means of a load sharing scheme. The DS-0 channel interconnections, referred to above in relation to Figure 3, are provided by means of two narrowband interconnection units NBX 56-1 and 56-2. Again the second unit 56.2 is provided for backup purposes. The individual interconnections can include 2-way DS-0 interconnects, and 2-way beam interconnections, which are interconnected between two groups of DS-or continuous time slots, and which are particularly useful for providing an interconnection of nx 64k, in where n = 2-24 for TI and 2-31 for El, according to the different number of DS-channels in IT and El. Other interconnections that can be used are the framing interconnections that allow the first bit of a frame IT of the first time slot of a frame The intact pass through the NBX 56, allowing for example a complete IT including but not limited to its framing, data link, CRC4, and Ti.403 to pass internationally through The Access interconnections can be provided by allowing the interconnection of 2 senses between time slots DS-0 TI and El. A DS-0 interconnection can include a signal interconnection, depending on the DS-0 definition used in an system given and typically individually adjustable for each interconnection. It is appreciated that signal interconnection is generally covered by standards; the interconnections of TI and El access signals, for example, are governed by the following standards respectively: Bellcore TR-170 and ITU-T G.796. It is further appreciated that the components of the present invention preferably comply with applicable standards. The bit transparency of the IT framework allows a fixed data link to pass intact. This is supported by the SLC906 TI interface, described in Digital Interface Between the SLC96 Digital Loop Carrier System and a Local Digital Switch, TR-TSY-000008, edition 2, August 1987, whose description is incorporated as a reference. The TI framing bit transparency also allows the transmission of a TI signal within an El signal. This allows the central management of the facility's data link in the extended superframe (ESF) DS-1 format to be handled in the central converter 36 and not in individual transport interface logical layers is handled in the central converter 36 and not in individual transport interface logical layers. the entire range of international access interconnection characteristics can be handled in the central converter 36 including the optional zero code suppression for each DS-0 interconnection separately, providing framing bit transparency in which the framing bits and channels pass from an incoming signal to an outgoing signal without being recreated. Standard alarms are also handled, typically including the alarm indication signal (AIS), frame loss (LOF), and remote alarm indication (RAI). The central converter 36 is timed by a central clock (not shown) by means of two clock damping units (CBU) 58.1 and 58.2. The second unit 58.2 again serves preferably as backup. The system buses including the clock bus 60, the PCM bus 62, the control bus 64 and the power supply bus 66, are preferably dual redundant. In the operation of central converter 36, the incoming channels El and TI are received in the NBU. The channels are then synchronized to a CBU clock signal, allowing the DS-0 channels to propagate synchronously through the interconnections of the NBX 56. The signals TI and El terminate in the NBU 50.1..50.8 and demultiplexed in the initial DS-0 channels. In the units ANBU and UNBU, the conversion addition stage between the law A and the law μ is carried out in this stage, this means after demultiplexing and before sending by means of the interconnections. The NBX 56 acts as a server to the NBU 50 and handles the signaling interconnections as well as allowing the exchange of the time slots of the DS-0 channels. The DS-0 channels are sent through the interconnections of the NBX 56 to the appropriate NBU for the output, where they are remixed into the IT and El channels as appropriate and then sent back to the switching matrix 34. This is provides a switching system in which the signals can be converted centrally between the TI and El format and between the μ law and the A law. Optionally, the switching system can provide the central management of the installation data link in the format of extended superframe (ESF) DS-l also known as TI.403. Other logical layer functions can also be handled in the central converter. It is appreciated that several features that are described for clarity in the context of separate embodiments may also be provided in combination in a single embodiment. On the contrary, several features of the invention which for brevity are described in the context of a single embodiment may also be provided separately or in a suitable sub-combination. Those skilled in the art will appreciate that the present invention is not limited to what has been shown and described in particular above. Rather, the scope of the present invention is defined only by the following claims:

Claims (19)

1. NOVELTY OF THE INVENTION Having described the invention as above, property is claimed as contained in the following: CLAIMS 1. - A switching system for a telecommunications network, characterized in that it comprises: a switching matrix:; a transport interface for receiving the signals of a plurality of ports 1/0, the signals are arranged in the channels of at least one first and one second format; a plurality of interconnections to switch the signals between the 1/0 ports by means of the switching matrix; and a server operatively associated with the switching matrix and comprising format exchange circuits that serve to receive a signal arranged in the first format and to rearrange the signal in the second format, thereby producing a converted signal, and to transmit the signal converted to the switching matrix for an eventual output.
2. 2. - A switching system according to claim 1 and characterized in that the first and the second format each comprise one of the following: at least a part of the American hierarchy (asynchronous hierarchy), at least a part of the ITU digital hierarchy (plesiochronic digital hierarchy), and at least part of the Japanese hierarchy, where the first and second formats are not identical.
3. 3. - A switching system according to claims 1 or 2, characterized in that the first format and the second format each have a tributary, and each tributary consists of one of the following: a tributary E-1; and a tributary T-l.
4. 4. - A switching system according to claims 1,2, or 3, characterized in that the interconnections serve to demultiplix channels in the first format and remultiplex channels in the second format.
5. 5. - A switching system according to claim 4, characterized in that the interconnections serve to perform, in the demultiplexed channels, at least one of the following: conversions of the law A to the law μ; and conversions of the law μ to law A.
6. 6. - A switching system according to any one of the preceding claims and wherein the plurality of interconnections make up the commutation matrix, the commutation matrix serves to carry signals of the first format and the second format.
7. 7. - A switching system according to any of the preceding claims, characterized in that the interconnections also comprise a converter matrix that serves to demultiplex channels, perform at least one of the conversions of law A to law μ and conversions of the law μ to the A law in the demultiplexed channels, and to remultiplex the channels.
8. 8. - A switching system according to claim 7, characterized in that the converter matrix serves to perform the remultiplexing independently of the demultiplexing.
9. 9. - A switching system according to one of claims 1 to 6, characterized in that the channels received at the interface in the first format or the second format are passed to the switching matrix in the same first or second format.
10. 10. - A switching system for a telecommunications network, characterized in that it comprises: a switching matrix: a transport interface for receiving signals from a plurality of ports 1/0, the signals being arranged in multiplexed channels; a plurality of interconnections for switching the signals between the I / O ports by means of the switching matrix; and a server operatively associated with the switching matrix and comprising circuits that serve to receive an arranged signal in the multiplexed format and perform logic layer functions on the multiplexed channel and transmit the converted signal to the switching matrix for an output eventual.
11. 11. - A switching system according to claim 10, characterized in that the logical layer function includes at least one installation data link in the extended superframe format DSl.
12. 12. - A method for converting arranged signals in multiplexer channels of a first format to signals arranged in multiplexer channels of a second format and routing those signals, characterized in that it consists of the steps of: receiving signals from a plurality of ports 1 / 0; route those signals through a matrix to a central converter: demultiplex the channels from a first format to individual voice channels; convert the individual voice channels of the second format; remultiplex the channels of the second format; and route the remultiplexed channels through a matrix to appropriate output ports.
13. 13. Method according to claim 12, characterized in that the first and the second format each comprise one of the following: at least a part of the North American hierarchy (asynchronous hierarchy), at least a part of the ITU digital hierarchy (plesiochronic digital hierarchy), and at least part of the Japanese hierarchy, where the first and second formats are not identical.
14. 14. - A method according to claim 12 or 13, characterized in that the first format is El and the second format is TI.
15. 15. - A method according to claim 12 or 13, characterized in that the first format is TI and the second format is El.
16. 16. - A method according to claim 12 characterized in that the step of demultiplexing the channels of the first format in individual voice channels it is followed by a conversion stage from law A to law μ.
17. 17. - A method according to any of claims 12-16, characterized in that the step of demultiplexing the channels of the first format in the individual voice channels is followed by a conversion step of the law μ to the law A.
18. 18. - A method for performing logical layer functions in the switching system for a telecommunications network, characterized in that it consists of: receiving signals from a plurality of I / O ports, the signals arranged in multiplexed channels; providing a plurality of interconnections to switch the signals between the I / O ports by means of the switching matrix; and providing a server operatively associated with the switching matrix to receive an arranged signal in the multiplexed format and perform the functions of the logical layer in the multiplexed channel, and to transmit the converted signal to the switching matrix for the eventual output.
19. 19. - A method according to claim 18 and wherein the logical layer function includes at least one installation data link in the extended superframe format DSl.