MXPA00000982A - Apparatus and method for modulation/demodulation with consecutive minimum runlength limitation - Google Patents

Abstract

Problem:how to record and play back data at a high line density. Means for solving the problem:a DSV control bit determining/inserting unit (11) inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit (12). The modulation unit (12) converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit (13). The conversion table used by the modulation unit (12) includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit. In addition, the conversion table enforces a conversion rule, according to which the remainder of division of the"1"count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of the"1"count of an element in the code resulting from conversion of the data string by 2.

Description

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APPARATUS AND METHOD FOR MODULATION / DEMODULATION WITH LIMITATION OF LENGTH OF MINIMUM CONSECUTIVE CYCLE DETAILED DESCRIPTION OF THE INVENTION Technical field of the invention. In general, the present invention relates to a modulation apparatus and a modulation method, to a demodulation apparatus and a demodulation method, as well as to a medium having a program. More particularly, the present invention relates to a preferred modulation apparatus and a preferred modulation method, a preferred demodulation apparatus and a preferred demodulation method, as well as a medium having a preferred program used in operations for recording data. on a recording medium at a high recording density and reproducing data recorded in a recording medium at a high recording density.

PREVIOUS TECHNIQUE When data are transmitted through a registered transmission line on a recording medium such as a magnetic disk, an optical disc or a magneto-optical disc, the data are modulated in a code corresponding to the transmission line or to the medium registration before transmission or registration. As a modulation technique, block coding is known. In block coding, an ordered sequence of data is put into blocks in units, each of which comprises m x i bits. Each of the units which will be referred to later as a data word is then converted into a code word comprising n x i bits in accordance with an appropriate coding rule. For i = l, this code word is a fixed length code. In the case that i has a plurality of values each selected from the range of 1 to imax, a maximum of i, the resulting codeword is a variable length code. In general, a code resulting from block coding is expressed as a variable length code (d, k; m, n; r). Here, i is known as the restriction length and r is imax, a maximum restriction length, d is the minimum number of 0 that appear between two consecutive 1s. d is known as the minimum cycle of 0. On the other hand, k is the maximum number of 0 that appear between two consecutive 1s. k is known as a maximum cycle of 0. Incidentally, in an operation to register the variable length code obtained from the block coding described above on a recording medium such as an optical disk or a magneto-optical disk, for example, or a compact disc (CD) or a minidisk (MD), the variable length code undergoes a modulation NRZl (No Return to. Inverted) where each "1" of the variable length code is interpreted as an inversion while "0" it is interpreted as an absence of investment. The variable length code that completes the NRZl modulation is then registered. The variable length code that completes the NRZl modulation is known as the record wave train. In the case of a magneto-optical disc conforming to the first ISO specifications that prescribe a not-so-large recording density, a bit stream that completes the record modulation is recorded as if it had not experienced the NRZI modulation. Let the notations Tmin and Tmax denote the minimum and maximum investment periods of a register wave train respectively. In this case, in order to register the record wave train at a high register density in the direction of the linear velocity, a long minimum inversion period or a large minimum cycle d is preferred. Furthermore, from the point of view of generating the clock, it is desirable to have a short maximum inversion period T max or a small maximum cycle k. To satisfy these requirements, a variety of modulation techniques have been proposed. To put this concretely, for an optical disc, a magnetic disk or a magneto-optical disc, there are proposals or modulation techniques are currently used to generate a variable length code RLL (1-7), which is also expressed as ( 1-7; m, n; r) and a variable length code RLL (2-7) also expressed as (2-7 m, n; • r) as well as a fixed length code RLL (1-7) also expressed as (1-7;, n; 1) used in an ISO MO specification. As for a disk apparatus currently under investigation and development, such as an optical disk and a magneto-optical disk having a high recording density, A RLL (Limited Cycle Length Code) code is commonly used with a minimum cycle d of 1. The following is an example of a conversion table of the variable length RLL code (1-7). < Table 1 > RLL (1, 7; 2, 3; 2 The symbol x used in the Conversion Table has the value of "1" for the next tracking channel bit of "0" or has a value of "OO" for a following tracking channel bit "1". The restriction length ^ 5 maximum r is 2. The parameters of the variable length code RLL (1-7) are (1,7; 2, 3; 2). The minimum investment period Tmin that can be expressed (d + 1) T is thus equal to 2 (= 1 + 1) T where T is a one-bit space in the wave train registration. The minimum investment period Tmin that can also be expressed by (m / n) x2 Data is thus equal to 1.33 (= 2 / 3x2) data, where Data is the space of a bit in the ordered sequence of data. The maximum investment period Tmax that can be expressed by (k + l) T is equal to (7 + 1) T = 8T = 8x (m / n) Data = 8x2 / 3 Data = 5.33 Data. The width of the detection window Tw which can also be expressed by (m / n) Data is thus equal to 0.67 (= 2/3) Data. By the way, in a channel bit stream that completes the RLL modulation (1-7) shown in Table 1, a generation frequency corresponding to a period of 2T that is equal to the minimum inversion period Tmin is observed very frequently followed by generation frequencies corresponding to periods of 3T and 4T. The fact that it is generated A lot of information in the margin at short intervals, such as 2T and 3T, is advantageous for the generation of a clock signal in many cases. As the density of the registration line increases even more, however, the minimum cycle time • 5 becomes an adverse problem. That is to say that if 2T minimum cycles are consecutively generated, the record wave train is prone to generate distortions in it. This is because a 2T wave output is smaller than another wave output and, consequently, is easily affected for factors such as blurring and tangential inclination. In addition, at a high line density, the registration of consecutive minimum marks (2T) is also easily affected by disturbances such as noise. In this way, an operation to reproduce the data will also be prone to to errors. In this case, a pattern of errors in the reproduction of the data is observed as deviations of the front and back edges of a minimum mark in many cases. As a result, the error length of the generated bit is increased. As described above, when the data is transmitted through a transmission line or registered on a recording medium, the data is modulated in the code corresponding to the transmission line or the recording medium before transmission or record. If the code resulting from the modulation contains a direct current component, a variety of error signals such as tracking errors in the control of a servomechanism of the disk drive becomes prone to variations or fluctuations are easily generated. For this • 5 reason, it is desirable to make as much effort as possible to prevent the modulated code from containing a direct current component. To prevent the modulated code from containing a direct current component, control has been proposed of a DSV (Digital Sum Value) to prevent the modulated code from containing a direct current component. The DSV is a total found by adding the values of a bit stream (data symbols), where the values of +1 and -1 are assigned to "1" and "0" in the train respectively, which results from the NRZl modulation (i.e., level coding) of a channel bit stream. The DSV is an indicator of a direct current component contained in a code train. Lowering the absolute value of the DSV by controlling the DSV is equivalent to suppressing the magnitude of a component of direct current contained in a train of codes. The DSV control is not applied to a modulation code generated in accordance with the variable length (1 - 7) RLL table shown in Table 1 given above. The control of the DSV in such case is achieved calculating a DSV of an encoded bitstream (a channel bitstream) after modulation for a predetermined period of time and inserting a predetermined number of DSV control bits into the coded bit stream (the bit stream) channel) . • 5 At any speed, the control bits of the DSV are basically redundant bits. If the efficiency of code conversion is taken into consideration, it is thus desirable to reduce the number of control bits of the DSV to as small a value as possible. In addition, if the control bits of the DSV are inserted, it is also desirable to make the minimum cycle d and maximum cycle k not change. This is because a change in (d, k) over the registration / reproduction characteristics will take effect. 15 PROBLEMS TO BE RESOLVED BY THE INVENTION As described above, in an operation to register the RLL code at a high line density or an operation to execute the RLL code registered at a high line density, the problem arises that a pattern of consecutive minimum cycles d will cause a large error to be easily generated. In addition, in the case of the RLL code such as the RLL code (1 - 7), the DSV control needs the insertion of the control bits of the DSV in an arbitrary part of an ordered sequence of code words (a channel bit stream). Since the control bits of the DSV are basically redundant bits, however, it is necessary to reduce the number of control bits of the inserted DSV to as small a value as possible. To maintain the minimum cycle and the maximum cycle at constant values, however, the number of control bits DSV is at least 2. In this way, it is desirable to reduce the number of DSV control bits to an even smaller value. The present invention solves the problems described above. An object of the present invention is to allow the DSV control to be executed to produce high efficiency control bits over the RLL code of (d, k; m, n) where the minimum cycle d = 1, ie the code RLL of (1, 7; 2, 3) so that the number of consecutive minimum trials is reduced while the minimum cycle and the maximum cycle are maintained. Another object of the present invention is to prevent the propagation of a scaling demodulation error using a conversion table having as simple a configuration as possible.

MEANS FOR RESOLVING PROBLEMS A modulation apparatus according to claim 1 is characterized by including a conversion step for converting input data into code according to a conversion table, where the conversion table complies with a conversion rule, of according to which the remainder of the division of a count of "1" of an element into an ordered sequence of data by 2 that has a value of 0 or 1 will always equal the remainder of the division of a count of "1" of an element in the ordered sequence of code words resulting from the conversion of the ordered sequence of data by 2 and the conversion codes of the conversion table comprise: basic codes for d = 1, k = 7, m = 2 and n = 3 where d is a minimum cycle and k is a limit of the length of the cycle; first substitution codes to limit the number of consecutive occurrences of the minimum cycle d; and second substitution codes to maintain the limit of the length of the cycle k. A modulation method according to claim 23 is characterized by including a conversion step for converting input data into code according to a conversion table, where the conversion table complies with a conversion rule, according to which the The remainder of the division of a count of "1" of an element into an ordered sequence of data by 2 that has a value of 0 or 1 will always equal the remainder of the division of a count of "1" of an element in the ordered sequence of code words resulting from the conversion of the ordered sequence of data by 2 and the conversion codes of the conversion table comprise: basic codes for d = l, k = 7, m = 2 and n = 3 where d is a minimum cycle and k is a limit of the length of the cycle; first substitution codes to limit the number of consecutive occurrences of the minimum cycle d; and second substitution codes to maintain the limit of the length of the cycle k. A means presenting a program according to claim 24 for presenting a program implementing the processing includes a conversion step for converting input data into code according to the data of a conversion table in a modulation apparatus for converting data. with a basic data length of m bits in variable length code (d, k; m, n; r) with a basic code length of n bits is characterized in that the conversion table complies with a conversion rule, according to which the remainder of the division of a count of "1" of an element into an ordered sequence of data by 2 that has a value of 0 or 1 will always equal the remainder of the division of a count of "1" of an element in the ordered sequence of code words resulting from the conversion of the ordered sequence of data by 2 and the conversion codes of the conversion table comprise : basic codes for d = l, k = 7, m = 2 and n = 3 where d is a minimum cycle and k is a limit of the length of the cycle; first substitution codes to limit the number of consecutive occurrences of the minimum cycle d; and second substitution codes to maintain the limit of the length of the cycle k. A demodulation apparatus according to claim 25 is characterized by having conversion means for converting the input code into data according to a conversion table, where the conversion table complies with a conversion rule, according to which the The remainder of the division of a count of "1" of an element into an ordered sequence of data by 2 that has a value of 0 or 1 will always equal the remainder of the division of a count of "1" of an element in the ordered sequence of code words resulting from the conversion of the ordered sequence of data by 2 and the conversion codes of the conversion table comprise: basic codes for d = l, k = 7, m = 2 and n = 3 where d is a minimum cycle and k is a limit of the length of the cycle; first substitution codes to limit the number of consecutive occurrences of the minimum cycle d; and second substitution codes to maintain the limit of the length of the cycle k. A demodulation method according to claim 28 is characterized by having a conversion step for converting the input code to data according to a conversion table, where the conversion table complies with a conversion rule, according to which the remainder of the division of a count of "1" of an element into an ordered sequence of data by 2 that has a value of 0 or 1 will always equal the remainder of the division of a count of "1" of an element in the ordered sequence of code words resulting from the conversion of the ordered sequence of data by 2 and the conversion codes of the conversion table comprise: basic codes for d = l, k = 7, m = 2 and n = 3 where d it is a minimum cycle and k is a limit of the length of the cycle; first substitution codes to limit the number of consecutive occurrences of the minimum cycle d; and second substitution codes to maintain the limit of the length of the cycle k. A means presenting a program according to claim 29 for presenting a program including a conversion step for converting the input code into data according to a conversion table in a demodulation apparatus for converting the variable length code ( d, k; m, n; r) with a basic code length of n bits in data with a basic data length of n bits is characterized in that the conversion table complies with a conversion rule, according to which the residue of the division of a count of "1" of an element into an ordered sequence of data by 2 that has a value of 0 or 1 will always equal the remainder of the division of a count of? l "of an element in the sequence order of code words resulting from the conversion of the ordered sequence of data by 2 and the conversion codes of the conversion table comprise: basic codes for d = l, k = 7, m = 2 and n = 3 where d is a minimum cycle and k is a limit of the length of the cycle; first substitution codes to limit the number of consecutive occurrences of the minimum cycle d; and second substitution codes to maintain the limit of the length of the cycle k. According to the modulation apparatus claimed in claim 1, the method of modulation claimed in claim 23, the means presenting a claimed program as claim 24, the demodulation apparatus claimed as claim 25., the demodulation method claimed as claim 28 and the medium presenting the claimed program as claim 29, the conversion process is carried out on the basis of a conversion table that fulfills a conversion rule, according to the which the remainder of the division of a count of "1" of an element into an ordered sequence of data by 2 that has a value of 0 or 1 will always equal the remainder of the division of a count of "1" of an element in the ordered sequence of code words resulting from the conversion of the ordered sequence of data by 2 and the conversion codes of the conversion table comprise: basic codes for d = l, k = 7, m = 2 and n = 3; first substitution codes to limit the number of consecutive occurrences of the minimum cycle d; and second substitution codes to maintain the cycle length limit.

DETAILED DESCRIPTION OF THE PREFERRED MODALITIES Before beginning the explanation of some preferred embodiments of the present invention, to clarify the relations that associate the means of the present invention described in the claims with the implementations adopted in the modalities, in the following description that characterizes the invention, each of the means is followed by a typical implementation enclosed in parentheses in the form of "means (implemented for example by means of a typical implementation)". It is not necessary to say, however, that the typical implementation does not intend to be constituted in a sense • 5 limiting. That is, the media is not necessarily limited to a typical implementation associated with the media. A modulation apparatus according to claim 1 is characterized by having conversion means (implemented for example, by a unit of modulation shown in Figure 12) to convert data from • code entry according to a conversion table (implemented for example in Table 2) where the conversion table complies with a conversion rule, according to which the remainder of the division of a count of "1" of a element in an ordered sequence of data by 2 that has a value of 0 or 1 will always equal the remainder of the division of a count of "1" of an element in the ordered sequence of code words resulting from the conversion of the ordered sequence of data by 2 and the codes of Conversion table conversion comprises: basic codes for d = l, k = 7, m = 2 and n = 3 where d is a minimum cycle and k is a limit of the length of the cycle; first substitution codes to limit the number of consecutive occurrences of the minimum cycle d; and second substitution codes to maintain the limit of the length of the cycle k. According to claim 10, the claimed modulation apparatus as claimed in claim 10 is further characterized by having synchronization signal insertion means (implemented for example by means of a synchronization signal insertion unit 212 shown in the Figure 9) to insert a synchronization signal that includes a unique pattern not included in the conversion codes of the conversion table at any arbitrary position in the ordered sequence of code words. According to claim 21, the modulation apparatus claimed as claim 1 is further characterized by having control means of the DSV (implemented for example by a terminating / inserting unit of the control bit of the DSN 11 shown in Figure 11). ) to control the DSVs of the input data and supply the DSVs to the conversion media. According to claim 22, the modulation apparatus claimed as claim 1 is further characterized in that the conversion means comprise: first code detection means (implemented for example by a consecutive minimum sequence limiting code detection unit 33 shown in Figure 3), for detecting the first li codes substitution to limit the number of consecutive occurrences in the minimum cycle d; and second means of code detection (implemented for example by means of code detection ^ JP 5 to ensure a maximum cycle 34 shown in Figure 3) to detect the second substitution codes to maintain the limit of the length of the cycle. A demodulation apparatus according to claim 25 is characterized by having means of conversion (implemented, for example, by a unit of • demodulation 111 shown in Figure 5) to convert the input code into data according to a conversion table, where the conversion table (implemented for example in Table 2) complies with a conversion rule, of according to which the remainder of the division of a count of "1" of an element into an ordered sequence of data by 2 that has a value of 0 or 1 will always be equal to • residual of the division of a count of "1" of an element in the ordered sequence of resulting code words of the conversion of the ordered sequence of data by 2 and the conversion codes of the conversion table comprise: basic codes for d = l, k = 7, m = 2 and n = 3 where d is a minimum cycle and k is a limit of the length of the cycle; first substitution codes to limit the number of consecutive occurrences of the minimum cycle d; and second substitution codes to maintain the limit of the length of the cycle k. According to claim 26, a claimed demodulation apparatus like claim 25 is further characterized by having bit removal means (implemented for example by a DSV control bit removal unit of the unit 112 shown in FIG. Figure 5) to remove redundant bits inserted at predetermined intervals in the code. Preferred embodiments of the present invention are described as follows. To make the explanation easier to understand, in the following description, an array of "0" and "1" bits of data before conversion, ie, an ordered sequence of data prior to conversion, is represented as a train of bits inserted in parentheses () as for example (000011). On the other hand, an array of bits "0" and "1" of a code resulting from the conversion, that is, an ordered sequence of words of the sequence ordered after conversion is represented as a stream of bits delimited by a pair of symbols "as for example" 000100100. "Tables 2 and 3 given below are examples of a conversion table for converting data into a code according to the present invention, < Table 2 > 17PP.RML. 32 Data Code 11 * or * 10 001 01 010 0011 010 100 0010 010 000 0001 000 100 000011 000 100 100 000010 000 100 000 000001 010 100 100 000000 010 100 000"110111 001 000 000 (below 010) 000010Q0 000 100 100 100 00000000 010 100 100 100 if xxl then * 0 * = 000 xxO then * 0 * = 101 synchronization and Termination # 01 000 000 001 (12 bit channels) # 01 001 000 000 001 000 000 Q01 (24 bit channels) # = 0: Unfinished case # = 1: Case completed Termination Table 10 00 000 • 0000 010 100"110111 001 000 000 (below 010) When the next bits of the channel are" 010"15 convert" 11 01 11"to" 0Q1 000 000"after using the main table and the termination table. Table 2, the ff conversion table shows the codes resulting from the conversion including the basic codes, substitution codes and termination codes. The conversion process may not be carried out without a basic code. In the conversion table, the basic codes are the codes resulting from the conversion of the ordered sequence of data (11) to (000000). The conversion process can be carried out even if not there is a substitution code. If a replacement code exists, however, a more effective conversion process can be carried out. In the conversion table, the substitution codes are the codes resulting from the conversion of the ordered sequences of data (110111), • 5 (00001000) and (00000000). The termination code is used to terminate the code resulting from the conversion at any arbitrary position. The termination codes in the table are the codes resulting from the conversion of the ordered data sequences (00) and (0000). In addition, the table conversion also perceives the signals of • synchronization. In Table 2, the minimum cycle d is 1, while the maximum cycle k is 7. One of the elements of the basic codes includes an indeterminate code, that is, a code indicated by the asterisk symbol "*". It can be determined that the bit represented by the symbol "*" of the indeterminate code is "0" or "1", in order to keep the values of the minimum cycle and the maximum cycle k regardless of an immediately preceding or successive ordered sequence of words of code. To put this in detail, if the ordered sequence of 2-bit data to be converted is (11), a code resulting from the conversion may be "000" or "101" depending on the ordered sequence of immediately preceding code words. To be more specific, if the The only channel bit of the ordered sequence of immediately preceding code words "1", the ordered 2-bit data sequence (11) converted to the code "000" to preserve the minimum cycle d. If the only channel bit of the ordered sequence of immediately preceding code words is "0", on the other hand, the ordered sequence of 2-bit data (11) is converted into the code "101" to preserve the maximum cycle k . The basic codes shown in the conversion table of Table 2 have a variable length structure. The number of basic codes with a bit restriction length of 1 is 3, a value which is smaller than the required number of 4 (= 2Am = 2? 2). Those basic codes are "_ * 0 *", "001" and "010". As a result, in an operation to convert an ordered sequence of data, there is an ordered sequence of data, which can not be converted only with a constraint length of 1. For this reason, it is necessary to refer to basic codes with a constant length i of up to 3 in Table 2 in an operation to convert all ordered sequences of data. That is, the basic codes with a restriction length i of up to 3 are included in Table 2 to allow Table 2 to serve as a sufficient conversion table. In addition, in the conversion table of Table 2 also includes substitution codes to limit the consecutive occurrences of the minimum cycle d. If the ordered sequence of data is (110111) and an ordered sequence of code words after a code resulting from the conversion of the data number sequence is "010", the ordered sequence of data is converted into a code word of "010 000 000". If the code words after a code resulting from the conversion of the ordered sequence of data are different from "010", on the other hand, the ordered sequence of data (110111) is converted into 2-bit units. To put it in detail, the ordered 2-bit sequences (11), (01) and (11) in the ordered sequence of data are converted into an ordered sequence of code words "* 0 * 010 and * 0 *". As a result, consecutive occurrences of the minimum cycle d in the ordered sequence of code words resulting from the conversion of the ordered sequence of data can be restricted, limiting the number of repeated minimum cycles to a maximum of 6. In addition, the conversion table of Table 2 fulfills a conversion rule, according to which the residue of the division of the control "1" of an element in an ordered sequence of data by 2 that has a value of 0 to 1 will always be equal to the residue of the division of the 1,111 count of an element into the ordered sequence of code words resulting from the conversion of the ordered sequence of data by 2. That is, if the count of "1" of an element in the ordered sequence of data is even, the count of "1" of an element in the ordered sequence of code words is also even and, if the count of "1" of an element in the ordered sequence of data is odd, on the other hand, the count of "1" of an element in the ordered sequence of code words is also odd. For example, an ordered sequence of data of (000001) is converted into an ordered sequence of code words of "010 100 000". In this case, the remainder of the division of the count of "1" of a • element in the ordered sequence of data by 2 is one that is equal to the remainder of the division of the count of "1" of an element in the ordered sequence of data of the code words resulting from the conversion of the ordered sequence of data by 2. That is, the counts of "1" of the ordered sequence of data and the ordered sequence of codewords are both odd. As another example, a • ordered sequence of data (000000) is converted to an ordered sequence of code words of "010 100 100". In In this case, the remainder of the division of the count of "1" of an element in the ordered sequence of data by 2 is 0, which is equal to the remainder of the division of the count of "1" of an element in the sequence order of code words resulting from the conversion of the ordered sequence of data by 2. That is, the counts of "1" of the ordered sequence of data and the ordered sequence of code words are both pairs. In addition, the maximum restriction length r in the conversion table of Table 2 is 4. The codes in the • 5 table with a restriction length i of 4 are substitution codes to implement the value 7 of the maximum cycle k. Such a substitution code is known as the maximum cycle assurance code. That is, an ordered sequence of data from (0000100) is converted into a ordered sequence of code words of "000 100 100 • 100"while an ordered sequence of data from (00000000) is converted into an ordered sequence of code words of "010 100 100 100". It should be noted, that in this case, the value of the minimum cycle d is maintained in 1 too. If the conversion table in Table 2 does not include substitution codes, which have a length of • restriction i of 4, the maximum restriction length r for the table is 3, causing a code to be generated with a maximum cycle k of 8. Since the table includes basic codes with a restriction length i of, however, a code can be generated with a maximum cycle k of 7. In general, the greater the maximum cycle k, the greater the inconvenience of the generation of a clock signal and, of es1: e mode, poorer stability of the system. Thus, by reducing the value of the maximum cycle k from 8 to 7, the characteristic of the system can be improved commensurately with the reduction in the maximum cycle k. That is, if the conversion table in Table 2 is created to include basic codes only, the maximum restriction length r for such a table is 3. In this case, it is possible to generate codes that have a minimum cycle d of 1 and a maximum cycle k of 8. In addition, the remainder of the division of the count "1" of an element in an ordered sequence of data by 2 that has a value of 0 or 1 will always be equal to the remainder of the division of the count "1"of an element in the ordered sequence of code words resulting from the conversion of the ordered sequence of data by 2. If the conversion table is created to include substitution codes limiting the consecutive occurrences of the minimum cycle d in addition to the basic codes , the maximum restriction length r for such a table is also 3. In this case, however, it is possible to generate a code that has a minimum cycle d of 1 and a maximum cycle k of 8, while the number of minimum cycles consecutive d is limited to a value of a higher limit. In addition, the remainder of the division of the count "1" of an element of an ordered sequence of data by 2 having a value of 0 or 1 will always be equal to the remainder of the division of the count "1" of an element in the sequence ordered code words resulting from the conversion of the ordered sequence of data by 2. If the conversion table is created to also include substitution codes to ensure a maximum cycle k • 5 out of 7, in addition to the substitution codes to limit the consecutive occurrences of the minimum cycle in the basic codes, the maximum restriction length r for such a table is 4. In this case, it is possible to generate a code that has a maximum cycle d of 1 and a maximum cycle k of 7, while the number of consecutive minimum cycles d is limited to a higher limit value. In addition, the remainder of the division of the count "1" of an element in an ordered sequence of data by 2 that has a value of 0 or 1 will always be equal to the remainder of the division of the count "1" of an element in the sequence neat code words resulting from the conversion of the ordered sequence of data by 2. In general, however, the greater the maximum restriction length r, the poorer the propagation characteristic of a modulation error generated in the case of a deviation of bits, that is, an error which is generated due to a bit of the limit deviating towards a forward or backward direction from its normal position in a bit. The comparison of Table 1 with Table 2 shows that the maximum restriction length r of the first is 2 while that of the second is 4. Thus, Table 2 will result in poorer characteristics than table 1. However, the results of the simulation that they will be described later referring to Table 7, they indicate that the characteristics of Table 2 are not so poor compared to Table 1. For example, as shown in Table 7, the average bit error rate of Table 1 is 1,014 bits, while Table 2 is 1.67 bits, a value which is much higher than that of Table 1. The difference in the average bit error rate can be considered to be attributable to the fact that the number of groups of conversion codes in Table 1 is less than that of Table 2 by a difference of 2. By the way, for a case in which a synchronization signal is inserted at any arbitrary position in a sequence ordered code words ( that is, a channel bit stream) generated as a result of the conversion carried out according to a Conversion Table of Table 2, the conversion table produces a code with a variable length structure. This is because the conversion table includes a termination table that prescribes completion codes to terminate the code resulting from the conversion at any arbitrary position. A termination code is used where necessary. Assume, for example, that a synchronization signal is inserted at a particular position in the code resulting from the conversion. In this case, first of all, at a junction point in an ordered sequence of code words immediately preceding the particular position and • 5 an ordered sequence of code words immediately after the particular apposition, the binding bits are placed while maintaining the minimum cycle d and the maximum cycle k and a unique pattern representing the synchronization signal to be placed between the binding bits .

Consider a pattern of the synchronization signal that breaks the value of 7 of the maximum cycle k. In this case, the pattern of a synchronization signal with a minimum length is a 12-bit code word (ie, 12 channel bits) given as follows: 15"# 01 000 000 001" The "#" symbol in the header in the pattern of the synchronization signal is a binding bit, which may be "0" or "1" as described below. The second channel bit after the "#" bit is "0" to keep the cycle min. D. The third channel bit and the subsequent bits are set in values which form a unique pattern 9T, a code pattern not prescribed in Table 2 to give a maximum cycle k of 8. As shown by the previous pattern, the third channel bit and the last bit of channel sandwich 8 bits "0" consecutive. It should be noted that, although the last bit of channel in the pattern of the synchronization signal was set to? 1", using the conversion table of Table 2, the minimum cycle d can be retained. of termination and the join bit "#" in the bit pattern of the synchronization signal As shown in Table 2, the termination table is constructed as follows: 00 000 0000 010 100 The completion table is required for basic codes with a restriction length i that provides a number of pairs, each of which comprises an ordered sequence of data and an ordered sequence of codewords less than the required number 4 (= 2? m = 2? 2) To put it in detail, in the case of Table 2, for the Restriction length i = 1, since the number of pairs each comprises an ordered sequence of data and an ordered sequence of code words 3, the termination table is required. For the restriction length i = 2, since the number of pairs each comprises an ordered sequence of data and an ordered sequence of code words is also 3, the termination table is required. For the restriction length i = 3, the number of pairs each comprising an ordered sequence of data and an ordered sequence of code words is 5, including a pair having a substitution code. The rest of the four pairs each include a basic code. Since the required number of 4 is satisfied, the table • 5 termination is not necessary. For the restriction length i = 4, since the ordered sequences of code words are all substitution codes, it is not necessary to take a termination code into consideration. In this way, the termination table is required for the restriction length i = 1, where a completion code is used for an ordered sequence of data from (00). For the same reason, the termination table for the constraint length i = 2 is required, where a termination code is used for an ordered sequence of data of (0000).

According to the termination table, the ordered data sequences (00) and (0000) are converted into ordered sequences of code words "000" and "010100" respectively. As a result, in an operation to insert a synchronization signal, it is possible to avoid a situation in which the data preceding the pattern of the synchronization signal can no longer be converted. That is to say, that the conversion system is capable of eliminating a situation in which it is no longer possible to leave the code immediately preceding the synchronization signal that serves as a termination.

The "#" bit of the synchronization signal pattern is used to distinguish a use case from the termination table of a case, in which the termination table is not used. To be more specific, the first channel bit "#" is the header of the synchronization signal pattern set to "1" to indicate that the completion code was used or is set to "0" to indicate that it is not He used the termination. By doing this, it is possible to determine correctly whether or not the termination table was used, that is, whether the termination code was used or not. As described above, the pattern of a synchronization signal with a minimum length is a 12-bit code word (ie, 12 channel bits). Since the pattern of the synchronization signal that breaks the value of 7 of the maximum cycle k but provides a maximum cycle k of 8 (9T) is acceptable, any other pattern of synchronization signals that forms a codeword of minus 12 bits. In the case of the formation of a 15-bit codeword, for example, the following two synchronization signals may be produced: "# 01 000 000 001 010 '" # 01 000 000 001 001' In the case of the formation of a 21-bit code word, the following synchronization signal may occur: "# 01 000 000 001 000 000 001"5 The above 21-bit synchronization signals include 2 consecutive patterns, each of which provides a maximum cycle k of 8 (9T). Such synchronization signal can be detected with a higher degree of reliability. Then, in the case of the formation of a 24-bit codeword, the following may occur • synchronization signal: "# 01 001 000 000 001 000 000 001" The above synchronization signal, a pattern that has the shape of "3T - 9T - 9T", reduces the probability of 15 appearing a long cycle (T) before and / or after the two consecutive patterns, each of which provides a maximum cycle k of 8 (9T) as well as increases in power • detection. It is possible to select which detection power should provide a synchronization signal according to the requirements of the system. Table 3 is another typical conversion table provided by the present invention < Table 3 > 25 17PP.RML.52 i = 1 Main Table: Data Code 00 101 01 100 10 001 11 000 i = 2 Substitution Table A (Limits from d to 1) 0000 100 010 0001 101 010 1000 000 010 1001 001 010 i = 3 Substitution Table B (Limits from k to 8) lililí 000 010 010 111110 001 010 010 011110 010 010 010 011111 100 010 010 i = 4 Substitution Table C (Limits RMTR a 6) 00010001 100 010 010 Q10 can-0 10010001 100 000 010 010 can-1 10010001 000 010 010 010 r = 4 Substitution Table D (Limits ka 1] can 010 11100000 000 001 010 010 can 010 11100010 100 001 010 010 can 010 11100001 001 010 010 010 can 010 11100011 101 010 010 010 Syn data: xl Ox can .: xxO 100 000 000 lOx (12 channel bits) data: xl Ox 10 can .: xxO 100 000 000 100 000 000 lOx (24 channel bits) • Termination: adding data bits? 01 'u ll' at the beginning, and? 00 'or? 01' at the end 15 The conversion table in Table 3 has a structure where, for the minimum cycle d = 1, the maximum cycle • k = 7, and at constraint length i = 1, 1 = 1, 4 (= 2Am = 2? 2) basic codes are provided. That is, for the restriction length i = 1, the 4 basic codes are placed in the main table. For the restriction length 1 = 2, or greater, substitution code tables are provided to limit parameters such as the minimum cycle d and the maximum cycle k. To be more specific, the Table A for the restriction length i = 2 prescribes substitute codes to eliminate the minimum cycle of 1. Table B for the restriction length 1 = 3 prescribes substitute codes to limit the maximum cycle of ka to an upper limit of 8. The Table C for the restriction length i = 4 prescribes substitute codes to limit the consecutive occurrences of the minimum cycle d that has the value of 1. Table D for the restriction length 1 = 4 prescribes substitute codes to limit the maximum cycle of ka an upper limit of 7. Thus, in the conversion table of Table 3, the maximum restriction limit is r = 4. As described above, the conversion table in Table 3 includes substitution codes to limit the consecutive appearances of the minimum cycle d. For example, an ordered sequence of data of (0001001) is converted into an ordered sequence of code words of "100 010 010 010". As for an ordered data sequence of (10010001), reference is made to an immediately preceding code word to determine whether the immediately preceding channel bit is "0" or "1". If the immediately preceding channel bit is "011," the ordered sequence of data is converted into an ordered sequence of code words "100 000 010 010." If the immediately preceding channel bit is "1", on the other hand, the ordered sequence of data is converted into an ordered sequence of code words "000 010 010 010". As a result, the ordered sequence of code words resulting from the data conversion has a number of consecutively repeated minimum cycles limited to a maximum of 6. In addition, the conversion table in Table 3 complies with a conversion rule, in accordance to which the remainder of the division of the division count "1" of an element in an ordered sequence of data by 2 having a value of 0 or 1 will always be equal to the remainder of the division of the count of "1" of an element in the ordered sequence of words of • code resulting from the conversion of the ordered sequence of data by 2. That is, if the count of "1" of an element in the ordered sequence of data is even, the count of "1" of an element in the ordered sequence of code words is also pair, and, if the count of "1" of an element in the ordered sequence of data is odd, on the other hand, the count of "1" of an element in the ordered sequence of • Code words are also odd. For example, an ordered sequence of (1000) data is converted into a ordered sequence of code words of "000 010". In this case, the remainder of the division of the count of "1" of an element in the ordered sequence of data by 2 is 1, which is equal to the remainder of the division of the count of "1" of an element in the sequence ordered code words resulting from the conversion of the ordered sequence of data by 2. That is, the counts of "1" of the ordered sequence of data of the ordered sequence of code words are both odd. As another example, an ordered data sequence of (Lilili) is converted into an ordered sequence of code words of "000 010 010". In this case, the remainder of the division of the count of "1" of an element in the ordered sequence of data by 2 is 0, which is equal to the remainder of the division of the count of "1" of an ordered sequence element of code words resulting from the conversion of the ordered sequence of data by 2. That is, the counts of "1" of the ordered sequence of data and the ordered sequence of codewords are both pairs. In addition, the codes in the conversion table of Table 3 with a restriction length i of 4 equal to the maximum restriction length r are the substitution codes to increase the value of 7 of the maximum cycle k. In the case of the conversion using a substitution code, reference is made to an ordered sequence of immediately preceding code words. To be more specific, if the ordered sequence of code words immediately preceding is "010", the conversion is implemented. If the ordered sequence of data is (11100000) and the ordering sequence of code words immediately preceding is "010", for example, the conversion is implemented to result in an ordered sequence of code words of "000 001 010 010" As another example, if the ordered sequence of data is (11100010) and the sequence • 5 ordered from immediately preceding code words is "010", the ordered sequence of data is converted into an ordered sequence of code words of "100 001 010 010". The conversion table of Table 3 given above can not be built from codes • Basic only to implement RLL coding. The RLL code with a guaranteed minimum cycle d and a maximum assured cycle k can be produced using basic codes in the main table, as well as codes of substitution in Table A for a restriction length i of 2 and Table B for a restriction length i of 3. In this case, the restriction length • maximum r is 3 and it is possible to generate a code that has a minimum cycle d of 1 and a maximum cycle k of 8. In addition, the The remainder of the division of the count "1" of an element in an ordered sequence of data by 2 that has a value of 0 or 1 will always be equal to the remainder of the division of the count of "1" of an element of the ordered sequence of code words resulting from the conversion of the ordered sequence data by 2.

If Table C that prescribes substitution codes to limit the consecutive occurrences of the minimum cycle d is included in the configuration of the conversion table in Table 3, in addition to the main table and Tables A and B, • 5 the maximum restriction length r is 4 and it is possible to generate a code that has a minimum cycle d of 1, a maximum cycle k of 8 and a limited number of consecutive occurrences of minimum cycles d. In addition, the remainder of the division of the count "1" of an element into an ordered sequence of data by 2 that has a value of 0 or 1 will always be • equal to the remainder of the counting division of "1" of an element in the ordered sequence of code words resulting from the conversion of the ordered sequence of data by 2. It should be noted, that in this case, not always it is necessary to refer to the ordered sequence of immediately preceding code words as is the case using Table C of Table 3. If Table D which prescribes substitution codes to ensure a maximum cycle k of 7 is included in the configuration of Table 3, in addition to the main table and Tables A and B and Table C which prescribes substitution codes to limit the consecutive occurrences of the minimum cycle d, the maximum restriction length r is 4 and is possible to generate a code that has a minimum cycle d of 1, a maximum cycle k of 7 and a limited number of consecutive occurrences of minimum cycles d. In addition, the remainder of the counting division of "1" of an element in an ordered sequence of data by 2 that has a value of 0 or 1 will always be • 5 equal to the remainder of the counting division "1" of an element of the ordered sequence of code words resulting from the conversion of the ordered sequence of data by 2. The completion table of Table 2 is not requires in the process to insert a signal of ^^ synchronization at a particular position in an ordered sequence of code words (or a channel bit stream) resulting from the conversion by using the conversion table in Table 3. This is because, according to the conversion table of Table 3, the code can be terminated at a restriction length of i. To make the insertion of a pattern of a • synchronization signal as a result of a code as efficient as possible, the pattern is determined as follow. The 3-bit code word immediately preceding a unique pattern (or an ordered sequence of code words) that serves as a synchronization signal and the 3-bit codeword immediately following the unique pattern are words of code resulting from the conversion according to Table 3.

The 3 bits of the code words immediately preceding and immediately following the unique pattern each have a format in which the data bits and the joining bits are mixed as follows. • First of all, the 3 bits of the immediately preceding codeword are determined as follows. A unit of m bit of a word of data is examined before the conversion where m = 2 is examined. The first bit of the unit 2 bits in the header of the data word before of the conversion is a bit of information while the • second bit has a value of "1" to indicate a synchronization signal. The 2-bit unit in the header of the data word is converted into a code word (channel bits) according to Table 3. To be specific, the m bits (2 bits) of the data word (xl) are converted into n bits (3 bits) of a code word "xxO". Next, the 3 bits of the code word immediately following are determined as follows. In the same way, a unit of m bits of a word of data before the conversion where m = 2 is examined. In this case, however, the first bit of the 2 bit unit in the header of the data word before conversion has a value of "0" to indicate a synchronization signal, while the second bit is a bit from information. The 2-bit unit in the header of the data word is converted into a code word (channel bits) according to Table 3. To be specific, the m bits (2 bits) of the data word (Ox ) are converted into n bits (3 bits) of a code word "lOx". When a unique pattern of the synchronization signal is set as a pattern that breaks the value of 7 of the maximum cycle k, a pattern of synchronization signals with a length as short as possible that includes the unique pattern codeword may be implemented. at least 12 bits (12 bits of channel) given as follows: • xx0 100 000 000 10x ' where the value of "x" is dependent on the table of conversion. The previous 15-bit code word includes 3 bits "x". 2 bits "x" are in the header of the code word while 1"x" is in the tail of the same. The 3 bits "x" represented by the 2-bit unit of a data word before conversion. The 12 remaining channel bits of the codeword are a redundant portion that actually represents the pattern of the synchronization signal. The third channel bit of the code word is set to "0" to preserve the minimum cycle d. As for the rest, starting with the fourth bit of channel, 9T is set as a pattern of synchronization signals to provide a maximum cycle k of 8. To put it in detail, 8"0" is consecutively arranged between "1" and "1". As described above, the unique pattern of a synchronization signal with a minimum length is a 12-bit codeword (i.e., 12 channel bits). Since a pattern of the synchronization signal that breaks the value 7 of the maximum cycle k but provides a maximum cycle k of 8 (9T) is acceptable, any other pattern of synchronization signals that forms a unique pattern code word of at least 12 bits. At • case of the formation of a 15-bit unique pattern code word, for example, the following synchronization signal may occur: "xxO 100 000 000 100 lOx" 15 In the case of the formation of a code word of 21 In the case of bits, the following synchronization signal may occur: "Xxxo 100 000 000 100 000 000 lox" The previous 21-bit synchronization signal comprises 2 consecutive patterns, each of which provides a maximum cycle k of 8 (9T). According to a synchronization signal, the detection power can be increased. It is possible to select which detection power should provide a synchronization signal of according to the requirements of the system.

Much like the conventional method, after the ordered sequence of data is converted using a conversion table, such as the one shown in Tables 2 or 3, the DSV control can be executed by adding the control bits of DSV at predetermined intervals to a channel bit stream resulting from the conversion. Making use of the relationship between the ordered sequence of data and the ordered sequence of code words resulting from the conversion based on Tables 2 and 3However, the DSV control can still be executed with a greater degree of efficiency. To put it in detail, there is immediately the conversion rule, so that the remainder of the division of the count "1" of an element in a sequence of data by 2 that has a value of 0 or 1 will always be equal to the remainder of the division of the count "1" of an element of an ordered sequence of code words resulting from the conversion of the ordered sequence of data by 2. Thus, the insertion of the control bits of the DSV having a value of "1" "to indicate the inversion and a value of" 0"to indicate the absence of investment in a channel bit stream is equivalent to the insertion of the DSV control bits having a value of" 1"to indicate the investment and a value of "0" to indicate the absence of investment in a stream of data bits.

Consider, for example, a case in which 3 bits (001) of data are converted according to Table 2. Let x be a control bit of the DSV after the 3 bits sandwiched in the data. In this case, the data, including the control bit of the DSV, is converted to (001-x) where x is the control bit of bit 1 that has the value of "0" or "1". For x = 0, the data that includes the control bit of the DSV are converted according to Table 2 as follows: Orderly Sequence of Data Orderly Sequence of Word • Code 0010 010 000 10 For x = l, on the other hand, the data that includes the control bit of the DSV is converted according to Table 2 as follows: Orderly Sequence of Data Orderly Sequence of Word • of Code 0011 010 100 By applying the level of coding through the NRZl modulation to the ordered sequence of code words resulting from the conversion using Table 2, the following ordered code sequences are uniformly coded.

Orderly Sequence Orderly Sequence Orderly Sequence of Coded Code Word Data 0010 010 000 011111 0011 010 100 011000 As shown in the above table, the last 3 bits of the first ordered sequence of encoded codes are inverted bits of the last 3 bits of the second ordered sequence of encoded codes. The above results imply that, by selecting (1) or (2) as a value of the DSV control bit, the DSV control can be executed within an ordered sequence of data. Next, consider the redundancy introduced by the DSV control. The execution of the DSV control by inserting 1 DSV control bit of 1 into an ordered sequence of data corresponds to the execution of the DSV control by inserting 1.5 bits of DSV control into a channel bit stream where the value of 1.5 is the reciprocal of the conversion rate of m / n = 2/3 of Tables 2 and 3. To execute the control of the DSV for the table of RLL (1-7) as shown in Table 1 , it is necessary to apply the control in a channel bit stream. In this case, at least 2 channel bits are required to maintain the minimum cycle d, making the relative redundancy high compared to the control of the DSV applied to an ordered sequence of data for Tables 2 and 3. In other words, in the system of the present, the execution of the DSV control in an ordered sequence of data, the # 5 DSV control efficiency can improve. Next, an embodiment implementing a modulation apparatus provided by the present invention is explained with reference to Figure 1. In this embodiment, an ordered sequence of data is converted into a variable length code (d, k; m, n; r) = (1, 7, 2, 3; • 4) using Table 2. As shown in Figure 1, the modulation apparatus 1 comprises a DSV control bit determination / insertion unit to determine if the value of the bit for DSV control is "1" or "0" and for inserting a control bit of the DSV in any arbitrary range into an ordered sequence of data supplied thereto, a modulation unit 12 for modulating an ordered sequence of data with the bits of the DSV inserted into it and a unit of NRZl coding 13 for converting the output of the modulation unit 12 into a register wave train. In addition, the modulation apparatus 1 also has a timing control unit 14 for generating timing signals and supplying the signals to a variety of components.

Figure 2 is an explanatory diagram used to describe the processing carried out by the control bit determination / insertion unit of the DSV 11. As shown in the Figure, the control bit values of the DSV are determined and the bits of DSV control are inserted in an ordered sequence of data in any arbitrary intervals. To insert a DSV control bit in a location between data pieces DATA1 and DATA2 of an ordered sequence of incoming data, for example, the control bit determination / insertion unit of the DSV 11 calculates a cumulative DSV for data up to. DATA1. The total DSV 'is calculated by executing the steps of: converting DATA1 into a channel bit stream; carrying out the NRZl modulation on the bit stream; assigning the value +1 to a level H (high) (1) and the value -1 to a level (low) L (r) of the result of the modulation NRZl; and add the values assigned to the levels of the NRZI modulation result. Similarly, the determination / insertion unit of the control bits DSV 11 calculates a total DSV for the segment of DATA2 after DATAl. Let xl be a control bit of the DSV when inserted in a place between data pieces DAT0S1 and DAT0S2. The determination / insertion unit of the control bits of the DSV 11 determines the value of the control bit of the DSV xl, so that the absolute value of the sum of the DSVs for the DAT0S1, xl and DAT0S2 • 5 approaches 0. If the DSV control bit xl is set (1), the level codes of segment DAT0S2 after DAT0S1 is inverted. If the control bit of the DSV xl is set (0), on the other hand, the level codes of the DATA segment2 after DATA1 is not inverted. This is because, in • each element of the conversion tables of Tables 2 and 3, the remainder of the division of the count "1" of an element of an ordered sequence of data by 2 that have a value of 0 or 1 will always equal the remainder of the counting division "1" of an element of the ordered sequence of code words resulting from the conversion of the ordered sequence of data by 2. In this way, the insertion of a bit (1) in the • ordered sequence of data must be accompanied by the insertion of a "1" into the ordered sequence of words of code resulting from the conversion of the ordered sequence of data in the case in which the investment is involved. After the value of the control bit of the DSV xl shown in Figure 2 has been determined as described above, a control bit of the DSV is inserted. x2 between the DAT0S2 and the DATA3 providing a predetermined data interval between xl and x2 to implement the DSV control in the same way. In this case, the cumulative DSV is the sum of the cumulative DSV for data up to DAT0S1, the value of the DSV for xl and the data of the DSV for the segment of DAT0S2. As described above, the control bits of the DSV are inserted in an ordered sequence of data in advance before the ordered data sequence is modulated by the modulation unit 12 to generate a channel bit stream. Figure 3 is a block diagram showing a typical configuration of the modulation unit 12. As shown in the Figure, a diversion recorder 31 diverts the data stored therein in 2 bits at a time, supplying its output to a unit that judges the length of the restriction 32, a unit that detects the code that limits the consecutive appearance of the minimum site 33, a unit that detects the code that secures the limit of the length of the cycle 34 and all the conversion units 35- 1 to 35-4. The deviation register 31 supplies as many bits as required to process each of the components 32 to 35. The unit that judges the restriction length 32 determines the restriction length i of the data and supplies the length ia a multiplexer 36. When the unit that detects the code limiting the consecutive appearance of the minimum cycle 33 detects a special data word subject to limitation of consecutive occurrences of the minimum cycle d, the unit that detects the code limiting the consecutive appearance of the minimum cycle 33 supplies a signal of detection (i = 3) indicating the restriction length ia the unit judging the restriction length 32. In the case of Table 2, the special data word (110111). In the same way, when the unit that detects the code that secures the cycle length limit 34 detects a special data word that requires securing the maximum cycle k, the unit that detects the code that secures the limit of the cycle length 34 applies a signal of the same (i = 4) indicating the restriction length ia to the unit judging the restriction length 32. In the case of Table 2, the special data word is (00001000) or (00000000). When a special data word is detected by the unit that detects the code limiting the consecutive occurrence of the minimum cycle 33 or the unit that detects the code that secures the limit of the cycle length 34, the unit that judges the restriction length 32 passes the restriction length i of the special data word to the multiplexer 36. At that time, the unit judging the restriction length 32 can also determine another value for the restriction length itself. In this case, however, the unit that judges the restriction length 32 allows the restriction length to be supplied by the unit that detects the code that limits the consecutive appearance of the minimum cycle 33 or the unit that detects the code that secures the limit of the Cycle length 34 takes precedence over what is determined by itself. In other words, the largest restriction length is selected. The conversion units are 35-1 to 35-4 each form a judgment of whether or not a basic code for the data supplied to them is cataloged in a conversion table included in them. If the basic code is cataloged, the data is converted into a code word represented by the basic code and the code word resulting from the conversion is supplied to the multiplexer 36. If the basic code for the data is not cataloged in the table Conversion, on the other hand, the conversion units 35-1 to 35-4 discard the data. It should be noted that, since the modulation apparatus 12 is designed for the conversion table of Table 2, each of the conversion units 35-i is designed to work the data conversion with a restriction length i to 4. That is, each of the conversion units 35-i is designed to work the data conversion of up to a maximum restriction length r of 4. The multiplexer 36 selects a code resulting from the conversion carried out by one of the units of ^ 5 conversion 35-i corresponding to a restriction length i supplied by the unit judging the restriction length 32. The selected code is then sent by means of a buffer 37 as serial data. The timing operation of each component is controlled in synchronization with the timing signals generated by the timer control unit 14. The operation of the mode is described below. First of all, the deviation recorder 31 supplies as many bits of data as required to process such a judgment formation into base units in bits to the unit judging the restriction length 32, the unit that detects the code that limits the appearance consecutive of the minimum cycle 33, the unit detects the code that secures the limit of the cycle length 34 and all the conversion units 35-1 to 35-4. Provided with an included conversion table similar to that in Table 2, the unit that judges the length of restriction 32 determines the value of the restriction length i referring to the table of conversion and supply to the value of the multiplexer 36. In the unit that detects the code limiting the consecutive appearance of the minimum cycle 33, a word of • 5 data can be replaced by the substitution code to limit the consecutive occurrences of the minimum cycle d of Table 2 provided it is included in the next code word "010". In the case of Table 2, the data word is (110111) when the data that require limitation of consecutive occurrences of the minimum cycle d detected as a result of the reference to this part of the conversion table, the unit that detects the code limiting the consecutive occurrence of the minimum cycle 33 sends a detection signal indicating that the restriction length i = 3 to the unit judging the restriction length 32. In the unit that detects the code that secures the cycle length 34, on the other hand, the data words to be replaced by the replacement codes to ensure the limit of the cycle length of the Table 2 are included. In the case of Table 2, the data words are (00001000) and (00000000). When the data required to ensure the limit of the length of the cycle are detected as a result of the reference to this part of the conversion table, the unit that detects the code that secures the limit of the cycle length 34 sends a detection signal indicating the restriction length i = 4 to the unit judging the restriction length 32. When a detection signal is received indicating ^ 5 that the restriction length i = 3 in the case of Table 2 of the unit that detects the code limiting the consecutive occurrence of the minimum cycle 33, the unit that judges the restriction length 32 passes the value i = 3 to multiplexer 36, even if at that time the unit that judges the length of Restriction 32 determines the value of the restriction length i itself instead of supplying the value determined itself to the multiplexer 36. In the same way, when a detection signal is received indicating that the restriction length i = 4 in the case of Table 2 of the unit that detects the code that secures the limit of the cycle length 34, the unit that judges the restriction length 32 passes over the value i = 4 to the multiplexer 36, even if at that moment the unit that judges the restriction length 32 determines that the value of the length of Restriction i by itself, instead of supplying the value determined by itself to the multiplexer 36. This means that, the unit that judges the restriction length 32 passes the value of the restriction length i received from the unit that detects the code that limits the consecutive occurrence of the minimum cycle 33 or the unit that detects the code that secures the limit of the length of the cycle 34 to the multiplexer 36 instead of supplying the value determined in itself, if the value of the restriction length i determined by the unit that detects the code limiting the consecutive appearance of the minimum cycle 33 or the unit that detects the code of the length limiting the cycle 34 is different from the value determined in itself . In other words, the largest restriction length to be transmitted to the multiplexer 36 is selected. Figure 4 is a diagram that exemplifies the process carried out by the unit that judges the restriction length 32, the unit that detects the code that limits the consecutive appearance of the minimum cycle 33 and the unit that detects the code that ensures the limit of the length of cycle 34, showing an example in concrete terms. As described above, in the unit that detects the code that secures the limit of the cycle length 34, the data words (00001000) and (00000000) of Table 2 are included as part of a function thereof to determine the value of the restriction length i. When the 8-bit data matching the data word (00001000) or (00000000) is supplied, to the unit that detects the code that secures the limit of the cycle length 34, the unit that detects the code that secures the limit of the cycle length 34 sends a detection signal indicating that the restriction length i = 4 to the unit judging the restriction length 32. In the unit that detects the code limiting the consecutive occurrence of the minimum cycle 33, by On the other hand, data words (110111) of Table 2 are included as a function thereof to determine the value of the restriction length i. When 6-bit data matching the data words (110111) is supplied to the unit that detects the code limiting the consecutive occurrence of the minimum cycle 33 and the 3-bit code word resulting from the conversion after the data word is "010", the unit that detects the code limiting the consecutive occurrence of the minimum cycle 33 sends a detection signal indicating that the restriction length i = 3 to the unit judging the restriction length 32. It should be noted that the 3-bit code word "010" is the result of the conversion of an ordered sequence of data having a value of (01), (001) or (00000) before conversion. In other words, the function includes an ordered sequence of data (110111) + (01/001/00000). When 6-bit data that is equal to the data word (110111) is detected, data of up to 5 bits is compared after the 6-bit data with the word (01) or (001) or (00000) to determine if they are same as each other. If the incoming data is (11011101), (11011001) or (11011100000), the unit that detects the code limiting the consecutive occurrence of the minimum cycle 33 sends a detection signal indicating that the restriction length i = 3 to the unit which judges the restriction length 32. In the unit that judges the restriction length 32, the ordered data sequences of the conversion table of Table 2 are included. 6-bit data is supplied which is equal to the data words (000011), (000010), (000001) or (000Q00) to the unit that judges the restriction length 32, the unit that judges the restriction length 32 determines that the value of the length of the constraint i is 3. If data of 4 bits equal to the data words (0011) are supplied, ( 0010) or (0001) to the unit judging the restriction length 32, the unit judging the restriction length 32 determines that the value of the restriction length i is 2. If 2-bit data equal to the words are supplied of data (11), (10) or (01) to the unit judging the restriction length 32, the unit judging the restriction length 32 determines that the value of the restriction length i is 1. Assume that they are supplied 6-bit data (000010). In this case the unit judging the restriction length 32 determines that the value of the restriction length i is 3. Also assume that 2-bit data (00) follows the 6-bit data. As a result, data of 8 bits equal to the data words (00001000) is supplied to the unit that detects the code that secures the limit of the length 34, causing the unit that detects the code that secures the code of the length of the cycle 34 sends a signal • 5 detection which indicates that the restriction length is i = 4 to the unit judging the restriction length 32. In this case, the unit judging the restriction length 32 allows the detection signal to convey the value of 4 of a unit that detects the code that secures the limit of the cycle length 34 that precedes the value of 3 determined • by itself, judging that the restriction length i has a value of 4. As described above, the restriction length of the data comprising a train of (1) and (0) can be determined according to the conversion table to Table 2 by referring to a supplied data word of up to 8 bits corresponding to a maximum restriction length and, if necessary, a 3-bit code word. As an alternative, the restriction length of the data comprising a train of (1) and (0) can be determined by referring to only one supplied data word of up to 11 bits. The unit that judges the restriction length 32 supplies the values of the restriction length i determined in this way to the multiplexer 36.

It should be noted that the unit judging the restriction length 32 can also determine the value of the restriction length i in ascending order of the values of i starting with the smallest, i.e., of the order of i = l, i = 2, i = 3 ei = 4 as opposed to that shown in Figure 4. The conversion units 35-1 to 35-4 each have a conversion table corresponding to a value of the restriction length assigned to it. To be more specific, the conversion units 35-1 to 35-4 have conversion tables for i = l, i = 2, i = 3 and i = 4, respectively. If a conversion rule for the data supplied to any of the conversion units 25-1 to 35-4 is cataloged in the table of the conversion units, the 2 xi bits of the supplied data are converted into 3 xi bits of the code according to the cataloged conversion rule. The resulting code is then supplied to the multiplexer 36. The multiplexer 36 selects a code that results from the conversion carried out by one of the conversion units 35-1 corresponding to a restriction length supplied by the unit judging the length of restriction 32. The selected code is then sent by means of a buffer 37 as serial data.

As shown in Table 2, for the restriction length i = 3, the conversion table includes a substitution code for an ordered sequence of data (110111) which requires limitation on the consecutive repetitive occurrences of the minimum cycle d. Assume that the following ordered sequence of data is provided: (1101110111011101) In this case, the conversion process is carried out in the following word order of data: (11), (01), (11), (01), and so on. As a result of the conversion, the following ordered sequence of code words (a channel bit stream) is generated: "101 010 101 010 101 010 101 010" Next, the typical NRZl modulation is applied to the ordered sequence of words of generated code to carry out the level coding. Since the logical inversion takes place with the timing lr in the signal, the ordered sequence of previous code words is converted into the following ordered sequence of code words:? 110 011 001 100 110 011 'where the minimum investment intervals 2T they continue through the ordered sequence. When registering or playing at a high line density, such an ordered sequence of code becomes a pattern which easily causes an error in the recording or playback operation. Assume that the conversion table in Table 2 also prescribes a substitution code for a sequence • 5 ordered data (110111) which requires the limitation on consecutive repetitive occurrences of the minimum d. Now, the following ordered sequence of data is provided: (1101110111011101) 10 In this case, the first data word • (11011101) in the ordered data sequence comprises a data word (110111) followed by a data word (01) which will be converted into an ordered sequence of code words "010". In this way, the first word of data is converted into the following ordered sequence of code words: "001 000 000 010". Similarly, the second word of data (11011101) in the ordered sequence of data also comprises the data word (110111) followed by the data word (01) which will be converted into the ordered sequence of code words "010". In this way, the first data word is converted into the following ordered sequence of code words: 25"001 00 000 010".

As a result, the ordered sequence of data is converted into the following ordered sequence of code words: "001 000 000 010 001 000 0Q0 010 ..." where repeated repetitive occurrences of the minimum cycle d are avoided. That is, a pattern that easily causes an error in the registration or reproduction operation at a high line density is eliminated. It should be noted that, in the conversion of the ordered sequence of data into the ordered sequence of code words described above, the minimum cycle d and the maximum cycle k retain their respective values. As described above, the conversion carried out by the modulation apparatus 1 is based on the conversion table of Table 2. It should be noted that the conversion can also be carried out using the conversion table of Table 3. In In this case, the unit that detects the code limiting the consecutive appearance of the minimum cycle 33 used in the modulation unit 12 shown in Figure 3 is provided with Table C for the restriction length i = 4 of Table 3, by On the other hand, the unit that detects the code that secures the limit of the length of cycle 34 is provided with Table A for the restriction length i = 2, Table B for the restriction length i = 3 and Table D for the restriction length i = 4 of Table 3.

Incidentally, in Tables 2 and 3, the composition of each pair of an ordered sequence of data and an ordered sequence of code words within a group of the same restriction length may change. In the case of the group of the constraint length i = 1 of Table 2, for example, the composition of each pair is originally shown below: Data Code 10 i = l 11 * o * • 10 001 01 010 The composition of the pair can change as follows: 15 Data Code i = l 11 * Q * • 10 010 01 001 20 Even with a changed pair composition, the remainder of the division of the control "1" of an element in an ordered sequence of data by 2 that has a value of 0 to 1 will always be equal to the remainder of the division of the count of "1" of an element in the ordered sequence of code words resulting from the conversion of the ordered sequence of data by 2. Next, an embodiment implementing a demodulation apparatus provided by the present invention is explained referring to the Figure 5. In the present embodiment, a variable length code (d, k; m, n; r) = (l, 7; 2, 3; 4) is demodulated again in an ordered sequence of data using Table 2. As shown in Figure 5, the demodulation apparatus 100 comprises a demodulation unit 111 for demodulating a signal received from a transmission line or a signal reproduced from a recording medium using the modulation table or a reverse conversion table and a unit that removes the control bits of the DSV 112 to remove the control bits of the DSV inserted in the ordered sequence data resulting from the demodulation at arbitrary intervals of the ordered sequence of data to restore the original ordered data sequence. A buffer 113 is used to temporarily store the serial data generated by the unit that removes the control bits from the DSV 112. The data stored in the buffer 113 is subsequently re-measured at a predetermined transfer rate to produce a signal of exit. A timing control unit 114 generates timing signals and supplies the signals to a variety of components to control the timing of their operations. Figure 6 is a block diagram showing • 5 the configuration of the demodulation unit 111. As shown in the figure, the demodulation unit 111 has a comparator 121 for converting more hybrid signals from a transmission line or a reproduced signal from a recording medium into binary data. If the signal supplied to comparator 121 is a signal that completed the NRZl modulation (ie, the level coding), the signal undergoes an inverse NRZl coding process (i.e., a process that encodes the limit). A unit that judges the restriction length 122 determines the restriction length i of a digital signal received from the comparator 121. When a unit that detects the code limiting the consecutive occurrence of the minimum cycle 123 detects a special code to limit consecutive occurrences of the minimum cycle d of the digital signal generated by the comparator 121, the unit that detects the code limiting the consecutive appearance of the minimum cycle 123 supplies a detection signal thereof (i = 3) indicating the restriction length i to the unit judging the restriction length 122. In the case of the Table 2, the special code is "001 000 0Q0". Of the same mode, when the unit that detects the code that secures the limit of the length of the cycle 124 detects a special code to ensure the maximum cycle, the unit that detects the code that secures the limit of the length of the cycle 124 supplies a signal of detection of the same (i = 4) indicating the restriction length ia the unit that judges the restriction length 122. In the case of Table 2, the special code is "000 100 100 100" or "010 100 100 100" . The reverse conversion units 125-1 to 125-4 each have a table used to reverse convert a variable length code of n x i bits back into data of m x i bits. In the case of Table 2, the inverse conversion units 125-1 and 125-4 have the inverse conversion tables for the restriction length i = 1 to 4, respectively, which are essentially the same as the tables of conversion included in the conversion units 35-1 to 35-4 described at the beginning. A multiplexer 126 selects one of the outputs generated by the reverse conversion units 125-1 to 125-4 depending on the judgment results received from the unit judging the length of the restriction 122. The operation of the demodulation unit 111 shown in Figure 6. A signal received from a transmission line or a reproduced signal from a recording means is supplied to the comparator 121 to be subjected to comparison. A signal produced by ~ the comparator 121 is a digital signal of inverse NRZl code, that is, the code with a "1" indicating a limit. The digital signal is then supplied to the unit that judges the restriction length 122 to determine the restriction length and the signal using the conversion table (strictly speaking, the inverse conversion table) of Table 2. A judgment result , i.e., a value of the restriction length i, produced by the unit judging the restriction length 122 is supplied to the multiplexer 126. In addition, the digital signal produced by the comparator 121 is also supplied to the unit that detects the code which limits the consecutive occurrence of the minimum cycle 123. The unit that detects the code limiting the consecutive occurrence of the minimum cycle 123 has a "reverse conversion" portion included which includes a substitution code of the inversion table of Table 2 to limit the consecutive occurrences of the minimum cycle D. In the case of Table 2, the substitution code is the code word "001 000 000". When a code "001 000 000 not 100" cataloged in the inverse conversion table to limit the consecutive occurrences of the minimum cycle d is detected from the digital data ,, the unit that detects the code that limits the consecutive appearance of the minimum cycle 123 sends the restriction length i = 3 to the unit judging the restriction length 122. In addition, the digital signal produced through the comparator 121 is also supplied to the code detecting unit that secures the limit of the length of the cycle 124. The unit that detects the code that secures the limit of the length of the cycle 124 has a portion reverse conversion included that includes substitution codes of the inversion table of Table 2 to maintain the maximum cycle k. In the case of Table 2, the replacement codes are the code words "000 100 100 100" and "010 100 100 100". When the code word is "000 100 100 100" or "010 100 100 100" cataloged in the reverse conversion table to preserve the maximum cycle k is detected from the digital data, the unit that detects the code that secures the limit of the length of the cycle 124 sends the restriction length i = 4 to the unit judging the restriction length 122. Figure 7 is a diagram showing a summary of the processing for determining the restriction length i of a modulated code supplied to the apparatus of demodulation 100. As shown in the figure, the unit that detects the code that secures the limit of the length of cycle 124 has a reverse conversion portion included that includes the code words "000 100 100 100" and "010 100 100 100"of the inversion table of Table 2. When an ordered sequence of 12-bit code words is supplied to the unit that • 5 detects the code that secures the limit of the length 124 equalizes any of the code words in the reverse conversion portion, the unit that detects the code that secures the limit of the length of the cycle 124 sends the restriction length i = 4 to the unit that judges the restriction length 122. • Similarly, the unit that detects the code limiting the consecutive occurrence of the minimum cycle 123 has a reverse conversion portion included that includes the code word "001 000 000" of the inversion table of Table 2. When orderly sequences of 12-bit code words are supplied, to the unit that detects the code limiting the consecutive occurrence of the minimum cycle 123 equal to "001 000 000 not 100", the unit that detects the code that limits the consecutive appearance of the minimum cycle 123 sends the restriction length i = 3 to the unit that judges the restriction length 122. It should be noted that the 12 detected bits of the ordered sequence of code words are actually "001 000 000 010" even if it has not been done nothing with the determination of the length of the restriction i in particular.

The unit judging the restriction length 122 has a reverse conversion table included in Table 2. If an ordered sequence of 9-bit code words supplied to the unit judging the restriction length • 5 122 is "000 100 100" or "010 100 100" or if an ordered sequence of 12-bit code words supplied to it is "000 100 000 not 100" or "010 100 100 not 100", the unit that judge the restriction length 122 determines that the restriction length i is 3. If one of the sequences ordinates of 6-bit code words supplied to the • unit judging restriction length 122 is "010 100" or "000 100 ', or if one of the ordered sequences of 9-bit code words supplied to it is" 010 000 not 100", on the other hand, the unit that judges the restriction length 122 determines that the restriction length i is 2, otherwise, if one of the ordered sequences of 3-bit code words supplied to the unit judging the restriction length 122 is "000", "01" or " 010"the unit that judges the restriction length 122 determines that the The restriction length i is 1. It should be noted that the unit that judges the restriction length 122, the unit that detects the code that limits the consecutive occurrence of the minimum cycle 123 and the unit that detects the code that secures the limit of the Cycle length 122 can each also carry out the processing in ascending order of the values _and beginning with the smallest one, that is, in the order of i = l, i = 2, i = 3 ei = 4 in opposition to that shown in Figure 7. Assume that the unit that judges the restriction length 122 can also determine the value of the restriction length i in the order of i = 2 / i = 3 ei = 4 and an ordered sequence is supplied of code words "000 100 100 100" to the unit judging the restriction length 122. The unit judging the restriction length 122 compares the ordered sequence of code words supplied thereto with the code words in the table conversion included in an ascending order of values of the restriction length i starting with the smallest to form a judgment of whether or not the ordered sequence of code words is equal to the code words. The ordered string of code words "000 100 100 100" supplied to the unit judging the restriction length 122 equals the codewords for all the restriction lengths i = l, i = 2, i = 3 and i = 4. In such a case, as a determination rule, the largest restriction length is selected and supplied to the multiplexer 126. The inverse conversion table of the reverse conversion unit 125-1 is implemented as a memory where a piece of data is stored. (11) in the addresses "101" and "000" while the pieces of data (10) and (01) are stored in the addresses "001" and "010", respectively. The tables of inverse conversion of the units of • 5 reverse conversion 125-2 and 125-4 with each implemented as a memory to store data in the same way as the reverse conversion units 125-1. An ordered sequence of code words of 3 X i bits supplied to the inverse conversion unit 125-i is converted again in an ordered sequence of data of 2 X i bits, which is • then supplied to the multiplexer 126. The multiplexer 126 selects one of the ordered data sequences supplied by the reverse conversion units 125-1 and 125-4 according to a result of the determination of the value of the restriction length i produced by the unit judging the restriction length 122. Table 4 is an inverse conversion table for Table 2. 20 < Table 4 > Reverse Conversion Table (1, 7: 2, 3; 4) Orderly Sequence of ordered sequence Desmodulated data code words 25 i = 1 101 11 000 11 001 10 010 01 i = 2 010 100 0011 010 000 (not 100) 0010 000 100 0001 i = 3,000 100 100 000011 000 100 000 (not 100) 000010 010 100 100 000001 010 100 000 (not 100) 000000 i = 3: Minimum Transition Cycle Length Prohibited 001 000 000 (not 199) 110111 i = 4: Limits from k to 7 000 100 100 100 00001000 010 100 100 100 00000000- Figure 8 is a flow diagram used as a reference in the explanation of the operations carried out by the unit that removes the control bits from the DSV 112. The unit that removes the control bits from the DSV 112 is provided with an internal counter . As shown in the figure, the flow chart begins with a step SI in which the number of bits in an ordered sequence of data is supplied by the demodulation unit 111 are counted by the internal counter. The processing flow is then shifted to step S2 to form a judgment as to whether or not the number of bits has reached a value representing a predetermined data interval in which a control bit of the DSV was inserted. If the judgment result indicates that the number of bits does not correspond to an arbitrary Q data range, the processing flow proceeds to step S3 in which the data supplied to the demodulation unit 111 is sent to the buffer 113 as they are. . If the judgment result indicates that the number of bits corresponds to a predetermined data interval, indicating 5 that the current bit is a control bit of the DSV, on the other hand, the processing of step S3 is omitted. That is, the current bit of the ordered data sequence is discarded instead of being sent to the buffer 113 in this case. In any case, the processing flow proceeds to a step S4 in which processing is carried out to introduce a next ordered sequence of data. The flow of the processing then continues at a step S5 to form a judgment as to whether or not processing of all data that is not processed exists, the processing flow returns to step SI to repeat the processing execution. If the result of the trial formed in step S5 indicates that all the data has been processed, on the other hand, the process ends. • As a result, the control bits of the DSV are removed from the data sent by the unit that removes the control bits from the DSV 112. The data is then sent by means of the buffer 113. According to the description given above , the demodulation unit 111 uses the conversion table of ^ 'Table 2 or, strictly speaking, the inverse conversion table of Table 4. It should be noted that similar processing can be carried out using the conversion of Table 3 or, strictly speaking, the conversion table inverse of Table 5 given below. In this case, the unit that detects the code limiting the consecutive occurrence of the minimum cycle 123 employs the modulation unit 111 shown in Figure 6 provided by Table C for the restriction length i = 4 of Table 3.

On the other hand, the unit that detects the code that secures the limit of the length of cycle 124 is provided with Table A for the restriction length i = 2, Table B for the restriction length i = 3 and Table D for the restriction length i = 4 of Table 3. 25 < Table 5 > Reverse Conversion Table (1, 7; 2, 3; 4) Orderly Sequence of ordered Sequence code words of demodulated data r = l Main Table 101 00 100 01 001 10 000 11 r = 2 Substitution Table A (limits from d to 1) 1Q0 010 0000 101 010 0001 000 010 1000 001 010 1001 r = 3 Substitution Table B (limits from k to 8) 000 010 010 Lililí 001 010 010 111110 101 Q10 010 011110 100 010 010 011111 r = 4 Substitution Table C (limits of RMTR to 6) 10Q 010 010 010 00010001 100 000 010 010 10010001 000 010 010 010 10010001 r = 4 Substitution Table D (limits from k to 1] 000 001 010 010 11100000 100 001 010 010 11100010 001 010 010 010 11100001 101 010 010 010 11100011 By the way, there are cases in which it is necessary to insert a synchronization signal (Sinc) in the data. Next, the embodiments implementing a modulation apparatus 1 and a demodulation apparatus 100 are described which are capable of copying data with inserted synchronization signals referring to Figures 9 and 10, respectively. Also in the case of these modalities, the ordered sequences of data are modulated in a variable length code (d, k; m, n: r) = (1, 7; 2, 3; 4). In another modulation apparatus of the present invention shown in Figure 9 where the synchronization signals are inserted at predetermined intervals, the output of a control bits insertion / determination unit of the DSV 11 is supplied to a unit that determines the signal synchronization 211. Also supplied to the unit which determines the synchronization signal 211 is the output of a modulation unit 12. When the unit that determines the synchronization signal 211 determines a synchronization signal of the signals supplied by the determination unit / insertion of the control bit of the DSV 11 and the modulation unit 12, the unit that determines the synchronization signal 211 sends a synchronization signal to a unit that inserts the synchronization signal 212. The unit that inserts the synchronization signal 212 inserts the synchronization signal supplied by the unit that determines the synchronization signal 211 by a modulated signal supplied by the modulation unit 12 and supplies the output thereof to a coding unit NRZl 13. The rest of the configuration is the same as that of the modulation apparatus 1 shown in Figure 1. In the In case of a pattern of a 24-bit codeword to serve as a synchronization signal, the synchronization signal is converted by the unit that determines the synchronization signal 211 according to Table 2 in the following code: "# 01 001 000 000 001 0Q0 000 001"where the symbol # denotes a bit that depends on an immediately preceding sequence of data, which includes a DSV control bit, if any, delimited by the insertion of the synchronization signal. To be more specific, when using a termination table to complete an operation to modulate the data stream delimited by the use of the conversion table, "#" = "1". When Table 2 is used for the termination instead of the termination table, on the other hand, "#" = "0". In this way, the modulation unit 12 sends "#" = "1" or "#" = "0" to the • 5 unit which determines the synchronization signal 211 when the termination table is used or is not used respectively. Receiving the value of "#" from the modulation unit 12, the unit that determines the synchronization signal 211 append the value of "#" to the header of the sync signal and then send the signal of • synchronization to the unit inserting the synchronization signal 212. The unit inserting the synchronization signal 212 inserts the synchronization signal supplied to the unit that determines the synchronization signal 211 in a modulated signal supplied to the demodulation unit 12 and supplies the output thereof to the coding unit • NRZl 13. The rest of the processing is the same as the modulation apparatus shown in Figure 1. 20 The first data after the inserted synchronization signal is converted start with the header of the same without considering the data immediately preceding the synchronization signal. The modulation unit 12 and the unit that determines the signal of synchronization 211 are each provided with a counter to count the number of predetermined intervals to which the synchronization signals are inserted. The content of the counter is used to determine the position of a synchronization signal. • 5 As described above, the modality shown in Figure 9 uses the conversion table in Table 2. It should be noted that the conversion table in Table 3 can also be used. In this case, the unit that determines the signal of 211 synchronization adopts the word of 12-bit code given below as a pattern of • the synchronization signal: "xx 0 100 Q00 000 lOx" where the "x" symbol denotes a bit that is independent of the ordered sequences of data immediately coming and going, including a bit of the DSV control if there is one, delimited by the insertion of the synchronization signal. The 3 bits of the header in the 3 bits of the tail of the synchronization signal are determined by Table 3 as follows. Let (p) be the last sequence ordered data delimited by the insertion of the synchronization signal and (q) the first ordered sequence of data immediately after the synchronization signal. An ordered sequence of data (pl) is converted into the 3 bits in the header of the signal of synchronization while the ordered data sequence (Oq) is converted to the 3 bits of the synchronization signal queue using Table 3. The 3 bits of the header and the 3 bits in the queue of the synchronization signal resulting from the conversion wall the • 5 intermediate bits "100 000 000" to produce the pattern. By doing this, a synchronization signal can be generated which breaks the required maximum cycle k but always preserves at k = 8 (9T). Figure 10 is a block diagram that shows a typical configuration of a mode that • implements another demodulation apparatus 100 to demodulate the code resulting from the demodulation carried out by the modulation apparatus 1 shown in Figure 9. As shown in Figure 10, in the In this embodiment, an incoming signal transmitted through a predetermined transmission path to a demodulation unit 111 and a unit identifying the synchronization signal 221. The unit identifying the synchronization signal is supplied. uses the incoming signal and a signal received from the demodulation unit 111 to identify a synchronization signal, sending the synchronization signal to a unit that removes the synchronization signal 222. The unit that removes the synchronization signal 222 removes a signal of synchronization of a demodulated signal supplied by the demodulation unit 111 in accordance with the signal produced by the unit identifying the synchronization signal 221. The demodulated signal with its removed synchronization signal is then supplied to a unit that removes the control bit from the DSV 212. The rest of the configuration is the same as that of the demodulation apparatus 100 shown in Figure 5. The unit identifying the synchronization signal 221 has an included counter to count the number of code words. The content of the counter is used w to determine the position of each synchronization signal that is inserted in the sequence of data word nothing and predetermined intervals. After the position of the signal pattern has been identified synchronization, the "#" bit of the number determined in the modulation. That is, the bit in the header of the synchronization signal is read and sent to the demodulation unit 111. If the header bit is "1" the demodulation unit 111 uses the termination table of the Table 2 in the demodulation of a code immediately preceding the synchronization signal. If the header bit of "0", on the other hand, the demodulation unit 111 uses a table of conversion codes of Table 2 in the demodulation of an immediately preceding code of the synchronization signal. The remaining bits of the synchronization signal are discarded since they do not contain information. The unit identifying the synchronization signal 221 sends an identification signal to identify the bits that make up the synchronization signal to the unit that removes the synchronization signal 222. The unit that removes the synchronization signal 222 removes a synchronization signal from a demodulated signal supplied by the demodulation unit 111 in accordance with the identification signal produced by the unit identifying the synchronization signal 221. The demodulated signal with its synchronization signals removed is then supplied to a unit that removes the control bit of the DSV 112. As described above, the demodulation apparatus 100 shown in Figure 10 uses the conversion table of Table 2. It should be noted that Table 3 can also be used. In this case, for example, the unit identifying the synchronization signal 221 uses the contents of the counter to determine the position of each of the synchronization signals that are inserted in the ordered sequence of data words at predetermined intervals. After the position of a pattern of the synchronization signal has been identified, the unit identifying the synchronization signal 221 sends the signals specifying 3-bit code words in the header and the pattern queue of the synchronization signal to the demodulation unit 111 for requesting the demodulation unit 111 that those code words 5 are also demodulated since each includes an ordered sequence of data. The unit identifying the synchronization signal 221 sends a signal specifying the bits of the unique pattern of the synchronization signal which excludes the words of code that include ordered sequences of data to the unit • which removes the synchronization signal 222. In this way, the unit that removes the synchronization signal 222 is able to remove only the bits of the synchronization signal, ie, the bits of the unique pattern, specified by the signal received from the signal identifying the synchronization signal 221. FIG. 11 is a diagram showing an example of the code for recording synchronization signals and the • control bits of the DSV inserted in them. In this example, a 24-bit code word is used as a synchronization signal. The DSV control is executed at 56-bit data intervals and a synchronization signal is inserted for every 5 executions of the DSV control. In this way, the number of code words, that is, the number of channel bits for each synchronization signal is: 24 + (1 + 56 + 1 + 56 + 1 + 56 + 1 + 56 + 1 + 56 + 1) X 1.5 = 453 code words (channel bits). The relative redundancy introduced in the data words is approximately 7.3% as is obvious from the following calculation: Data quantity = (56 X 5) 1.5 / 453 = 420/453 = 0.927 Thus, the relative redundancy = 1 - 0.927 = 0.0728 = 7.3% The inventors and some other people performed simulations using the tables described above to produce the results of the modulation. The results of the modulation of an ordered sequence of data include DSV control bits inserted with consecutive occurrences of limited Tmin as described below. In the simulation, Tables 2 and 3 were used. A simulation was also performed using Table 1 for conventional RLL modulation (1-7) for comparison purposes. In the simulations, the DSV control was executed by inserting a DSV control bit for every 56 bits of random data data comprising 13,107,200 arbitrarily produced bits and the data was not then converted into an ordered sequence of code words (or a train). of channel bits) using the conversion code table of Tables 2 or 3. In another simulation, random data comprising 13,107,200 bits arbitrarily converted into an ordinary sequence of code words (or a channel bit stream) was produced. using the conversion code table of Tables 1 and 2, the channel bits were then inserted as a DSV control bit for each 112 code words or 112 channel bits of the ordered sequence of resultant code words to execute the DSV control. The reason why, in the simulation using Table 2 or 3, one control bit of the DSV was inserted for each 56 bits of data while, in the simulation using Table 1, 2 control bits of the DSV were inserted per every 112 code words is to make the relative redundancy caused by the control bits of the DSV uniform for both simulations. If the number of bits required to control the DSV in one case is different from the other case and the relative redundancy has been made uniform for both cases, Table 2 or 3 allows the DSV control to be executed with a high degree of efficiency by providing a good low band characteristic compared to Table 1. The numerical values of the simulation results were calculated as follows: Ren_cnt [the 101: occurrence of counts of 1 only minimum cycle to 10 consecutive minimum cycles.

T_size [2 to 10] Occurrence of counts from cycle 2T to cycle 10T. Sum: The number of bits Total: The number of cycle lengths, that is, • 5 the total number of occurrence of counts of cycle 2T, cycle 3T, etc. Average Cycle: (Sum / Total) Numerical values of the cycle distribution (T_size [i] * (i) / Sum) where i = 2, 3, 4, ... 10 10 The numerical values in the rows 2T to 10T of the # Table 6 are the numerical values of the cycle distribution. The numerical values of the distribution of the consecutive minimum cycles: 15 (Ren_cnt [i] * (i)) / T_size [2T], where i = 1, 2, 3, 4, ... 10 The numerical values on the rows RMTR • (1) to RMTR (9) of Table 6 are the numerical values of the distribution of the minimum consecutive cycles. Max_RMTR: The maximum number of DSV peak of repetitions of minimum cycle: Peaks of the values of the DSV calculated on the positive and negative sides observed in a process of execution of the control of the DSV on a train of bits of channel.

The calculation of the relative redundancy caused by the insertion of 1 DSV bit every 56 bits of data was based on the fact that there is 1 DSV bit for every 56 bits of data. In this way, the relative redundancy was calculated as • 5 follow: Relative redundancy = 1 / (1 + 56) = 1.75% The calculation of the relative redundancy caused by the insertion of 2 bits of DSV for each 112 bits of code was based on the fact that there are 2 bits of DSV for every 112 bits of code word. In this way, redundancy • relative was calculated as follows: Relative redundancy = 2 / (2 + 112) = 1-75% In this way, the same redundancy was obtained for both cases. 15 < Table 6 > PP17 comparison • < Table 2 > < Table 3 > < Table 1 > 17PP-32 17PP-52 +2 bits - DC (Without - DCC) (DSV control) (Without DSV control) Average Cycle 3. 3665 3. 404 3. 3016 3. 2868 Sum 20011947 20011947 20011788 19660782 Total 5944349 5877654 6061150 5981807 2Q 0.2256 0.2246 0.2417 0.1419 3T 0.2217 0.2069 0.2234 0.2281 4Q 0.1948 0.1935 0.1902 0.1915 5T 0.1459 0.1491 0.1502 0.1511 6T 0.1109 0.1904 0.1135 0.1141 7T 0.0579 0.0814 0.0561 0.0544 8T 0.0392 0.0351 0.0218 0.0188 9T 0.0023 10T 0.0009 RMTR (1) 0.3837 0.3890 0.3628 0.3641 RMTR (2) 0.3107 0.3137 0.2. 0.2883 RMTR (3) 0.173 £ 0.1906 0.1717 0.1716 RMTR (4) 0.0938 0.0806 0.0909 0.0907 RMTR (5) 0.0299 0.0228 0.0456 0.0452 RMTR (6) 0.0081 0.0033 0.0219 0.0217 RMTR (7) 0.0100 0.0099 RMTR (8) 0.0047 0.0046 RMTR (9) 0.0022 0.0022 Max_RMTR 6 6 18 18 DSV peak # -36 to 36 # -35 to 40 * -46 to 43 * -1783 to 3433 ("#"; 56 bits of data + 1 bit of, 1.75%) ("*"; 112 bits c + 2 bits of, 1.75%) The results given above verify that, using Tables 2 and 3, the RLL system (1, 7) was implemented while, at the same time, the minimum and maximum cycles are conserved and the number of consecutive occurrences of the minimum cycle is limited to 6. In addition, the results of the DSV verify that the DSV control can be executed in an ordered sequence of data (that is, that the values of the peak DSV are contained in predetermined interval) and, in this case, since the efficiency of the bits of the DSV control is high, it is possible to obtain low band components which are more satisfactory than those of the conventional method of inserting DSV bits into an ordered sequence of code words (a three bit channel). The results of the DSV verify that, in the case of Table 1, the difference between the positive and negative peak FVD is 89 (= 46 + 43) while in the case of Tables 2 and 3, the differences are 72 = 36 + 36) and 75 (= 35 + 40) respectively, which are both smaller than the value in Table 1. It is obvious from the above discussion that, in comparison with the conventional RLL (1-7) system, that is, , the system based on Table 1, the so-called 17PP system using Table 2 or 3 is capable of limiting the number of repetitions from minimum cycle to 6 at most. As a result, the improvement of the error characteristics can be expected at a high density online. Furthermore, since the efficiency of the DSV control is excellent, the execution of the DSV control in the 17PP system at the same relative redundancy of 1.75% as the conventional RLL (1-7) system results in a smaller difference between the positive and negative peak values. As a result, since the low band components can be suppressed, stable data recording / reproducing operations can be carried out. In addition, a simulation was also carried out to examine the propagation of a demodulation error caused by a bit deviation in a channel bit stream generated from the same random data as in the case described above. A test result indicates that the worst propagation of the error in the 17PP system is 3 bytes. However, the result also verifies that the frequency of the current generation of the error is all except 0, a value indicating that there is not too much deterioration compared to the conventional RLL (1-7) system. The • 5 average byte error rates of 1,014 bytes for the Table 1, 1,167 bytes for Table 2 and 1,174 bytes for Table 3 have been verified. It should be noted that, for the conversion tables provided by the present invention, the numerical values of the results of the rate or percentage errors include control bits of the DSV but, for the • conventional RLL system (1 - 7), the numerical value does not include the control bits of the DSV. That is, it can not necessarily be said that the measurements have been carried out under the same conditions. The difference in the measurement conditions can affect the numerical values and in this way it is necessary to take into account the effect of the difference in the comparison. < Table 7 > 20 Generation of Error Responses < Table 2 > < Table 3 > < Table 1 > 17PP-32 17PP-52 + 2bits-DC worst case 3 bytes 3 bytes 2 bytes (bits of) Included Included Excluded Error of. byte (0) 0.028 0..096 0.080 Byte error (1) 0.777 0. .0635 0.826 Byte error (2) 0.195 0. .268 0.094 Byte error (3) 0.000 0. .001 Byte Error Rate Average 1,167 bytes 1,174 bytes 1,014 bytes As described above, in the present embodiment, conversion tables with a minimum cycle d of 1, a maximum cycle k of 7 and a m / n conversion rate of 2/3 include substitution codes to limit the number of occurrences consecutive of minimum cycle length, giving rise to the following effects: / (1) Registration and reproduction operation is provided at a high line density and tolerance against tangential inclination. (2) It is possible to reduce the number of low-level portions, increase the accuracy of wave processing such as AGC and PLL and, consequently, increase the total characteristic. (3) In comparison with the conventional system, it is possible to have a design with a small path memory length of an abi bit code or the like and, consequently, to reduce the size of the circuit.

In addition, the remainder of the division of the control "1" of an element in an ordered sequence of data by 2 that has a value of 0 or 1 will always be equal to the remainder of the division of the count of 111"of an element in the sequence order of code words resulting from the conversion of the ordered sequence of data by 2, providing the following additional effects: (4) The number of redundant bits can be reduced for DSV control. (5) Can be executed, at a minimum cycle d of 1 and conversion parameters (m, n) of (2, 3), the DSV control, by a 1.5-bit codeword. (6) In addition to a low relative redundancy, the minimum and maximum cycles can be retained In addition, the conversion tables include, especially, substitution codes to preserve the cycle length limit, giving rise to the following additional effects: (7) The tables are compact. (8) The propagation of the modulation error caused by a Bit deviation may be placed in the same state as the conventional system based on Table 1. It should be noted that, when a medium that presents a program for presenting a computer program to be executed to carry out the processing described above, can be used a CD-ROM and a solid-state memory, communication means such as a network and a satellite, in addition to a recording medium such as a magnetic disk. • [EFFECTS OF THE INVENTION] As described above, according to a claimed modulation apparatus as claimed in claim 1, a modulation method claimed as claim 23, a medium that presents a claimed program as the • claim 24, a claimed demodulation apparatus as in claim 25, a claimed demodulation method as in claim 28 and a means that presents a claimed program as in claim 29, the conversion process is carried out on the basis of a conversion table that fulfills a conversion rule, according to which the remainder of the division of a count "1" of an element into a • ordered sequence of data by 2 that has a value of 0 or 1 should always be equal to the remainder of the division of a count of "1" of an element in the ordered sequence of code words resulting from the conversion of the ordered sequence of data by 2 and the conversion codes of the conversion table comprise: basic codes for d = l, k = 7, m = 2 and n = 3; first substitution codes to limit the number of consecutive occurrences of the minimum cycle d; and second substitution codes to preserve the limit of the length of a cycle k • As a result, the DSV control can be executed using a small number of redundant bits and an ordered sequence of code words can be recorded and reproduced with fewer errors at a high line density. In addition, the growth of the spread of a demodulation error caused by a bit deviation can be suppressed.

[BRIEF DESCRIPTION OF THE DRAWINGS] The embodiments of the present invention have been described with reference to the following diagrams where: Figure 1 is a block diagram showing a typical configuration of a mode that implements a modulation apparatus provided by the present invention; Figure 2 is an explanatory diagram used to describe the processing carried out by a control bit determination / insertion unit of the DSV 11 employed in the modulation apparatus shown in the Figure 1; Figure 3 is a block diagram showing a typical configuration of a unit 12 employed in the modulation apparatus shown in Figure 1; Figure 4 is a diagram exemplifying the processing carried out by the modulation unit 12 shown in Figure 3; Figure 5 is a block diagram showing a typical configuration of a mode that implements the demodulation apparatus provided by the present invention; Figure 6 is a block diagram showing a typical configuration of a demodulation unit 111 employed in the demodulation apparatus shown in Figure 5; Figure 7 is an explanatory diagram used to describe the processing carried out by the demodulation unit 111 shown in Figure 6; Figure 8 is a flowchart used as a reference in the explanation of the operations carried out by a unit that removes the control bits of the DSV 112 employed in the modulation apparatus shown in Figure 5; Figure 9 is a block diagram showing another typical configuration of a mode implementing a modulation apparatus provided by the present invention; Figure 10 is a block diagram showing another typical configuration of a modality that implements a • demodulation apparatus provided by the present invention; and Figure 11 is a diagram showing an example of a code for recording synchronization signals and the control bits of the DSV inserted therein. 10 • LIST OF THE MAIN NUMERICAL REFERENCES 11 Unit for determining / inserting control bits of the DSV 12 Modulation unit 13 Coding unit NRZl 31 Diversion recorder • 32 Unit that judges the restriction length 33 Unit that detects the code that limits the consecutive appearance of the minimum cycle 34 Unit that detects the code that ensures the limitation of the cycle length -1 to 35-4 Conversion units Multiplexor Buffer memory ' 1 Demodulation unit 2 Unit that removes control bits from the DSV 1 Comparator 2 Unit that judges the length of restriction 3 Unit that detects the code that limits the consecutive appearance of the minimum cycle 4 Unit that detects the code that ensures the limit of the length of the cycle -1 to 125-4 Inverse conversion units 6 Multiplexer

Claims (31)

1. CHAPTER CLAIMEDICATORÍO Having described the invention, it is considered as a novelty and, therefore, what is contained in the • 5 following CLAIMS: 1. A modulation device to convert data 10 with a basic data length of m bits in code ^ U »variable length (d, k; m, n; r) with a basic code length of n bits where d is a minimum cycle and k is a cycle length limit, the modulation apparatus is characterized in that it has means of conversion to convert data from 15 code entry according to a conversion table, where the conversion table complies with a conversion rule, according to which the remainder of the division of a count • "1" of an element in an ordered sequence of data by 2 that has a value of 0 or 1 should always equal the residue 20 of the division of a count of "1" of an element into the ordered sequence of code words resulting from the conversion of the ordered sequence of data by 2 and the conversion codes of the conversion table comprise: 25 basic codes for d = 1, k = 7, m = 2 and n = 3; first substitution codes to limit the number of consecutive occurrences of the minimum cycle d; and second substitution codes to maintain the limit of the cycle length k. • The modulation apparatus according to claim 1, characterized in that the number of pairs each comprises an ordered sequence of data and an ordered sequence of code comprising the basic code with a restriction length i of 1 is less than 10 4 (= 2? M = 2? 2). • The modulation apparatus according to claim 1, characterized in that the basic codes of conversion tables have a variable length structure. 4. The modulation apparatus according to claim 1, characterized in that the basic codes of the conversion tables include a code * 0 * 'where the • symbol * is an indeterminate code, which is? 0 'if a code word immediately preceding or later is 20? L 'and l' if the immediately preceding or subsequent code word is? 0 ', implying that the code * 0 *' is? 000 'or? 101'. 5. The modulation apparatus according to claim 1, characterized in that the codes of Conversion tables conversion includes codes, each determined by reference to an ordered sequence of immediately following code words or an orderly sequence of data immediately following. 6. The modulation apparatus in accordance with • 5 claim 1, characterized in that the conversion codes of the conversion tables include codes, each determined by reference to an ordered sequence of code words immediately after or an ordered sequence of code words of a specific type. 10 7. The modulation apparatus in accordance with • claim 5, characterized in that the codes, each determined by reference to an ordered sequence of code words immediately after or an orderly sequence of data immediately after, are the first 15 or second substitution codes. The modulation apparatus according to claim 1, characterized in that the number of pairs each comprises an ordered sequence of data and an ordered sequence of code comprising basic codes 20 for a restriction length i of 1 equals 4 (= 2? M = 2? 2). The modulation apparatus according to claim 1, characterized in that, for restriction lengths i of 2 and greater, the conversion codes are 25 all the first and second substitution codes. 10. The modulation apparatus according to claim 1, characterized in that the conversion codes for a restriction length i of 2 are the codes to preserve the minimum cycle d at 1. The modulation apparatus according to claim 1 , characterized in that the conversion codes of the conversion tables include codes, each determined by reference to an ordered sequence of immediately preceding code words. 10 12. The modulation apparatus in accordance with • claim 1, characterized in that the apparatus further has means for inserting synchronization signals to insert a synchronization signal that includes a unique pattern not included in the conversion codes of the table 15 conversion at any arbitrary position in the ordered sequence of code words. 13. The modulation apparatus in accordance with • claim 12, characterized in that the unique pattern is a pattern that breaks the maximum cycle k. 14. The modulation apparatus according to claim 12, characterized in that the unique pattern is a pattern that preserves the minimum cycle d. 15. The modulation apparatus according to claim 12, characterized in that a unique pattern in the The synchronization signal comprises a code word 1 in the header thereof which serves as a connection bit with a code word resulting from the conversion of immediately preceding data, a second bit to preserve the min. Cycle and a third bit. . 16. The modulation apparatus according to claim 12, characterized in that the synchronization signal is at least 12 words of size code. The modulation apparatus according to claim 12, characterized in that, for a synchronization signal of at least 21 size code words, the synchronization signal includes at least two patterns with a maximum cycle k of 8. 18 The modulation apparatus according to claim 12, characterized in that the conversion codes of the conversion table include terminator codes each for terminating the code resulting from the conversion. The modulation apparatus according to claim 18, characterized in that the termination codes are prescribed for the basic codes with a restriction length i, for which the number of pairs comprises each ordered sequence of data and a sequence ordered code that composes the basic codes 25 less than 4 (= 2Am = 2A2), and complies with a conversion rule, according to which the remainder of the division of a count of l 'of an element in an ordered sequence of data by 2 having a value of 0 or 1 should always equal the remainder of the division of a count of? l 'of an element in the ordered sequence of code words resulting from the conversion of the ordered sequence of data by 2. The modulation apparatus according to claim 18, characterized in that, in order to identify the termination code, a code word 1 in the header of the synchronization signal pattern n serves as a connection bit that is set to? l 'when the termination code is used and to? 0' when the termination code is not used. The modulation apparatus according to claim 12, characterized in that the unique pattern is walled by 3 bits in the header of the synchronization signal and 3 bits in the queue of the synchronization signal and 3 bits in the header and 3. bits in the queue, each is used as a union comprising mixed data and connection bits. The modulation apparatus according to claim 12, characterized in that: the first front of the 3 bits of the synchronization signal header has a value representing data words before the conversion seen in units of m bits; the second of the three bits is set to "1" to prescribe the synchronization signal; # 5 the first forward, of the 3 bits to the tail of the synchronization signal is set to "0" to prescribe the synchronization signal; and the second of the 3 bits in the queue represents data words before the conversion seen in units 10 of m bits. • The modulation apparatus according to claim 1, characterized in that the apparatus further has means of controlling the DSV to control a DSV of input data and supplying DSV to the means of 15 conversion. The modulation apparatus according to claim 1, characterized in that the conversion means comprise: first means detecting a code for 20 detecting the first substitution codes to limit the number of consecutive occurrences of the minimum cycle d; and second means detecting a code for detecting the second substitution codes to preserve the limit of the length of the cycle. 25. The modulation method to be adopted in a modulation apparatus for converting data with a basic data length of n bits the variable length code (d, k; m, n; r) with basic code length n bits where d is • 5 a minimum cycle and k is a limit of the length of the cycle, the modulation method is characterized by including a conversion step to convert input data into code according to a conversion table, where the conversion table fulfills a rule conversion, according to the 10 which remainder of the division of a count "1" of an element of an ordered sequence of data by 2 that has a value of 0 or 1 should always be equal to the remainder of the division of a count "1" of an element in the ordered sequence of code words resulting from the conversion of the 15 ordered sequence of data by 2 and the conversion codes of the conversion table comprise: basic codes for d = l, k = 7, m = 2 and n = 3; first substitution code to limit the number of consecutive occurrences of the minimum cycle d; and 20 seconds substitution codes to preserve the limit of the length of the cycle k. 26. The medium that presents a program to present a program that implements a conversion step to convert input data into code according to the 25 data of a conversion table and a modulation apparatus for converting data with a basic data length of n bits the variable length code (d, k; m, n; r) with basic code length n bits where it delimits is a minimum cycle and k is a limit of the length of the cycle, the modulation method is characterized by including a conversion step for converting input data into code according to a conversion table, where the conversion table complies with a conversion rule , according to which remainder of the division of a count "1" of an element of an ordered sequence of data by 2 that has a value of 0 or 1 should always be equal to the rest of the division of a count "1" of an element in the ordered sequence of code words resulting from the conversion of the ordered sequence of data by 2 and the conversion codes of the conversion table comprise: basic codes for d = l, k07, m = 2 and n = 3; first substitution codes to limit the number of consecutive occurrences of the minimum cycle d; and second substitution codes to preserve the limit of the cycle length k. 27. A demodulation apparatus for converting the variable length code (d, k; m, n; r) with a basic code length of n bits with a basic data length of m bits where d is a minimum cycle and k is a cycle length limit, the demodulation apparatus is characterized by having conversion means to convert input codes into data according to a conversion table where the conversion table complies with a conversion rule, according to which the waste of the division of the count "1" of an element and an ordered sequence of data having a value of 0 or 1 must always be equal to the remainder of the division of a count "1" of an element of the ordered sequence of words of code resulting from the conversion of the ordered sequence of data by 2 and the conversion codes of the conversion table comprises: basic codes for d = l, k = 7, m = 2 and n = 3; first substitution codes to limit the number of consecutive occurrences of the minimum cycle d; and second substitution codes to preserve the limit of the cycle length k. 28. The demodulation apparatus according to claim 27, characterized in that the apparatus further has means for removing bits to remove redundant bits inserted at predetermined intervals in the code. 29. The demodulation apparatus according to claim 28, characterized in that the redundant bits are DSV bits or synchronization signals. 30. A demodulation method to be adopted in a demodulation apparatus to convert variable length codes (d, k, m, n; r) with a basic code length of n data bits with a length of basic data m bits where d is a minimum cycle (and k is a limit of the length of the cycle?), the modulation method is characterized ^ P 5 for having a conversion step to convert input codes according to a conversion table where the conversion table complies with a conversion rule, according to which the remainder of the division of a count of "1" of an element of an ordered sequence of data by 2 that has 10 a value of 0 to 1 should be equal to the residue of the • division of a count "1" of an element into the ordered data sequence of code resulting from the conversion of the data sequence by 2 and the conversion codes of the conversion table comprises: 15 basic codes pairs for de = l , k = 7, m = 2 and n = 3; first substitution codes to limit the number of consecutive occurrences of the minimum cycle d; Y • second substitution codes to keep the cycle length limit k. 31. The medium that presents a program for presenting a program that includes a conversion step for converting code into data according to a conversion table in a demodulation apparatus for converting the variable length code (d, k; m, n; r) with a 25 basic code length of n data bits with a basic code length of m bits, where d is a minimum cycle and k is a cycle length limit, characterized in that the conversion table complies with a conversion rule, in accordance in which the residue of the division of a • count "1" of an element of an ordered sequence of data by 2 that has a value of 0 or 1 should equal the remainder of the division of a count of "1" of an ordered sequence element of resulting code words of the conversion of the ordered sequence of 10 data by 2 and the conversion codes of the table of • conversion comprises: basic codes for d = l, k = 7, m = 2 and n = 3; first substitution codes to limit the number of consecutive occurrences of the minimum cycle d; and 15 seconds substitution codes to keep the cycle length limit k. #