MX9606743A - Transport processor interface for a digital television system. - Google Patents

Transport processor interface for a digital television system.

Info

Publication number
MX9606743A
MX9606743A MX9606743A MX9606743A MX9606743A MX 9606743 A MX9606743 A MX 9606743A MX 9606743 A MX9606743 A MX 9606743A MX 9606743 A MX9606743 A MX 9606743A MX 9606743 A MX9606743 A MX 9606743A
Authority
MX
Mexico
Prior art keywords
data
transport processor
network
packetized
data rate
Prior art date
Application number
MX9606743A
Other languages
Spanish (es)
Other versions
MXPA96006743A (en
Inventor
Paul Wallace Lyons
Alfonse Anthony Acampora
Original Assignee
Thomson Multimedia Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Multimedia Sa filed Critical Thomson Multimedia Sa
Priority claimed from PCT/US1995/007459 external-priority patent/WO1996001024A1/en
Publication of MXPA96006743A publication Critical patent/MXPA96006743A/en
Publication of MX9606743A publication Critical patent/MX9606743A/en

Links

Landscapes

  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

A transmitted high definition television signal is represented by a packetized datastream configured as a sequence of data fields (fig. 1) with a non-uniform data rate due to different types of different duration non-data overhead information. Each data field is prefaced by a Field Sync overhead segment followed by 312 packetized data segments each with associated overhead information (FEC). At a transmitter (fig. 4), a transport processor (14) forms data packets with associated headers and exhibits uninterrupted operation at a constant uniform data rate, while supplying a packetized datastream to a network (17) which constructs sequential data fields by inserting the non-data overhead information into the datastream. The transport processor is advantageously operated at a constant uniform data rate without having to modify the original data field structure to accommodate the needs of the data field construction network. This result is facilitated by transferring data from the transport processor to an associated interface/buffer network (46) in response to a 3/8 symbol clock, in combination with a predetermined buffer fullness level. A counterpart transport processor/decoder (86) at a receiver (fig. 17) coacts with a data field processor (75) and similarly exhibits uninterrupted operation at a constant uniform data rate.
MX9606743A 1995-06-13 1995-06-13 Transport processor interface for a digital television system. MX9606743A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9413169.5 1994-06-30
PCT/US1995/007459 WO1996001024A1 (en) 1994-06-30 1995-06-13 Transport processor interface for a digital television system

Publications (2)

Publication Number Publication Date
MXPA96006743A MXPA96006743A (en) 1998-01-01
MX9606743A true MX9606743A (en) 1998-01-31

Family

ID=39165342

Family Applications (1)

Application Number Title Priority Date Filing Date
MX9606743A MX9606743A (en) 1995-06-13 1995-06-13 Transport processor interface for a digital television system.

Country Status (1)

Country Link
MX (1) MX9606743A (en)

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