MX2013007973A - Class ab output stage for operational amplifiers. - Google Patents

Abstract

The present invention provides a class AB output stage for improving the DC gain and the bandwidth in an OTA of two stages with a minimum consumption of power. The proposed topology allows the polarization current to be controlled in the output stage with the bipolar supply of the processed signal. The proposal allows the OTA of two stages to be designed, which only requires a capacitor for guaranteeing a frequency response with a phase margin higher than 45°. Said compensation scheme avoids the use of resistive elements which are sensitive to temperature and variations of the manufacturing process of the integrated circuit.

Description

AB OUTPUT STAGE FOR OPERATIONAL AMPLIFIERS Field of the invention The present invention belongs to the technical field of analog integrated circuits in complementary semiconductor oxide metal nanometric technologies; more particularly, it belongs to the technical field of transconductance operational amplifiers.

State of the art The design of analog integrated circuits in metal oxide nanometer technologies Semiconductor Complementary (CMOS) involves many restrictions. The reduction in the supply voltage and the reduction in the transconductance values for field effect transistors, Metal Oxide Semiconductor (MOS), make it difficult to fulfill important specifications such as direct current (DC) gain and bandwidth in the operational amplifiers of transconductance (OTA for its acronym in English). To obtain a wide bandwidth and a high gain in DC, it is typically necessary to increase the power consumption of the circuit. However, there must be a good compromise between the specifications fulfilled and the power consumption. An indispensable requirement for low consumption applications and therefore viable in portable implementation.

For the case of designing OTAs in conventional CMOS technologies, a strategy to increase the gain in DC is the use of stack transistors for i increase the intrinsic impedance. Other strategies use a technique to increase transconductance in "Folded Cascode" stages.

For example, patent application US2013106512 describes a folded cascode type operational amplifier that includes a first current source, a second current source, and a first voltage terminal connected to the first current source and the second current source. The operational amplifier also includes a first input-transistor connected to the first current source in series, and a second input transistor-connected to the second current source in series. In addition, the operational amplifier includes a current tail source connected to a connection point between the first input-transistor and the second input transistor, a load current source, and a second voltage terminal connected to the source of the current. tail current and source charge current. The operational amplifier also includes an output of transistors connected to the load current source, and an output-terminal disposed between the second current source and the second transistor-input and connected to the transistor output. The second current source is a current source reflected from the first current source, and a proportion of a current that passes through the second current source to a current that passes through the first current source is greater than one.

Similarly, patent application US2011291760 describes a differential amplifier that includes a high voltage input stage and a low voltage output stage. The entry stage is formed from High voltage MOS transistors, two of which constitute a differential pair. The output stage is formed from low voltage MOS transistors, some of which constitute a current mirror circuit connected to the differential pair. The output stage also includes at least one transistor that amplifies a voltage produced in the current mirror circuit to generate an output voltage signal. High voltage MOS transistors have high breaking voltages than low voltage MOS transistors. The incorporation of the two types of transistors in a single amplifier reduces the necessary number of transistors and the necessary number of polarization voltages.

Unfortunately, the above restricts the dynamic output range of the amplifier that causes distortion in the processed signal. Another alternative is the use of cascade amplifier stages. The disadvantage is the need for a compensation circuit for the cascade circuits that increases the resources used and can reduce the bandwidth of the amplifier. Another alternative to increase the bandwidth and speed of the amplifiers are the output stages in class AB. It is important to note that for this type of output stages it is very important to maintain control in the polarization and supply a bipolar signal path to obtain the benefit. Both actions are difficult to perform with reduced power consumption.

The present invention relates to an output stage of class AB that improves the gain in DC and the bandwidth in a two-stage OTA with a minimum power consumption. The proposed topology allows control of the bias current in the output stage with the bipolar supply of the processed signal. The proposal also makes it possible to design a two-stage OTA that requires only one capacitor to guarantee a frequency response with a phase margin greater than 45 °. Said compensation scheme avoids the use of resistive elements that are sensitive to temperature and variations of the manufacturing process of the integrated circuit.

Brief description of the figures Figure 1 is the circuit diagram for the transconductance operational amplifier, where (C) are capacitances, (M) are transistors, (V) are voltages, and (I) is intensity.

Figure 2 is the circuit layout at the transistor level, where (M) are transistors, and (V) are voltages.

Figure 3 are graphs showing the results of a simulation at the transistor level.

Best method of carrying out the invention With reference to figure 1, a simplified schematic representation of the invented topology for the transconductance operational amplifier is described. In this scheme, lb is the polarization current of the circuit, M, labels the CMOS transistors and Ci to the intrinsic and load capacitances. Figure 1 shows half of the fully differential implementation for analysis purposes. The elements Cpi, Cp2, Cp3 are capacitanciás parasites while Cc and CL are the compensation capacitance and the capacitive load to the OTA respectively.

The Mi and M2 transistors make up a preamplifier stage in a "Folded Cascode" configuration, and the output stage is composed of the M3 and 4 transistors in common source configurations. In the preamplifier circuit, transistor M2 functions as an intermediate stage that transfers signal to the output stage and at the same time stabilizes the operating point in current for said output stage. Transistor M2 is polarized with lb / 2 to maintain the sum of currents at node e2. The preamplifier stage distributes signal from the node ei to the upper common source stage (in transistor 4) while the signal in the node e? it is distributed to the lower common source stage (in the M3 transistor). Note that the polarization of the output stage depends strictly on the voltages Vgs3, Vgs4 that are set by ez and ei respectively. The Cc capacitor makes possible a frequency compensation without a resistor (which can be sensitive to process and temperature variations). For the circuit of Fig. 1 the polarizing current sources are ideal, however these can be replaced by high performance current sources to increase the gain in DC.

An expression to evaluate the frequency response of the circuit can be obtained if we consider: flL = SU = ¾, For the parasitic elements, let's consider because the transistors in the output stage increase the parasitic capacitance values. Finally, taking into account that the compensation capacitor is a multiple of the parasitic capacitances: Cc = aCp [3] The analysis of the circuit in Fig. 1 results in a gain in DC: ^ = ^ ((a *) 3 + 3 (s??) 2) [4] where rds = 1 / gds- A zero is in the value The non-dominant pole is in and the non-dominant pole is in 1 J The second term of the dominant pole equation p- \ (Equation 6) is slightly smaller than the first term, so the dominant pole is in low frequency. In the case of the non-dominant pole p2, it can be observe that it is a complex pole conjugated at a much higher frequency compared to the dominant one (note that in the denominator of the equation for p? the gas element does not appear).

An interesting aspect of the proposed circuit is that if the real part of the non-dominant pole is equalized to the location of the zero (ie, pi = zi), the circuit can compensate for the phase response of the zero on the left side of the complex plane . That is, a zero compensation is achieved if: From the above analysis it can be stated that the proposed circuit makes possible a frequency compensation for a two-stage amplifier with a single capacitor (without the need for a resistor that cancels zero). This significantly improves the reliability of the frequency response, since in an integrated circuit the capacitors are less sensitive to temperature and to the variation of the manufacturing process.

It is also possible to declare that the proposed circuit improves the DC response when obtaining a high gain, this is thanks to the "Folded Cascode" configuration in cascade with a common source configuration with the M3 transistor and the signal sum of the preamplifier towards the common source upper stage with the M4 transistor (see figure 1).

The amplifier circuit with proposed class AB output has been implemented in standard CMOS process with 90nm minimum channel transistors. Figure 2 refers to the completely differential implementation of the circuit at the transistor level. Note that the current sources for the polarization of the pre-amplifier stage have been implemented with single-current mirrors and high-performance current mirrors to increase the gain in DC. The reason for not using high performance current mirrors, both in the upper and lower current source, is to ensure that the circuit operates with the four stack transistors in the saturation region and prevent the preamplifier stage from displaying distortion in the processed signal. Being a completely differential configuration, the circuit uses a common mode feedback network to guarantee that it is at a fixed value. This circuit can be implemented in both discrete time and continuous time and the control voltage must be applied in the transistors M7, M7b of figure 2 which are driven by the feedback voltage Vcmfb to set the common mode to the output in Vdd /2.

For the design of said prototype have been used as design parameters a = 2 ß =? [9] The value of alpha is close to unity because in a nanometric process the transconductance values are of the same order of magnitude.

Figure 3 shows the result of a simulation at the transistor level with the aforementioned parameters. In the same figure the result is presented when the exit stage is only of type A (disabling the stage of common superior source and compensating the circuit with a passive Capacitor-Resistor architecture). From the obtained result it can be declared that the proposed topology increases the bandwidth with respect to the class A output. In the implemented prototype, a zero crossing frequency was obtained in 720MHz with a DC gain of 71dB. The phase margin obtained is 62 ° with a "Slew Rate" of 74V / us. It should be mentioned that the proposed amplifier has an excursion of the rail-to-rail signal with a power consumption of 360 micro Watt.

The present invention improves the bandwidth and frequency response of a two-stage OTA. The compensation in frequency has been achieved with a compensating capacitor that places the non-dominant pole in high frequency and a zero that can be compensated by that pole. This strategy avoids the use of a resistor that is sensitive to the variations of the manufacturing process of the integrated circuit and to the temperature. The benefits are obtained without a significant increase in the power consumed by the circuit.

The operational amplifier solution with class AB output has been compared with similar strategies in the state of the art. The following table shows a comparison of the most important specifications of an amplifier: gain in DC, bandwidth, phase margin, power consumption among others. To quantify the performance of the circuits, a merit figure (FoM) used in the state of the art has been used. The FoM is directly proportional to the bandwidth of the circuit by the load capacitance and is inversely proportional to the power consumption.

Equation 10 shows the expression of the FoM used and from the following table we can see that the proposed circuit has a benefit compared with similar schemes. It should be mentioned that in the FoM the dynamic range of the circuit has not been included, which is an additional advantage in the proposed solution.

Similarly, the proposed circuit eliminates the need for a resistor-capacitor compensation network that is more sensitive to variations in manufacturing process and temperature.

Frequency (Hz) FIGURE 3

Claims (2)

1. An operational amplifier type folded cascode, characterized in that it comprises an AB output stage determined by equations [1] - [10].

2. The operational amplifier of claim 1, characterized in that it comprises the topographies of integrated circuits established in Figures 1 and 2.