MX2010001064A - Esquema para empaquetado y vinculacion de variables en sistemas graficos. - Google Patents
Esquema para empaquetado y vinculacion de variables en sistemas graficos.Info
- Publication number
- MX2010001064A MX2010001064A MX2010001064A MX2010001064A MX2010001064A MX 2010001064 A MX2010001064 A MX 2010001064A MX 2010001064 A MX2010001064 A MX 2010001064A MX 2010001064 A MX2010001064 A MX 2010001064A MX 2010001064 A MX2010001064 A MX 2010001064A
- Authority
- MX
- Mexico
- Prior art keywords
- variables
- packing
- varyings
- linking
- scheme
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T15/00—3D [Three Dimensional] image rendering
- G06T15/005—General purpose rendering architectures
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Graphics (AREA)
- Image Generation (AREA)
- Devices For Executing Special Programs (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Complex Calculations (AREA)
Abstract
Un dispositivo inalámbrico que ejecuta un proceso de empaquetado de compilador de primer nivel y un proceso de empaquetamiento de hardware de segundo nivel en variables; el proceso de empaquetamiento de compilador empaqueta dos o más variables de sombreador (variables o atributos) cuya suma de componentes es igual a M en un registro de vector M-dimensional (MD) compartido; el empaquetamiento de hardware empaqueta consecutivamente M componentes de las variables de sombreador (variables o atributos) y cualesquiera variables restantes en una memoria caché de vértice u otro medio de almacenamiento.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/830,667 US8355028B2 (en) | 2007-07-30 | 2007-07-30 | Scheme for varying packing and linking in graphics systems |
PCT/US2008/071655 WO2009018385A2 (en) | 2007-07-30 | 2008-07-30 | Scheme for packing and linking of variables in graphics systems |
Publications (1)
Publication Number | Publication Date |
---|---|
MX2010001064A true MX2010001064A (es) | 2010-03-03 |
Family
ID=39940557
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MX2010001064A MX2010001064A (es) | 2007-07-30 | 2008-07-30 | Esquema para empaquetado y vinculacion de variables en sistemas graficos. |
Country Status (11)
Country | Link |
---|---|
US (1) | US8355028B2 (es) |
EP (1) | EP2023285B8 (es) |
JP (1) | JP5048836B2 (es) |
KR (1) | KR101118814B1 (es) |
CN (1) | CN101779219B (es) |
BR (1) | BRPI0813854B1 (es) |
CA (1) | CA2693344C (es) |
MX (1) | MX2010001064A (es) |
RU (1) | RU2448369C2 (es) |
TW (1) | TWI378355B (es) |
WO (1) | WO2009018385A2 (es) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9123151B2 (en) * | 2008-08-05 | 2015-09-01 | Autodesk, Inc. | Exchanging data between vertex shaders and fragment shaders on a graphics processing unit |
US8947444B1 (en) * | 2008-12-09 | 2015-02-03 | Nvidia Corporation | Distributed vertex attribute fetch |
GB201103698D0 (en) * | 2011-03-03 | 2011-04-20 | Advanced Risc Mach Ltd | Graphics processing |
GB201103699D0 (en) | 2011-03-03 | 2011-04-20 | Advanced Risc Mach Ltd | Graphic processing |
US9412193B2 (en) * | 2011-06-01 | 2016-08-09 | Apple Inc. | Run-time optimized shader program |
US9214008B2 (en) * | 2013-01-18 | 2015-12-15 | Nvidia Corporation | Shader program attribute storage |
US9395988B2 (en) * | 2013-03-08 | 2016-07-19 | Samsung Electronics Co., Ltd. | Micro-ops including packed source and destination fields |
US9633410B2 (en) | 2013-03-14 | 2017-04-25 | Intel Corporation | Compositor support for graphics functions |
US10096079B2 (en) | 2013-06-10 | 2018-10-09 | Sony Interactive Entertainment Inc. | Fragment shaders perform vertex shader computations |
US10134102B2 (en) | 2013-06-10 | 2018-11-20 | Sony Interactive Entertainment Inc. | Graphics processing hardware for using compute shaders as front end for vertex shaders |
US10176621B2 (en) | 2013-06-10 | 2019-01-08 | Sony Interactive Entertainment Inc. | Using compute shaders as front end for vertex shaders |
US10102603B2 (en) | 2013-06-10 | 2018-10-16 | Sony Interactive Entertainment Inc. | Scheme for compressing vertex shader output parameters |
US10332308B2 (en) | 2014-12-08 | 2019-06-25 | Intel Corporation | Graphic rendering quality improvements through automated data type precision control |
KR20160074154A (ko) | 2014-12-18 | 2016-06-28 | 삼성전자주식회사 | 컴파일러 |
US10460513B2 (en) * | 2016-09-22 | 2019-10-29 | Advanced Micro Devices, Inc. | Combined world-space pipeline shader stages |
KR20180038793A (ko) * | 2016-10-07 | 2018-04-17 | 삼성전자주식회사 | 영상 데이터 처리 방법 및 장치 |
CN108986014A (zh) * | 2018-07-19 | 2018-12-11 | 芯视图(常州)微电子有限公司 | 适用乱序顶点染色的图元装配单元 |
US11748839B2 (en) | 2020-04-16 | 2023-09-05 | Samsung Electronics Co., Ltd. | Efficient fast random access enabled geometry attribute compression mechanism |
US11508124B2 (en) | 2020-12-15 | 2022-11-22 | Advanced Micro Devices, Inc. | Throttling hull shaders based on tessellation factors in a graphics pipeline |
US11776085B2 (en) | 2020-12-16 | 2023-10-03 | Advanced Micro Devices, Inc. | Throttling shaders based on resource usage in a graphics pipeline |
US11710207B2 (en) | 2021-03-30 | 2023-07-25 | Advanced Micro Devices, Inc. | Wave throttling based on a parameter buffer |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB9413169D0 (en) | 1994-06-30 | 1994-08-24 | Thomson Consumer Electronics | Modulator data frame interfacing |
GB2317464A (en) * | 1996-09-23 | 1998-03-25 | Advanced Risc Mach Ltd | Register addressing in a data processing apparatus |
US5949421A (en) * | 1997-03-31 | 1999-09-07 | Cirrus Logic, Inc. | Method and system for efficient register sorting for three dimensional graphics |
CA2348771A1 (en) | 1999-09-01 | 2001-03-08 | Matsushita Electric Industrial Co., Ltd. | Copyrighted data processing method and apparatus |
RU2249245C2 (ru) | 1999-09-01 | 2005-03-27 | Мацусита Электрик Индастриал Ко., Лтд. | Способ и устройство для обработки данных с авторскими правами |
US6717577B1 (en) | 1999-10-28 | 2004-04-06 | Nintendo Co., Ltd. | Vertex cache for 3D computer graphics |
US6829696B1 (en) * | 1999-12-30 | 2004-12-07 | Texas Instruments Incorporated | Data processing system with register store/load utilizing data packing/unpacking |
US6900812B1 (en) * | 2000-08-02 | 2005-05-31 | Ati International Srl | Logic enhanced memory and method therefore |
US6828975B2 (en) * | 2001-03-01 | 2004-12-07 | Microsoft Corporation | Method and system for managing graphics objects in a graphics display system |
US7017154B2 (en) * | 2001-03-23 | 2006-03-21 | International Business Machines Corporation | Eliminating store/restores within hot function prolog/epilogs using volatile registers |
US6704026B2 (en) * | 2001-05-18 | 2004-03-09 | Sun Microsystems, Inc. | Graphics fragment merging for improving pixel write bandwidth |
DE10131254A1 (de) | 2001-07-01 | 2003-01-23 | Deutsche Post Ag | Verfahren zum Überprüfen der Gültigkeit von digitalen Freimachungsvermerken |
US6831653B2 (en) * | 2001-07-31 | 2004-12-14 | Sun Microsystems, Inc. | Graphics pixel packing for improved fill rate performance |
US6847369B2 (en) * | 2002-01-30 | 2005-01-25 | Sun Microsystems, Inc. | Optimized packing of loose data in a graphics queue |
US7530062B2 (en) * | 2003-05-23 | 2009-05-05 | Microsoft Corporation | Optimizing compiler transforms for a high level shader language |
US7746347B1 (en) * | 2004-07-02 | 2010-06-29 | Nvidia Corporation | Methods and systems for processing a geometry shader program developed in a high-level shading language |
US7681187B2 (en) * | 2005-03-31 | 2010-03-16 | Nvidia Corporation | Method and apparatus for register allocation in presence of hardware constraints |
US20080094408A1 (en) * | 2006-10-24 | 2008-04-24 | Xiaoqin Yin | System and Method for Geometry Graphics Processing |
-
2007
- 2007-07-30 US US11/830,667 patent/US8355028B2/en active Active
-
2008
- 2008-03-31 EP EP08006444.7A patent/EP2023285B8/en active Active
- 2008-07-29 TW TW097128649A patent/TWI378355B/zh not_active IP Right Cessation
- 2008-07-30 RU RU2010107218/08A patent/RU2448369C2/ru not_active IP Right Cessation
- 2008-07-30 BR BRPI0813854A patent/BRPI0813854B1/pt active IP Right Grant
- 2008-07-30 CN CN2008801009326A patent/CN101779219B/zh active Active
- 2008-07-30 WO PCT/US2008/071655 patent/WO2009018385A2/en active Application Filing
- 2008-07-30 CA CA2693344A patent/CA2693344C/en not_active Expired - Fee Related
- 2008-07-30 KR KR1020107004551A patent/KR101118814B1/ko active IP Right Grant
- 2008-07-30 JP JP2010520164A patent/JP5048836B2/ja not_active Expired - Fee Related
- 2008-07-30 MX MX2010001064A patent/MX2010001064A/es unknown
Also Published As
Publication number | Publication date |
---|---|
EP2023285B1 (en) | 2017-12-20 |
RU2448369C2 (ru) | 2012-04-20 |
WO2009018385A3 (en) | 2009-03-26 |
BRPI0813854B1 (pt) | 2020-01-14 |
KR20100038462A (ko) | 2010-04-14 |
EP2023285A1 (en) | 2009-02-11 |
WO2009018385A2 (en) | 2009-02-05 |
US20090033672A1 (en) | 2009-02-05 |
TWI378355B (en) | 2012-12-01 |
CA2693344C (en) | 2017-01-17 |
KR101118814B1 (ko) | 2012-03-20 |
RU2010107218A (ru) | 2011-09-10 |
CN101779219B (zh) | 2013-03-27 |
EP2023285B8 (en) | 2018-06-27 |
TW200910110A (en) | 2009-03-01 |
JP2010535393A (ja) | 2010-11-18 |
CN101779219A (zh) | 2010-07-14 |
BRPI0813854A2 (pt) | 2019-02-12 |
US8355028B2 (en) | 2013-01-15 |
JP5048836B2 (ja) | 2012-10-17 |
CA2693344A1 (en) | 2009-02-05 |
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Legal Events
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HH | Correction or change in general |