MX2009007939A - Uso de sistema de renombramiento de registros para enviar en avance los resultados intermedios entre las instrucciones constituyentes de una instruccion expandida. - Google Patents

Uso de sistema de renombramiento de registros para enviar en avance los resultados intermedios entre las instrucciones constituyentes de una instruccion expandida.

Info

Publication number
MX2009007939A
MX2009007939A MX2009007939A MX2009007939A MX2009007939A MX 2009007939 A MX2009007939 A MX 2009007939A MX 2009007939 A MX2009007939 A MX 2009007939A MX 2009007939 A MX2009007939 A MX 2009007939A MX 2009007939 A MX2009007939 A MX 2009007939A
Authority
MX
Mexico
Prior art keywords
constituent
intermediate results
instruction
register renaming
instructions
Prior art date
Application number
MX2009007939A
Other languages
English (en)
Inventor
James Norris Dieffenderfer
Thomas Andrew Sartorius
Rodney Wayne Smith
Michael Scott Mcilvaine
Nathan Samuel Nunamaker
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of MX2009007939A publication Critical patent/MX2009007939A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Organic Low-Molecular-Weight Compounds And Preparation Thereof (AREA)
  • Electrotherapy Devices (AREA)

Abstract

Los resultados intermedios se pasan entre las instrucciones constituyentes de una instrucción expandida utilizando recursos de renombramiento de registros y lógica de control. Una primera instrucción constituyente genera resultados intermedios y se le asigna un PRN en una tabla de renombramiento de instrucciones constituyentes, y escribe los resultados intermedios en el registro físico identificado. Una segunda instrucción constituyente realiza una consulta en la tabla de renombramiento de instrucciones constituyentes y lee los resultados intermedios del registro físico. La lógica de renombramiento de instrucciones constituyentes rastrea las instrucciones constituyentes en todo el trayecto de datos, y elimina el registro de la tabla de renornbramiento de instrucciones constituyentes y regresa el PRN a una lista libre cuando la segunda instrucción constituyente ha leído los resultados intermedios.
MX2009007939A 2007-01-24 2008-01-24 Uso de sistema de renombramiento de registros para enviar en avance los resultados intermedios entre las instrucciones constituyentes de una instruccion expandida. MX2009007939A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/626,424 US7669039B2 (en) 2007-01-24 2007-01-24 Use of register renaming system for forwarding intermediate results between constituent instructions of an expanded instruction
PCT/US2008/051958 WO2008092037A1 (en) 2007-01-24 2008-01-24 Use of register renaming system for forwarding intermediate results between constituent instructions of an expanded instruction

Publications (1)

Publication Number Publication Date
MX2009007939A true MX2009007939A (es) 2009-08-07

Family

ID=39323615

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2009007939A MX2009007939A (es) 2007-01-24 2008-01-24 Uso de sistema de renombramiento de registros para enviar en avance los resultados intermedios entre las instrucciones constituyentes de una instruccion expandida.

Country Status (13)

Country Link
US (1) US7669039B2 (es)
EP (1) EP2126689B8 (es)
JP (1) JP5275253B2 (es)
KR (1) KR101154628B1 (es)
CN (1) CN101601008B (es)
AT (1) ATE481676T1 (es)
BR (1) BRPI0806737B1 (es)
CA (1) CA2674872C (es)
DE (1) DE602008002568D1 (es)
ES (1) ES2352586T3 (es)
MX (1) MX2009007939A (es)
RU (1) RU2431887C2 (es)
WO (1) WO2008092037A1 (es)

Families Citing this family (9)

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Publication number Priority date Publication date Assignee Title
US9697002B2 (en) 2011-10-03 2017-07-04 International Business Machines Corporation Computer instructions for activating and deactivating operands
US9690583B2 (en) 2011-10-03 2017-06-27 International Business Machines Corporation Exploiting an architected list-use operand indication in a computer system operand resource pool
US9513915B2 (en) * 2012-03-28 2016-12-06 International Business Machines Corporation Instruction merging optimization
US9395988B2 (en) * 2013-03-08 2016-07-19 Samsung Electronics Co., Ltd. Micro-ops including packed source and destination fields
US10565670B2 (en) 2016-09-30 2020-02-18 Intel Corporation Graphics processor register renaming mechanism
CN111506347B (zh) * 2020-03-27 2023-05-26 上海赛昉科技有限公司 一种基于指令写后读相关假设的重命名的方法
CN112416434B (zh) * 2020-12-03 2023-02-17 海光信息技术股份有限公司 物理寄存器分配方法、物理寄存器分配装置和电子设备
CN114168197B (zh) * 2021-12-09 2023-05-23 海光信息技术股份有限公司 指令执行方法、处理器以及电子装置
CN116662006B (zh) * 2023-06-06 2024-02-23 北京市合芯数字科技有限公司 多线程处理器重命名资源管理方法、系统、装置及介质

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5627985A (en) * 1994-01-04 1997-05-06 Intel Corporation Speculative and committed resource files in an out-of-order processor
US5586278A (en) * 1994-03-01 1996-12-17 Intel Corporation Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor
US5771366A (en) * 1995-06-09 1998-06-23 International Business Machines Corporation Method and system for interchanging operands during complex instruction execution in a data processing system
US5758117A (en) * 1995-12-14 1998-05-26 International Business Machines Corporation Method and system for efficiently utilizing rename buffers to reduce dispatch unit stalls in a superscalar processor
US6279102B1 (en) * 1997-12-31 2001-08-21 Intel Corporation Method and apparatus employing a single table for renaming more than one class of register
US6212619B1 (en) * 1998-05-11 2001-04-03 International Business Machines Corporation System and method for high-speed register renaming by counting
US7055021B2 (en) * 2002-02-05 2006-05-30 Sun Microsystems, Inc. Out-of-order processor that reduces mis-speculation using a replay scoreboard
US7185182B2 (en) * 2003-02-04 2007-02-27 Via Technologies, Inc. Pipelined microprocessor, apparatus, and method for generating early instruction results
US7219218B2 (en) * 2003-03-31 2007-05-15 Sun Microsystems, Inc. Vector technique for addressing helper instruction groups associated with complex instructions
JP3752493B2 (ja) * 2003-03-31 2006-03-08 東芝マイクロエレクトロニクス株式会社 レジスタ・リネーミング機能を有するプロセッサ
US7373486B2 (en) * 2005-08-29 2008-05-13 P.A. Semi, Inc. Partially decoded register renamer

Also Published As

Publication number Publication date
ATE481676T1 (de) 2010-10-15
EP2126689A1 (en) 2009-12-02
ES2352586T3 (es) 2011-02-21
KR20090100448A (ko) 2009-09-23
WO2008092037A1 (en) 2008-07-31
CA2674872C (en) 2013-06-25
CA2674872A1 (en) 2008-07-31
EP2126689B1 (en) 2010-09-15
BRPI0806737A8 (pt) 2018-04-10
JP2010517180A (ja) 2010-05-20
RU2431887C2 (ru) 2011-10-20
RU2009131714A (ru) 2011-02-27
DE602008002568D1 (de) 2010-10-28
CN101601008B (zh) 2013-05-08
BRPI0806737B1 (pt) 2023-11-28
EP2126689B8 (en) 2010-12-29
JP5275253B2 (ja) 2013-08-28
KR101154628B1 (ko) 2012-06-08
US20080177987A1 (en) 2008-07-24
CN101601008A (zh) 2009-12-09
US7669039B2 (en) 2010-02-23
BRPI0806737A2 (pt) 2011-09-13

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