MX2008009316A - Efficient memory hierarchy management - Google Patents

Abstract

In a processor, there are situations where instructions and some parts of a program may reside in a data cache prior to execution of the program. Hardware and software techniques are provided for fetching an instruction in the data cache after having a miss in an instruction cache to improve the processor's performance. If an instruction is not present in the instruction cache, an instruction fetch address is sent as a data fetch address to the data cache. If there isvalid data present in the data cache at the supplied instruction fetch address, the data actually is an instruction and the data cache entry is fetched and supplied as an instruction to the processor complex. An additional bit may be included in an instruction page table to indicate on a miss in the instruction cache that the data cache should be checked for the instruction.

Description

ADMINISTRATION OF EFFICIENT MEMORY HIERARCHY FIELD OF THE INVENTION The present disclosure generally relates to techniques for finding instructions from a memory having an instruction cache and a data cache and, more specifically, to an improved approach for searching for an instruction after a fault. in the instruction cache looking for the instruction directly from the data cache if the instruction resides there.

BACKGROUND OF THE INVENTION Commonly portable products, such as cell phones, laptops, personal data assistants (PDA) or similar, require the use of a processor that executes programs, such as communication and multimedia programs. The processing system for these products includes a processor and complex memory to store instructions and data. For example, instructions and data may be stored in a hierarchical memory consisting of multiple levels of caches, including, for example, an instruction cache, a data cache, and a system memory. The use of a separate instruction cache and a separate data cache is known as a Harvard architecture. Because the Harvard architecture isolates the instruction cache from the data cache, problems arise when the instructions are stored in the data cache. In a general system processing with a Harvard architecture, there are situations that arise, in which instructions can be stored in the data cache. For example, if a program is encrypted or in a compressed form, it must be decrypted / decompressed prior to enabling the program to be run. The decryption / decompression process treats the encrypted / compressed program as data in order to process it and stores the decrypted / decompressed instructions as data in a data cache, for example, a level 1 data cache, on its route to the system memory. The generation of instructions from Java byte codes is another situation where the instructions are initially treated as data that is stored using the data path, including the data cache, to the system memory. The initial state of a program in which the program instructions are being treated as data, creates a coherence problem within the memory hierarchy, because at least some parts of a program can reside in the data cache prior to the execution of the program. In order to solve the coherence problem, a software approach is typically taken where the program or program segments in the data cache are moved to the system memory under the control of the program, the instruction cache is typically invalidated to clean the cache memory of any segments of old programs, and the instructions that comprise the program are then searched from the system memory. The movement of the instructions from the data cache to the system memory and the search of the instructions from the pre-execution system memory can take several cycles, reducing the performance of the processor due to the overload of the time of processing that must occur to access the instructions that initially reside in the data cache before the program shifts in the processor.

SUMMARY OF THE INVENTION Among its various aspects, the present disclosure recognizes that the overload of having to deal with instructions in a database may be the fact of limiting processor performance and possibly limiting the quality of the service that can be achieved. The present disclosure also recognizes that it may be desirable to have access to instructions that are residing in a data cache. further, the present disclosure describes an apparatus, methods and a computer-readable medium for directly searching for an instruction from a data cache when that instruction was not found in the instruction cache, an instruction cache fault, and it is determined that the instruction is in the data cache. By looking for the instruction directly in the data cache, after an instruction cache failure, the performance of the processor can be improved. For such purposes, one embodiment of the present invention includes a method for finding an instruction in a data cache that is separated from an instruction cache. In said method, it is determined that a search attempt failed in the instruction cache for the instruction in an instruction search address. The instruction search address is transformed into a data search address. In addition, an attempt is made to search the data cache for the instruction in the transformed data search address. Another embodiment of the invention focuses on a processor complex for searching instructions. The processor complex may conveniently include an instruction cache, a data cache, and a first selector. The first selector is used to select an instruction search address or a data search address. The selected search address is applied to a data cache, where instructions or data can be selectively searched from the data cache. A more complex understanding of the present inventive concepts discussed herein, as well as other features, will be apparent from the following detailed description and the appended figures.

BRIEF DESCRIPTION OF THE FIGURES Figure 1 is a block diagram of an exemplary wireless communication system in which a modality of the description can be employed; Figure 2 is a functional block diagram of a processor and memory complex in which the operation of the data cache is adapted for efficient instructions search memory operations according to an embodiment of the present invention; Figure 3 is a flow chart of an exemplary method for searching an instruction stored in a data cache, in order to reduce the overhead of handling failure associated with the instruction initially stored as data in the data cache according to with the present description; Fig. 4 is a functional block diagram of a processor and memory complex which includes an instruction location frame wherein the operation of the data cache is adapted for efficient instruction search in accordance with the present disclosure; Fig. 5 is a flowchart of an exemplary method for searching an instruction stored in a data cache according to the present disclosure; and Figure 6 is a flowchart of an exemplary method for executing a code that is generated as data and that is stored in a data cache according to the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION The inventive aspects of the present description will be illustrated more fully with reference to the appended figures, wherein various embodiments of the description are shown. However, the embodiment of this invention can be exemplified in various forms and should not be construed as limited to the modalities stipulated herein. Rather, these embodiments are provided so that this description will be complete and complete, and will convey the scope of the description to those skilled in the art. It will be appreciated that the present description can be exemplified as methods, systems or computer program products. Accordingly, the present inventive concepts described herein may take the form of a hardware mode, a software mode or a mode combining software and hardware aspects. In addition, the present inventive concepts described herein may assume the form of a computer program product in a computer-usable storage medium having a computer-usable program code exemplified in the medium. Any convenient computer-readable media can be used including hard disks, CD-ROMs, optical storage devices, fast memories, or magnetic storage devices. The computer program code, which can be compiled, assembled, and loaded into a processor can initially be written in a programming language such as C, C ++, Native Assembler, JAVA®, Smalltalk, JavaScript®, Visual Basic® , TSQL, Perl, or in various programming languages according to the teachings of the present disclosure. The program code or computer readable medium refers to a machine language code such as an object code whose format is understandable by a processor. The software modalities of the description do not depend on their execution with a particular programming language. When the program code is executed, a new task is created which defines the operating environment for the program code. Figure 1 shows an exemplary wireless communication system 100 where a description mode can be employed. For purposes of illustration, Figure 1 shows three remote units 120, 130 and 150 and two base stations 140. It will be recognized that typical wireless communication systems may have remote units and base stations. Remote units 120, 130 and 150 include hardware components, software components, or both, as represented by components 125A, 125C and 125B, respectively, which have been adapted to incorporate the description as discussed below. Figure 1 shows forward link signals 180 of the base stations 140 to the remote units 120, 130 and 150 and reverse link signals 190 of the remote units 120, 130 and 150 to the base stations 140. In Figure 1, the remote unit 120 is shown as a mobile telephone, the remote unit 130 is shown as a portable computer, and the remote unit 150 is displayed as a remote unit of fixed location in a wireless local loop system. For example, the remote units may be cellular telephones, manual units of personal communication systems (PCS), portable data units such as personal data assistants, or fixed location data units such as meter reading equipment. Although Figure 1 illustrates remote units according to the teachings of the description, the description is not limited to these exemplary illustrated units. The description can conveniently be employed in any device having a processor with an instruction cache, a data cache and a system memory. Fig. 2 is a functional block diagram of a processor and memory complex 200 wherein the operation of the normal data cache is adapted for a more efficient instruction search as described in more detail here. The processor and memory complex 200 includes a processor 202, an instruction cache level 1 (Ll) 204, an instruction cache control unit Ll 206, a data cache Ll 208, a memory control unit data cache Ll 210, a control section 211, and a system memory 212. The instruction cache control unit Ll 206 may include an addressable memory of instruction content for the instruction tag comparison, such as could use in an established associative cache. The control section 211 includes multiplexing elements 220, 226 and 234, switching devices 232 and 238, and an inverter 240. Peripheral devices, which can be connected to the processor complex, are not shown for clarity of analysis of the present description. The processor and memory complex 200 can conveniently be used in the components 125A-C to execute the program code that is stored in the system memory 212. In order to search for an instruction in the processor and memory complex 200, the processor 202 generates an instruction search address (IA) 214 of the desired instruction and sends the instruction search address to the instruction cache control unit Ll 206. The instruction cache control unit Ll 206 check whether the instruction is present in the instruction cache Ll 204. This revision is performed, for example, through the use of an internal content addressable memory (CAM) in an associative search of a match with the search address of instructions supplied. When the instruction is present, a match occurs and the instruction cache control unit Ll 206 indicates that the instruction is present in the instruction cache 204. If the instruction is not present, a match in a search will not be found. CAM associative and the instruction cache control unit Ll 206 indicates that the instruction is not present in the instruction cache 204. If the instruction is present, the instruction in the instruction search address is selected from the instruction cache 204. The instruction is then sent on an instruction output link 216 through the multiplex element 226 to the processor 202. If the instruction is not present in the instruction cache, an instruction cache fault signal (I $ M = 1) is set as active indicating that a fault has occurred. Upon detecting a failure in the instruction cache memory, the processor and memory complex 200 attempts to search for the desired instruction from the data cache Ll 208. For this purpose, the multiplex element 220 is enabled by the signal (I $ M = 1) 218 for selecting the instruction search address 214. The instruction search address 214 then passes through a multiplex element 220 on a D-direction link 222 and is sent to the control unit of data cache Ll 210 as a data search address. It is appreciated that the processor and memory complex 200 represents a logical view of the system because, for example, the application of the instruction search address 214 on the D-address link 222 may require arbitration or a waiting period before it is can access the link Direction 222. The approach taken to multiplex the instruction search address 214 with the data address generated by processor 223 can be modified and depends on the particular focus taken on the designs of the instruction cache and memory data cache. The data cache control unit Ll 210 checks whether there is a hit in the data cache Ll 208 in the supplied instruction search address, through an internal associative search, for example, in the search address of Instruction supplied. A success indicates that there is data present in the search address of the instruction supplied. This data is actually an instruction and the data cache entry is searched from the data cache Ll 208 and placed on the data output link 224. In order to supply the searched data from the data cache of the data cache. data Ll 208 as an instruction for the processor, a multiplex element 226 can be conveniently employed. The data output link 224 is selected by multiplexing the element 226 by placing the sought-after data from the data cache on the instruction link 228 of the processor, when there is a fault in the instruction cache followed by a hit in the data cache in the instruction search direction. The occurrence of the fault in the instruction cache, indicated by the failure signal (I $ M = 1) 218 that is set as very active, followed by the success in the data cache in the same search address instructions, indicated by the hit signal (D $ H = 1) 230 that is set as very active, is represented logically by the AND gate 232. The output of the AND gate 232 is the selection signal 233 for the element multiplexing element 226. The instruction found in the data cache is also multiplexed for loading into the instruction cache 204 by the multiplex element 234 using the selection signal 233 logically provided by the AND gate 232. Although the link data output 224 is resending the instruction to the processor, the read data input 236 of the processor is deactivated by the AND gate 238 using the inverter 240 to provide an inverse of the selection signal 2 33. If it was determined that there was a failure in the data cache in the supplied instruction search address, the instruction is not in the data cache and the instruction is searched from system memory 212. The signal success (D $ H1 = 1) 230 is also sent to the instruction cache control unit Ll 206 to indicate, through its inactive state, that a failure occurred in the attempt to locate the instruction in the cache 208. Note that other means of signaling can be used to indicate that a failure occurred in the attempt to locate the instruction in the data cache 208. Because the instruction is not in the instruction cache 204 and not is in the data cache 208, this should be searched in the system memory 212. Once the instruction is obtained from the memory of the system 212, it is sent to the processor 202. Note that the paths from the system memory to supply an instruction due to a fault in the instruction cache or data cache and in order to supply data due to a failure in the data cache are not shown in order to clearly illustrate the present description. Figure 3 is an exemplary flowchart of a method 300 for directly searching for an instruction in a data cache after having an instruction cache failure, in order to minimize the overload commonly associated with the handling of data. the instruction initially stored as data in the data cache. Exemplary relationships between the steps of Figure 3 and the elements of Figure 2 are indicated by the description of the manner in which the elements of the processor and memory complex 200 can co-operate in a convenient manner to execute the steps of method 300. A In order to search for an instruction, an instruction search address is generated in step 304. For example, a processor, such as processor 202, generates an instruction search address of the desired instruction and sends the instruction search address 214 to the instruction cache controller Ll 206. In step 308, it is determined whether there is a hit or an instruction cache fault. For example, the instruction cache controller Ll 206 checks to see if the instruction is present in the instruction cache 204. If the instruction is present, its presence is indicated as a hit. If the instruction is present, the method 300 proceeds to step 312 and the instruction in the instruction search direction is selected. In step 316, the instruction is sent to the processor. For example, the selected instruction is placed on the instruction output link 216 and sent to the processor 202 through the multiplex element 226. If the instruction is not present in the instruction cache as determined in step 308, an indication is provided that a failure has occurred and an attempt is made to search for the instruction from the data cache in step 320. For example, the instruction search address 214 is sent through the data element. multiplexing 220 as a data search address 222 to the data cache 208. In step 324, a review is performed, for example, by the data cache controller Ll 210 to see if there are valid data present in the data cache. Instruction search address supplied. If there is valid data present in the data cache in the supplied instruction search address, the data is actually an instruction and the data cache entry is searched in step 328. In step 316, the data searched from the data cache are sent as an instruction to the processor. For example, the data searched on the data output link 224 from the data cache 208 is sent through the multiplex element 226 and supplied as an instruction to the processor 202 on the instruction link 228. In step 334, if there was an error in the data cache in the supplied instruction search address, the instruction is not in the data cache and in step 332 the instruction is searched from the system memory. For example, the hit signal of the data cache D $ H = 1 230 is sent to the instruction cache control unit Ll 206 to indicate through its inactive state that a failure occurred in the attempt to locate the instruction in the data cache 208. Because the instruction is not in the instruction cache 204 and not in the data cache 208, this must be sought from the memory of the system 212. Once the instruction is obtained from the memory of the system 212, the instruction is sent to the processor 202, as indicated in step 316. Figure 4 is a functional block diagram of a processor and memory complex 400 which includes an instruction location table wherein the operation of the normal data cache is adapted for the efficient operation of the instruction search according to the present description. The processor and memory complex 400 includes a processor 402, a level 1 instruction cache (Ll) 404, an instruction memory management unit (IMMU) and cache control (I MU / $ Control) 406, a data cache Ll 408, a data memory management unit (DMMU) and cache control (DMMU / $ Control) 410, a control section 411, and a memory hierarchy 412. The I MU / $ Control 406 may include, for example, a virtual-to-physical instruction address translation process. The control section 411 includes multiplexing elements 432, 438 and 448, switching devices 428, 444 and 452, and an inverter 454. Peripheral devices, which can be connected to the processor complex, are not shown for clarity of analysis of the present description. The processor and memory complex 400 can be conveniently employed in the components 125A-C to execute the program code that is stored in the system memory 412. The instruction cache can utilize a forward translation buffer (TLB) ) that contains an instruction location table in order to improve the performance of the instruction cache. The instruction location table has, for example, a list of physical location numbers associated with virtual location numbers and additional information associated with each location number entry. An instruction location table entry is created when a memory location in the range of the instruction address is loaded into the instruction cache or data cache. The loading of a memory location can occur under the supervision of an operating system (OS). In operation, the instruction location table is examined for a match with a virtual location number supplied to the TLB. Although a TLB having an instruction location table as part of the instruction MU and the cache control 406 is described herein, it will be recognized that alternative approaches may be used. In order to search for an instruction in the processor and memory complex 400, the processor 402 generates an instruction search address (IA) 414 for the desired instruction and sends the instruction search address to the IMMU / $ Control 406. An entry appropriate in an instruction location table, such as the location table 416 located in the IMMU / $ Control 406, is selected based on a supplied location number that is part of the AI 414. The instruction address based on the entry of the selected location table is combined with a location address, also part of the? 414, generating an instruction address (GA) 418 that is applied internally to the instruction cache Ll 404. The selected input of the location table 416 includes additional information stored with the input. One of the additional bits of information that can be stored with each location table entry is a revision data cache attribute, labeled as D bit 420. The D bit is set to "1" when the entry in the table The location of instructions is created due to the loading of an instruction location in the data cache or when instructions are generated that are stored in a location in the data cache during processing. The D bit is usually set by the operating system (OS) to indicate that the contents of a location can be used both as data and instructions. In an exemplary scenario, a program, which generates data which will be used as instructions, uses the OS to request that the appropriate locations be marked by setting the D bit in the entries of the associated location table. In another scenario, a program can also request OS locations that are already established with the D bit set. The D bit does not necessarily need to be explicitly deleted. If a program specifies that the data cache may contain instructions causing the appropriate D bit or D bits to be set, then that specification may be valid during the life of the program. The D bit or the D bits can then be removed later when the location table is used for a different process. The IMMU / $ Control 406 checks to see if the instruction is present in the instruction cache 404. If the instruction is present, this presence is indicated as a hit. If the instruction is present, the instruction in the instruction search address is selected from the instruction cache 404. The instruction is then sent on the instruction output link 422 through the multiplex element 438 to the processor 402 If the instruction is not present, an indication is provided by IMMU / $ Control 406 that a fault has occurred and an instruction cache fault signal (I $ M = 1) 424 is set to active indicating that it has a failure occurred. Upon detecting a failure in the instruction cache in conjunction with the selected D bit set to "1", the processor and memory complex 400 attempts to search for the desired instruction from the data cache Ll 408. This attempt it can be achieved conveniently, for example, by using the selected D bit in a switching function. The D bit 420 of the selected location table entry is output as the signal of the D bit 426. The signals of the D bit 426 are, for example, set in AND, by the AND gate 428, with the fault indication (I $ M = 1) 424. The output 430 of the AND gate 428 is then used by the mutliplexion element 432 to select the generated instruction address (GA) 418 or a data address 433 of the processor 402. When selected, the GA 418 passes through the multiplex element 432 in the D-direction link (DA) 434 and is sent to the data MU and the cache control 410 to determine whether the instruction resides in the data cache 408 in the address search for data. It is noted that the processor and memory complex 400 represents a logical view of the system, because, for example, the application of the instruction address generated 418 on the D-address link 434 may require arbitration or a waiting period before it is can access the link Direction 434. The approach taken to multiplex the generated instruction address 418 with the data address generated by the processor 433 can be modified and depends on the particular approach taken in the instructions cache designs and the data cache. The data cache then checks to see if valid data is present in the supplied instruction search address. If there is valid data present in the supplied instruction search address, the data is actually an instruction and the data cache entry is searched from the data cache Ll 408 and placed on the output link of the data cache. data 436. In order to supply the data cache entry as an instruction to the processor, a multiplex element 438 is used, for example. The multiplex element 438 is enabled to pass the data output link 436 on the instruction link 440 of the processor, where there is a fault in the instruction cache and the selected D bit is set to "1" followed by a hit the data cache in the instruction search address. The occurrence of instruction cache failure, indicated by the fault signal (I $ M = 1) 424 very active, and the signal D bit 426 set to "1", followed by the success in the data cache in the generated instruction address, indicated by the hit signal (D $ H = 1) 442 very active, it is logically represented by the AND gate 44. The output of the AND gate 444 is the selection signal 446 for the multiplex element 438. The instruction on the output link The data link is also multiplexed for loading into the instruction cache by the multiplexing element 448 using the selection signal 446. Although the data output link of the data cache Ll 436 is forwarded the instruction to the processor 402, the data output link 436 is turned off for transfers to the read data input 450 of the processor by the AND gate 452 using an inverse of the selection signal 446 provided by the inverter 454. If it was determined that there was a fault and n the data cache in the supplied instruction search address, the instruction is not in the data cache and the instruction is searched from the system memory 412. The hit signal (D $ H = 1) 442 is also sent to the IM U / $ Control 406 to indicate through its active state that a failure occurred in the attempt to locate the instruction in the data cache 408. Once the instruction is obtained from the system memory 412, this is sent to processor 402. Note that the paths from the memory hierarchy are not shown to provide an instruction because of a fault in the instruction cache or data cache memory and to supply data due to A failure in the data cache, can be employed any of a wide variety of connection approaches that is consistent with the application and the processor employed. Fig. 5 is an exemplary flow chart of a method 500 for searching an instruction in a data cache after having an instruction cache failure and a revision data cache attribute indicates that the cache memory cache data should be reviewed for instruction. Exemplary relationships between the steps of Figure 5 and the elements of Figure 4 are indicated by reference to the exemplary elements from the processor and memory complex 400 which can be conveniently employed to carry out the steps of the 500 method of figure 5. In order to search for an instruction, in step 502 an instruction search address is generated for the desired instruction. For example, a processor, such as the processor 402 generates an instruction search address and sends the instruction search address 414 to the instruction cache controller Ll 406. The instruction search address may be a virtual address constituted by a number of locations 504 and a location address 506. In step 508, an appropriate entry in an instruction location table, such as the location instruction table 416, is selected based on the number of locations provided 504. The address generated based on the entry of the selected location table is combined in step 509 with location address 506 to produce an instruction cache address. The input selected from the instruction location table 416 includes the additional information stored with that entry. One of the additional bits of information that can be stored with each location table entry is a revision data cache attribute, such as the bit labeled as D bit 420. This attribute is selected in step 510.

In step 512, it is determined whether there is a hit or an instruction cache fault. For example, the instruction cache checks to see if the instruction is present. If the instruction is present, its presence is indicated as a success. If the instruction is present, the method 500 advances to step 514 and the instruction in the instruction search direction is selected. In step 516, the instruction is sent to the processor. For example, the selected instruction is placed on the instruction output link 422 and sent through the multiplex element 438 to the instruction link 440 of the processor 402. If the instruction is not present in the instruction cache as determined in step 512, an indication is given that a failure has occurred and method 500 proceeds to step 518. In step 518, the D bit that was selected in step 510 is checked to see if it is set to "1"indicating that the data cache should be reviewed for the instruction. If the D bit was set to "1", the processor attempts to search for the instruction from the data cache in step 520. For example, the generated instruction search address 418 is sent as a data search address 434 to the data cache. In step 524, the data cache checks whether valid data is present in the supplied instruction search address. If there is valid data present in the supplied instruction search address, the data is actually an instruction and the data cache entry is searched in step 528. In step 516, the data sought from the memory Data cache are sent as an instruction to the processor. For example, the data searched on the data output link 436 is sent through the multiplex element 438 and supplied as an instruction to the processor 402 on the instruction link 440. Returning to step 518, if in step 518 it is determined that the D bit was a "0", it is known that the instruction is not present in the data cache and the method 500 proceeds to step 522. Step 522 is also achieved for the situation where there was a cache failure of data in the supplied instruction search address, as determined in step 524. In any case, it is known that the instruction is not present in the instruction cache or in the data cache and the instruction is sought from the system memory, as indicated in step 522. For example, there will be access to the system memory 412 for the instruction. Once the instruction is obtained from the system memory 412, the instruction is sent to the processor 402, as indicated in step 516. Figure 6 is an exemplary flow chart of a method 600 for executing the code of the program that is generated as data and stored in the data cache. The program code following this method can be executed in a processor and memory complex having an instruction cache, a data cache, and a system memory, such as those that were analyzed in connection with FIGS. and 4, and can conveniently be used in components 125A-C of Figure 1. In step 602, a program generates a code. This generation can occur, for example, when a program generates an executable code from a compressed program. The generated code is initially treated as data and is stored in a data cache after it is generated. Prior to execution of the program, an instruction cache is invalidated in step 604. The invalidation step ensures that there are no instructions in the same address as the generated code. In step 606 the generated code is executed by the processor looking for instructions from the address space of the program in the instruction cache and may include instructions that are stored in the data cache. For those instructions stored in the data cache, the techniques of the present disclosure are followed by allowing the data cache to be checked for instructions in an occurrence of a failure in the instruction cache. When finding an instruction in the data cache, the instruction is directly searched from the data cache for execution in the processor. Although the present description has been analyzed in a currently preferred context, it will be recognized that the present teachings can be adapted to a variety of contexts consistent with this description and the following claims.

Claims (20)

NOVELTY OF THE INVENTION Having described the present invention, it is considered as a novelty and, therefore, the content of the following is claimed as a priority: CLAIMS

1. - A method for finding an instruction in a data cache that is separated from an instruction cache, the method comprising: determining that a search attempt failed in the instruction cache for the instruction in an instruction search address; transform the instruction search address into a data search address; and make an attempt to search the data cache for the instruction in the transformed data search address.

2. The method according to claim 1, further comprising: setting as an asset a revision data cache attribute when generating instructions that are stored as data in the data cache.

3. - The method according to claim 2, further comprising: determining whether a revision data cache attribute is active; and enable the search attempt in the data cache for the statement only if the revision data cache attribute is active.

4. The method according to claim 2, characterized in that the revision data cache attribute is a bit stored in an instruction location table.

5. - The method according to claim 1, characterized in that the step of transforming the instruction search address further comprises: multiplexing the instruction search address and a data search address; and selecting the address to search for instructions for application to the data cache as the transformed data search address, where the instruction search address is selected after determining that the instruction search attempt failed in the cache Instructions .

6. The method according to claim 1, characterized in that the step to perform a search attempt in the data cache further comprises: determining the instruction hit in the data cache; and look for the instruction from the data cache.

7. - The method according to the rei indication 1, also comprises: determining the search attempt in the data cache failed; and inform an instruction memory control that the attempt to search the data cache failed.

8. The method according to claim 7, further comprising: finding the instruction from a system memory.

9. A processor complex comprising: an instruction cache memory; a data cache; and a first selector for selecting an instruction search address or a data search address based on a selection signal, the selection signal causes the instruction search address or the data search address to be applied to the data cache where the instructions or data can be searched selectively from the data cache.

10. The processor complex according to claim 9, characterized in that the selection signal of the first selector selects the data search address in response to a data access operation.

11. The processor complex according to claim 9, characterized in that the selection signal of the first selector selects the instruction search address if an instruction failure signal indicates that a fault has occurred in an instruction search operation. in the instruction cache.

12. - The processor complex according to claim 9, further comprising: a second selector for selecting an instruction output link from the instruction cache or a data output link from the cache of data to be applied to a processor instruction binding input.

13. - The processor complex according to claim 12, characterized in that the second selector selects the data output link from the data cache if a failure occurred in the instruction cache and if a hit occurred in the data cache in the selected instruction search address. through the first selector.

14. - The processor complex according to claim 12, characterized in that the second selector selects the instruction output link if a hit in the instruction cache occurs.

15. - The processor complex according to claim 9, further comprising: a third selector to select a memory output link from a system memory or a data output link from the memory cache data to be applied to the instructions link entry of the instruction cache.

16. - The processor complex according to claim 15, characterized in that the third selector selects the data output link from the data cache if a failure occurred in the instruction cache and if a hit occurred in the the data cache in the instruction search direction selected through the first selector. 17.- A method to execute a program code, which comprises: generating instructions which are stored as data in a data cache; invalidate an instruction cache prior to executing the program code using the generated instructions; and search for an instruction directly from the data cache if the instruction is not found in the instruction cache, where the program code is executed. 18. The method according to claim 17, characterized in that the step of generating instructions includes the operation of loading instructions in the data cache. 19. The method according to claim 17, characterized in that the invalidation of the instruction cache further comprises: invalidating only a portion of the instruction cache where the generated instructions are stored. The method according to claim 17, further comprising: setting a revision data cache attribute in an instruction location table to indicate that an instruction can be in the data cache; and find the instruction from the data cache if the statement is not found in the instruction cache and the revision data cache attribute is active.