MX2008005519A - Circuit and method for subdividing a camram bank by controlling a virtual ground - Google Patents

Abstract

A CAM bank is functionally divided into two or more sub-banks, without replicating CAM driver circuits, by disabling all match line discharge circuits in the bank, and selectively enabling the discharge circuits in entries comprising sub-banks. At least one selectively actuated switching circuit is interposed between the virtual ground node of each discharging comparator in the discharge circuit of a sub-bank and circuit ground. When the switching circuit is in a non-conductive state, the virtual ground node is maintained at a voltage level sufficiently above circuit ground to preclude discharging a connected match line within the CAM access time. When the switching circuit is placed in a conductive state, the virtual ground node is pulled to circuit ground and the connected match line may be discharged by a miscompare. Control signals, which may be decoded from address bits, are distributed to the switching circuits to define the CAM sub-banks.

Description

CIRCUIT AND METHOD TO SUBDIVE A CAMRAM BANK WHEN CONTROLLING A VIRTUAL EARTH CONNECTION FIELD OF THE INVENTION The present invention relates generally to the field of digital electronics and in particular to a circuit and method for subdividing a bank of CAMR7AM by means of a virtual ground connection.

BACKGROUND OF THE INVENTION Microprocessors perform computational tasks in a wide variety of applications, including integrated applications such as portable electronic devices. The increasingly increasing feature and improved functionality of such devices requires even more powerful computational processors to provide additional software functionality. Another trend of portable electronic devices is an increasingly smaller form factor. A greater impact of this trend is the decreasing size of the batteries used to power the processor and other electronics in the device, making energy efficiency an increasingly important design consideration. Therefore, improvements in the processor that increase the speed of execution and reduce the power consumption are desirable for processors of portable electronic device in particular as well as processors in general. Most modern processors take advantage of the spatial and temporal status properties of most programs by storing recently executed instructions and newly accessed data in one or more caches for easy access by an instruction execution path. A cache memory is a memory structure, usually the chip, of high speed comprising a Dirigible Content Memory (CAM) and corresponding Random Access Memory (RAM), known as a CAMRAM. The instructions or data reside in a "line" cache stored in the RAM. To determine if a particular data resides in the RAM, a portion of its address is applied in the CAM. A CAM is a particular memory structure in which an applied comparison input (referred to herein as the key) is simultaneously compared to the data stored in each CAM input referred to herein as a key field), and the result of the CAM is an indication of which, if any, the key field matches the key. In a cache, the key and the key fields are portions of addresses (virtual or physical), and if a correlation is presented (that is, access "hits" in the cache), the location of the correlation indexes the RAM, and the corresponding cache line is accessed. The CAMRAM circuit can also be used in an Address Translation Intermediate Memory (TLB) for fast address translation. In this application, an applied virtual address is the key, previously translated virtual addresses are stored as key fields in the CAM, and the associated locations of the RAM store the corresponding physical addresses. CAMRAMs are also deployed in other applications, such as a memory board that queues write requests. In this case, the address of a read request may be a key, which searches against write addresses queued. A hit indicates more recent write data than those stored in memory, which must be used to service the read request to ensure consistency. In general, CAMRAMs are useful in a variety of applications. Figure 1 depicts a functional block diagram of a portion of an input of a CAM structure, indicated generally by the number 100. The CAM input j includes a correlation line 102 encompassing all bit positions of field 110 of key java. The correlation line 102 is raised above by a PRECARGE signal that turns on the gate of a pass transistor 104 that connects the correlation line 102 to the power. In each bit of the java CAM input, a discharge circuit 105 can selectively download the correlation line 102. Figure 1 depicts a functional block diagram of the discharge circuit 105, which includes a switching circuit 106 such as a pass transistor interposed between the correlation line 102 and the ground connection of the circuit. The gate of the discharge transistor 106 is the logic XOR 108 of a key bit 112 and the corresponding key field bit 110. At each bit position iav °, if the key bit 112 and the key field bit 110 match, the result of the gate 108 of XOR is low and the transistor 106 does not conduct load from the line 102 of correlation to connection to Earth. If the key bit 112 and the key field bit 110 do not match, the result of the XOR gate 108 is high, turning on the transistor 106 and lowering the correlation line 102. In this way, if any bit of the key 112 mismatches any corresponding bit of the key field 110, the correlation line 102 is lowered. Conversely, only if each bit of the key 112 and the key field 110 match, no path to the ground connection is established and the correlation line 102 remains high. A detection circuit 114 detects the level of the java correlation line 102 at a time determined by the download time of the correlation line 102 in the worst case. If each key field 110 is unique, which is the case in the normal cache memory and the TLB operation, then only one key field 110 must correlate the key 112. In this case, only one correlation line 102 within the CAM will remain elevated. To ensure that this is the case, the result of each detection circuit 114 of the correlation line goes to a collision detection circuit 116, which detects multiple correlations, and generates an error if they occur. A high-performance processor can include large caches, for example, that have 512 entries or more. Comparing a key 112 with the 512 entries presents several problems. The capacitive load due to the large extent, such as to distribute the key bits 112 to all CAM inputs 100 reduces the operating speed. Additionally, pre-charging and downloading at least 511 correlation lines 102 for each access consumes excess energy. To address these problems the CAMRAM of a large cache memory can be divided into banks, as shown in Figure 2 (representing four banks, although any number of banks can be implemented in any given application). A CAMRAM 120 comprises a plurality of CAM banks 122 and a corresponding plurality of RAM banks 124. In the case of a cache memory, banks can be selected by decoding predetermined address bits. Each CAM bank comprises a set of CAM excitation circuits 126 that temporarily store and distribute the signals to the CAM inputs 100 within the CAM bank 122. CAM driver circuits 126 may include "overload" circuits such as clock drivers, write drivers and control signals for memory cells 110 of the key field, detection amps and buffers for reading memory cells 110 of key field, and the like (not shown). A component of the CAM driver circuits 126, shown in Figure 2, are key drivers 127 for distributing the key bits 112 to the CAM inputs 100 within each CAM bank 122. In this example, the key exciters 127 comprise AND gates that gate the key bits 112 with a CAM clock signal. A CAM bank 122 may include, for example, 64 CAM entries 100. In general, higher performance and lower power consumption can be achieved by reducing the number of CAM inputs 100 by CAM blocks 122. However, this requires a large number of CAM banks 122, which duplicate the circuits 126 excitators of CAM, which waste silicon area. Thus, a means for functionally subdividing a CAM bank 122 to activate fewer CAM inputs 100 at a time, while not duplicating CAM driver circuits 126, may be advantageous.

SUMMARY OF THE INVENTION A CAM bank is functionally divided into two or more sub-banks, without duplicating the CAM exciter circuits, by disabling all the discharge circuits of the correlation line in the bank, and selectively enabling the discharge circuits in the entries that comprise the sub-banks. At least one selectively activated switching circuit is interposed between the virtual grounding node of each discharge comparator in the discharge circuit of a sub-bank and the ground connection of the circuit. When the switching circuit is in a non-conductive state, the virtual grounding node is maintained at a voltage level sufficiently above the ground connection of the circuit to avoid discharging a connected correlation line within the access time of the circuit. CAM. When the circuit is placed in a conductive state, the virtual grounding node is pulled toward the circuit grounding and the connected correlation line can be discharged by a poor comparison. The control signals that can be decoded from the address bits are distributed to the switching circuits to define the CAM sub-banks. One embodiment refers to a method for subdividing a CAM bank that includes driver circuits and a plurality of CAM inputs less than the number of inputs in the CAM. The discharge circuits connected to the correlation lines at each CAM input in the bank are disabled by raising a virtual ground connection of each discharge circuit over the ground connection of the circuit. A plurality of CAM inputs less than the number of inputs in the bank is selectively enabled by pulling the virtual ground connection of each discharge circuit at the selected inputs to the circuit ground connection. Another embodiment relates to a CAM placed in a bank, which includes CAM driver circuits and a plurality of CAM inputs. Each CAM input includes a plurality of download circuits. Each download circuit includes a memory cell that stores a key field bit. The CAM placed in a bank includes a memory cell that stores a key field bit, and a comparator connected with a CAM input correlation line and operative to compare a key bit applied with the key field bit in the memory cell, and also operative to download the correlation line to a virtual grounding node if the key bit and the key field bit are a bad comparison. The CAM placed in bank further includes two or more selectively activated switching circuits, each interposed between the virtual grounding node of one or more comparators and the ground connection of the circuit. Each switching circuit is operative in an open state to inhibit the discharge of one or more associated correlation lines by maintaining the virtual grounding node of the comparators connected at a voltage level above the circuit grounding, and operational in a closed state to allow the discharge of the correlation lines by pulling the virtual ground connection nodes to the circuit ground connection. Another embodiment relates to a processor, which includes an instruction execution unit and a memory controller. The processor also includes a bank-cache memory that includes a CAMRAM placed in a bank. Each CAM bank includes a plurality of CAM inputs and CAM driver circuits. At least one CAM bank is further functionally divided into a plurality of sub-banks, without duplication of the CAM driver circuits by disabling all the download circuits of the correlation line at each CAM input in the bank, and enabling selectively the download circuits of the correlation line in a plurality of CAM inputs less than the total number of CAM entries in the bank.

BRIEF DESCRIPTION OF THE FIGURES Figure 1 is a functional block diagram of a CAM input. Figure 2 is a block diagram of a CAMRAM placed on a bench. Figure 3 is a schematic representation of a discharge circuit of the CAM correlation line. Figure 4 is a functional block diagram of a processor. Figure 5 is a flow chart of a method for subdividing a CAM bank. Figure 6 is a schematic representation of a RAM cell having a reduced leakage current mode.

DETAILED DESCRIPTION OF THE INVENTION According to one or more modalities, a CAM bank 122 is subdivided into two or more sub-banks that share CAM circuits 126 exciters. All discharge circuits 105 in the CAM bank 122 are disabled by raising the grounding voltage level at which the circuit 105 is discharged from the circuit ground connection to a voltage level above the ground connection enough to avoid downloading the correlation lines 102. That high voltage level is referred to herein as a virtual ground connection. A selective plurality of the CAM inputs 100 in the CAM bank 122 can then be enabled by pulling the virtual ground connection of the discharge circuits 105 at the selected CAM inputs 100 to the circuit ground connection. The selected inputs are then operative, and form an effective sub-bank of CAM inputs 100. In this way, a CAM block 122 can be subdivided without duplicating CAM driver circuits 126. Representative discharge circuit 105 is shown schematically in FIG. 3, which generally corresponds to the dotted line discharge circuit 105 of FIG. 1, with the addition of two signals: write line signal 136 (L) and selection signal 134. of sub-bank. SRAM cell 110 maintains the iavo bit of the key field for the java CAM input. SRAM cell 110 is a conventional six transistor cell, which implements two transversely coupled inverters, with write enable gates for true and compliance bit values. New values for the true key field (KFT2 ^) and the complement key field (KFC ^ j) are written in the SRAM cell 110 when the write line 136 (WL) is high. The SRAM cell 110 produces the stored value of the true key field (KFT2) and the complement key field (KFC in the comparator 129 attached to the correlation line 102. The comparator 129 implements both functions of the XOR 108 logic. and the discharge switch 106 of Figure 1 (assuming at this point that the switching circuit 132 closes, or is in a conductive state.) Also connected to the comparator 129 are the iavo bit of the true key (KT2) and the key of compliance (KC2) Notice that the opposite direction of the key and the key field bits are connected at each end of the comparator 129. When the key and the key field bits agree, the true sense of a will correlate In this case, one of the transistors stacked at either end of the comparator 129 will be in a closed or conductive state, and the other will be in an open or nonconductive state, avoiding that the correlation line 102 is discharged to the ground connection of the circuit. On the other hand, in the case of a bad correlation between the key and the key field bits, the true sense of one agrees with the fulfillment of the other, and both transistors of an extremity of the comparator 129 will be closed, discharging the line 102 of correlation to the ground connection of the circuit. In one or more embodiments, a switching circuit 132 is interposed between a virtual grounding node (VGND) 130 of the comparators 129 in a sub-bank and ground connection of the circuit. The state of the switching circuit 132 is controlled by a sub-bank selection signal 134. In the modality represented, when the sub-bank selection signal 134 is high, the swing circuit 132 is in a closed or conductive state, and the comparator 129 operates as described above. However, when the sub-bank selection signal 134 is low, the swing circuit 132 is in an open or non-conductive state, and the comparator 129 sees a grounding voltage level of VGND at the node 130. VGND is isolated from the ground connection of the circuit by the swing circuit 132, and is at a voltage level of the correlation line 102 (pre-charged to the supply level) less than the voltage drop across the source for the resistance to the drain, in the conductive state, of two transistors. VGND is too high to download the correlation line 102 in the time frame of a CAM access cycle, and thus the corresponding CAM input 100 is effectively disabled. A CAM block 122 can be subdivided into sub-banks by decoding additional address bits to generate a plurality of sub-bank selection signals 134. Each sub-bank selection signal 134 is then routed to the swing circuits 134 of the CAM inputs 100 in the corresponding sub-bank. For example, when decoding two additional address bits, a CAM block 64 of 64 inputs can be subdivided into four sub-banks of 16 inputs when generating and distributing four sub-bank selection signals 134. When a given address activates one of the sub-banks, only sixteen key fields 110 need to be compared, and only sixteen correlation lines 102 placed in threshold to determine if one of them was not downloaded, indicating a correlation. Note that the four sub-banks continue to share the CAM exciter circuits 126 of the CAM block 122. A swing circuit 132, connected to the conductor 131, can control the voltage of the VGND node of a complete sub-bank, as shown in Figure 3. Alternatively, the correlation lines 102 of the sub-bank can be divided and connected to a plurality of swing circuits 132, as required in any given implementation for speed, load and the like. For example, each correlation line 102 or even each comparator 129 in a correlation line 102 can be connected to a separate swing circuit 132. Regardless of the number of swing circuits 132 required to selectively enable a sub-bank, the savings in the area of silicon and the energy consumption on duplicating the CAM driver circuits 126 is significant. Figure 4 depicts a functional block diagram of a representative processor. The processor 10 executes instructions in an instruction execution conduit 12 according to the control logic 14. The conduit includes several registers or insurances 16, organized in phases of conduits, and one or more Arithmetic Logical Units 18 (ALU). A General Purpose Register (GPR) file 20 provides records that comprise the upper level of a memory hierarchy. The conduit looks for instructions of an Instruction Cache Memory 21 (cache memory I), which includes a CAM 22 and a RAM 23. The addressing and the permissions of the instruction memory are handled by an Intermediate Memory 24 of Address Translation of the Instructional side (ITLB). The data is accessed from a Data Cache Memory 25, which includes a CAM 26 and RAM 27. Addressing and data memory permissions are handled by a main TLB 29. In various embodiments, the ITLB 24 may comprise a copy of the part of the TLB 29. Alternatively, the ITLB 24 and the TLB 29 may be integrated. In various embodiments of the processor 10, the cache memory 22 I and the cache memory 26 D may be integrated, or unified. Either or both of the 22 I cache memory and the 26 D cache memory can use CAMRAM circuits in a bank, where the CAM banks 122 can be subdivided by controlling the voltage level of the virtual ground connection 130 of the download circuits 105 of the correlation line. In this way, the cache memory 22 I and / or the cache memory 26 D provide improved performance and reduced power consumption, without the penalty of duplicating CAM driver circuits 126. Losses in the cache 22 I and / or the cache memory 26 D cause access to the main memory 32 (outside the chip), under the control of a memory interface 30. The processor 10 could include an input / output (I / O) interface 34, controlling access to various peripheral devices 36. Those of skill in the art will recognize that numerous variations of the processor 10 are possible. For example, the processor 10 may include a second level cache (L2) for either or both of the caches 21, 25 I, and D. In addition, one or more of the functional blocks represented in the processor 10 may be omitted in one. particular modality. A method for subdividing a CAM bank 122 is represented in the form of a flowchart in Figure 5. All discharge circuits 105 in memory bank 122 are disabled by raising the level of grounding voltage observed by the comparator. 129 in the discharge circuit 105 to a virtual ground connection 130 on the circuit grounding voltage level (block 40). This may comprise interposing a switching circuit 132 between the virtual grounding node 130, and the grounding of the circuit, and placing the switching circuit 132 in a non-conductive state. The elevation of the virtual grounding node 130 over the ground connection of the circuit prevents the discharge of a linked correlation line 102 in case of a poor comparison between the bits of the key 112 and the key field 110.

A portion of the CAM inputs 100 in the CAM bank 122 - i.e., a sub-bank - can be selectively enabled by pulling the virtual ground connection node 130 of the comparators 129 of the download circuits 105 at the inputs 100. of selected CAMs to the ground connection of the circuit (block 42). This may comprise placing the switching circuit 132 in a conductive state, pulling the virtual ground connection node 132 to the ground connection of the circuit and allowing a connected correlation line 102 to be discharged to the circuit ground connection when any bit 112 of key and bit 110 of key field in input 100 of CAM have a bad correlation. The sub-bank can be defined by decoding address bits in addition to the address bits that are decoded to define the CAM banks 122. This further improves performance by reducing the number of key field bits 110 in each CAM input 100. In one embodiment, the sub-bank selection signals that subdivide a CAM bank 120 may additionally be used to reduce the leakage current in the RAM banks 124 by diverting the RAM cells by source. Figure 6 represents a SRAM cell 50 with a virtual grounding node (VGND) 52 isolated from the ground connection of the circuit by a switching circuit 58, which may for example comprise a transistor. Otherwise, the RAM cell 50 is a conventional six transistor memory cell that implements a pair of transversely coupled inverters, as described above with respect to the CAM key field memory cell 110 (FIG. 3). ). Also interposed between the node VGND 52 and the ground connection of the circuit, in parallel with the switching circuit 58, there is a node 56. When the RAM cell 50 is read or written, node 52 of VGND is pulled to the circuit grounding by placing the switching circuit 54 in a conductive state by securing the sub-bank selection signal 134. When the corresponding CAM input 100 is in a non-selected CAM bank (and therefore, disabled), the sub-bank selection signal 134 is uninsured, and the VGND node 52 is isolated from the earth connection of the circuit. In this case, the diode 56 ensures that the node 52 of VGND is maintained at a predetermined level over the ground connection of the circuit, which for example may be in the range 200-300 mV. This ensures that the RAM cell 50 will retain its stored data value; however, currents in leakage in cell 50 of RAM are reduced, thus reducing the power consumption by the CAMRAM 120.

Figure 6 represents a simple diode 56 and the switching circuit 58 interposed between the node VGND 52 and the ground connection of the circuit for the entire RAM cell 50 in a sub-bank, connected by the conductor 54. In one implementation Given, a subset of RAM lines can be connected to ground and connected to separate diodes 56 and switching circuits 58. For example, each line of RAM or even each RAM cell 50 may be connected to a separate diode 56 to switching circuit 58. All the diodes 56 and switching circuits 58 are controlled by the sub-bank selection signal 134. When the corresponding CAM sub-bank is selected and the sub-bank selection signal 134 is secured, the switching circuit 58 is placed in a conductive state, pulling the node 52 of VGND towards the ground connection of the circuit. The 50 cell of RAM requires a certain transitory period to stabilize with its ground connection in the ground connection of the circuit. This may occur during the CAM access period, ie, during the time required to compare the key 112 and the bits of the key field 110 for each CAM input 100 in the selected sub-bank, downloading all except one line 102. of correlation (maximum), thresholding the correlation lines 102, performing collision detection, and indexing the RAM input associated with the correlation CAM input 100. In the case where the RAM cell 50 requires more time to stabilize than the access time of the CAM input 100, wait cycles can be inserted by the cache control circuits (which, for example, can reside in circuits 125 RAM exciters). This exchange of speed for reduced power consumption can be particularly attractive for processors deployed in portable electronic devices, where the efficient use of limited battery power is more important. With reference to Figure 3, in one embodiment, the deviation per source can be used with the memory cell 110 of the CAM key field to reduce the leakage currents. In this mode, instead of the ground connection of the memory cell 110, the VGND node is connected by line 60 to a diode 62 and a switching circuit 68, which is connected to the ground connection of the circuit. The CAM memory cell 110 operates as described in the above with respect to the RAM cell 50. By placing the switching circuit 58 in a non-conductive state, the leakage currents in the CAM memory cell 100 are reduced, this observes a high grounding voltage of the circuit grounding by the diode 56 (for example, 200-300 mV). The diode 62 and the switching circuit 64 are represented as being connected to a single memory cell 110 in Figure 3 for simplicity; in any given implementation, a simple diode 62 and switching circuit 64 may be connected by the conductor 60 to a plurality of, or all of the memory cells 110 in a CAM sub-bank. The state of the switching circuit 64 is controlled by a sub-bank preparation control signal 68. When the switching circuit 64 is placed in a conductive state, the CAM memory cell 110 requires some transient time to establish itself with its VGND node in the lateral connection of the circuit. The sub-bank preparation signal 68 may be the same as the sub-bank selection signal 134. In this case, the settling time of the memory cell 100 will reduce the operating speed of the CAMRAM 120. In one embodiment, the sub-bank preparation signal 68 which controls the state of the switching circuit 68 may be different from the sub-bank selection signal 134. For example, the memory cell 110 of the sub-bank may be prepared by pulling its VGND nodes towards the ground connection of the circuit before decoding an address, and therefore before generating a sub-bank selection signal, at predict the sub-bank that is selected (for example, by always preparing the memory cell 110 of the last selected sub-bank). In general, the source deviation of the CAM memory cells 110 of a sub-bank will have a performance penalty greater than the source deviation of the RAM cell 50, since the transient preparation time required to pull the node from VGND to the circuit ground connection for CAM memory cell 110 can not overlap CAM access time. However, the exchange of energy savings performance may be attractive in portable electronic device applications, where saving battery power is a primary design goal. Although the present invention has been described herein with respect to particular features, aspects and embodiments thereof, it will be apparent that numerous variations, modifications and other embodiments are possible with the broad scope of the present invention, and consequently, all the Variations, modifications and modalities will be construed as being within the scope of the invention. The present modalities therefore must be taken in all aspects as illustrative and not restrictive and all changes that come within the meaning and margin of equivalence of the appended claims are intended to be encompassed therein.

Claims (9)

1. NOVELTY OF THE INVENTION Having described the present invention, it is considered as a novelty and therefore the property described in the following claims is claimed as property.
2. CLAIMS 1. A method for subdividing a CAM bank including exciter circuits and a plurality of CAM inputs less than the number of inputs in the CAM, characterized in that it comprises: disabling the discharge circuits connected to the correlation lines in each input of CAM in the bank by raising a virtual ground connection of each discharge circuit over the ground connection of the circuit; and selectively enabling a plurality of CAM inputs less than the number of inputs in the bank by pulling the virtual ground connection of each discharge circuit at the selected inputs to the circuit ground connection. The method according to claim 1, characterized in that the virtual ground connection is raised to a voltage level high enough to prevent a discharge circuit from discharging a correlation line.
3. 3. The method according to claim 1, characterized in that selectively enabling a plurality of CAM inputs lower than the number of inputs in the bank by pulling the virtual ground connection of each discharge circuit at the selected inputs to the ground connection of the The circuit comprises selectively activating a switching circuit interposed between a virtual grounding node of each discharge circuit at the selected inputs and the ground connection of the circuit. The method according to claim 3, characterized in that selectively activating the switching circuit comprises securing a control signal connected to the switching circuit. 5. The method of compliance with the claim 1, further characterized in that it comprises: reducing the leakage current in a bank of RAM associated with the CAM bank by raising a virtual ground connection of each RAM cell on the ground connection of the circuit; and pulling the virtual ground connection of each RAM cell associated with the selected CAM inputs to the circuit ground connection before reading or writing the RAM cell. The method according to claim 5, characterized in that the virtual ground connection of each RAM cell is raised above the ground connection of the circuit by a predetermined amount. The method according to claim 6, characterized in that the predetermined amount is the voltage drop through a diode interposed between a virtual grounding node of each RAM cell and the ground connection of the circuit. The method according to claim 1, further characterized by comprising: reducing the leakage current in the memory cell at each CAM input in the bank by raising a virtual ground connection of each memory cell over the connection to circuit earth; and pulling the virtual ground connection of each memory cell in a plurality of CAM inputs less than the bank entry number to the circuit ground connection before reading or writing the memory cell. The method according to claim 8, characterized in that the virtual ground connection of each memory cell is raised above the ground connection of the circuit by a predetermined amount. 7. The method of compliance with the claim 9, characterized in that the predetermined amount is the voltage drop across a diode interposed between a virtual grounding node of each memory cell and the ground connection of the circuit. 11. A CAM placed in banks, characterized in that it comprises: CAM driver circuits a plurality of CAM inputs, each CAM input includes a plurality of download circuits comprising: a memory cell that stores a key field bit; a comparator connected to a CAM input correlation line and operative to compare a key bit applied to the key field bit in the memory cell, and further operative to download the correlation line to a virtual grounding node if the key bit and the key field bit have a bad comparison; and two or more selectively activated switching circuits, each interposed between the virtual grounding node of one or more comparators and the ground connection of the circuit, each switching circuit operating in an open state to inhibit the discharge of one or more correlation lines associated with maintaining the virtual grounding node of comparators connected at a voltage level on the ground connection of the circuit, and operating in a closed state to allow the discharge of the correlation lines when pulling the nodes of virtual ground connection to the circuit ground connection. 12. The CAM in accordance with the claim 11, characterized in that a CAM bank is functionally divided into two or more sub-banks by the selective activation of switching circuits to enable only a sub-set of CAM inputs. 13. The CAM in accordance with the claim 12, characterized in that the switching circuits are selectively activated by the decoded control signals of the address bits applied to the CAM. 1
4. 4. The CAM according to claim 12, characterized in that a switching circuit controls the virtual ground connection of all the comparators of a CAM sub-bank. 1
5. 5. The CAM according to claim 12, further characterized in that it comprises a RAM placed in banks, comprising: RAM driver circuits a plurality of RAM lines, each one including a plurality of RAM cells; and two or more independently and selectively activated switching circuits, each interposed between the virtual grounding node of one or more RAM cells and the ground connection of the circuit, and operating in an open state to reduce leakage currents in the RAM cells by maintaining the virtual grounding node at a predetermined voltage level over the ground connection of the circuit, and operating in a closed state to allow reading and writing of the RAM cells by pulling the node virtual ground connection to the circuit ground connection. 1
6. 6. The CAM in accordance with the claim 15, characterized in that a RAM bank is functionally divided into two or more sub-banks by the selective activation of the switching circuits to enable reading or writing of only a subset of RAM lines. 1
7. 7. The CAM in accordance with the claim 16, characterized in that the switching circuits are controlled by the control signal of the associated CAM input. 1
8. 8. The CAM in accordance with the claim 17, characterized a switching circuit controls the virtual ground connection of all the RAM cells of a RAM sub-bank. 1
9. 9. A processor, characterized in that it comprises: an instruction execution unit; a memory controller; and a bank-cache memory including a CAMRAM placed on a bank, each CAM bank includes a plurality of CAM inputs and CAM driver circuits, at least one CAM bank is further functionally divided into a plurality of sub-banks , without duplication of the CAM driver circuits by disabling all the discharge circuits of the correlation line at each CAM input in the bank, and selectively enabling the download circuits of the correlation line in a plurality of smaller CAM inputs than the total number of CAM entries in the CAM bank. The processor according to claim 19, further characterized in that it comprises two or more selectively activated switching circuits, each interposed between a virtual grounding node of each correlation line discharge circuit in a sub-bank and connection and circuit ground. The processor according to claim 19, characterized in that the CAMRAM further placed in bank further includes at least one RAM bank in which a virtual grounding node of all the RAM cells is held over the connection to circuit ground by a predetermined amount to reduce the leakage current, and where the RAM bank is functionally divided into a plurality of sub-banks by selectively pulling the virtual grounding node of all the RAM cells in the sub-bank. bank to the ground connection of the circuit before reading or writing the RAM cells. The processor according to claim 21, further characterized in that it comprises at least one selectively activated switching circuit interposed between the virtual grounding node of each RAM cell in a sub-bank and the ground connection of the circuit . The processor according to claim 21, further characterized in that it comprises at least one diode interposed between the virtual grounding node of each RAM cell in a bank and the ground connection of the circuit, the diode determines the voltage of the virtual earth connection node of the RAM cell on the ground connection of the circuit.