MX2008001997A - Mejora de verificacion de valor de carga avanzada. - Google Patents

Mejora de verificacion de valor de carga avanzada.

Info

Publication number
MX2008001997A
MX2008001997A MX2008001997A MX2008001997A MX2008001997A MX 2008001997 A MX2008001997 A MX 2008001997A MX 2008001997 A MX2008001997 A MX 2008001997A MX 2008001997 A MX2008001997 A MX 2008001997A MX 2008001997 A MX2008001997 A MX 2008001997A
Authority
MX
Mexico
Prior art keywords
value
load value
table entry
value check
advanced load
Prior art date
Application number
MX2008001997A
Other languages
English (en)
Inventor
Bohuslav Rychlik
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of MX2008001997A publication Critical patent/MX2008001997A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Retry When Errors Occur (AREA)
  • Executing Machine-Instructions (AREA)
  • Devices For Executing Special Programs (AREA)

Abstract

Se describen sistemas y metodos para realizar instrucciones de computadora reordenadas. Un procesador de computadora carga un primer valor proveniente de una primera direccion de memoria, y guarda tanto el primer valor como el segundo valor en una tabla o cola. El procesador almacena un segundo valor en la misma direccion de memoria, y desaloja la entrada de tabla anterior, o anade el segundo valor a la entrada de tabla anterior. Despues de detectar subsecuentemente la entrada de tabla desalojada o el segundo valor inconsistente, el procesador genera una excepcion que activa la recuperacion del uso especulativo del primer valor.
MX2008001997A 2005-08-12 2006-08-09 Mejora de verificacion de valor de carga avanzada. MX2008001997A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/202,770 US7613906B2 (en) 2005-08-12 2005-08-12 Advanced load value check enhancement
PCT/US2006/031297 WO2007021887A2 (en) 2005-08-12 2006-08-09 Advanced load value check enhancement

Publications (1)

Publication Number Publication Date
MX2008001997A true MX2008001997A (es) 2008-04-16

Family

ID=37564037

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2008001997A MX2008001997A (es) 2005-08-12 2006-08-09 Mejora de verificacion de valor de carga avanzada.

Country Status (7)

Country Link
US (1) US7613906B2 (es)
EP (1) EP1922612B1 (es)
KR (1) KR101049344B1 (es)
CN (2) CN101283331B (es)
IL (1) IL189451A0 (es)
MX (1) MX2008001997A (es)
WO (1) WO2007021887A2 (es)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7937565B2 (en) * 2007-02-21 2011-05-03 Hewlett-Packard Development Company, L.P. Method and system for data speculation on multicore systems
US11098139B2 (en) 2018-02-28 2021-08-24 Chevron Phillips Chemical Company Lp Advanced quality control tools for manufacturing bimodal and multimodal polyethylene resins

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2786574B2 (ja) * 1992-05-06 1998-08-13 インターナショナル・ビジネス・マシーンズ・コーポレイション コンピュータ・システムにおける順不同ロード動作の性能を改善する方法と装置
US5467473A (en) * 1993-01-08 1995-11-14 International Business Machines Corporation Out of order instruction load and store comparison
US5682493A (en) * 1993-10-21 1997-10-28 Sun Microsystems, Inc. Scoreboard table for a counterflow pipeline processor with instruction packages and result packages
WO2000026771A1 (en) 1998-10-30 2000-05-11 Intel Corporation A computer product, method, and apparatus for detecting conflicting stores on speculatively boosted load operations
US6463579B1 (en) * 1999-02-17 2002-10-08 Intel Corporation System and method for generating recovery code
US6728867B1 (en) * 1999-05-21 2004-04-27 Intel Corporation Method for comparing returned first load data at memory address regardless of conflicting with first load and any instruction executed between first load and check-point
US6408379B1 (en) * 1999-06-10 2002-06-18 Advanced Micro Devices, Inc. Apparatus and method for executing floating-point store instructions in a microprocessor
US6658559B1 (en) * 1999-12-31 2003-12-02 Intel Corporation Method and apparatus for advancing load operations
US6681317B1 (en) * 2000-09-29 2004-01-20 Intel Corporation Method and apparatus to provide advanced load ordering
US7062638B2 (en) * 2000-12-29 2006-06-13 Intel Corporation Prediction of issued silent store operations for allowing subsequently issued loads to bypass unexecuted silent stores and confirming the bypass upon execution of the stores
CN1142485C (zh) * 2001-11-28 2004-03-17 中国人民解放军国防科学技术大学 流水线控制相关延迟消除方法
US20050055516A1 (en) * 2003-09-10 2005-03-10 Menon Vijay S. Method and apparatus for hardware data speculation to support memory optimizations

Also Published As

Publication number Publication date
WO2007021887A3 (en) 2007-05-18
CN101283331A (zh) 2008-10-08
US20070035550A1 (en) 2007-02-15
IL189451A0 (en) 2008-08-07
EP1922612B1 (en) 2014-04-23
CN101283331B (zh) 2013-05-29
CN103336682B (zh) 2016-07-06
US7613906B2 (en) 2009-11-03
KR20080041251A (ko) 2008-05-09
WO2007021887A2 (en) 2007-02-22
KR101049344B1 (ko) 2011-07-13
CN103336682A (zh) 2013-10-02
EP1922612A2 (en) 2008-05-21

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MX2008001997A (es) Mejora de verificacion de valor de carga avanzada.

Legal Events

Date Code Title Description
FG Grant or registration