MX2008001245A - Semiconductor storage device. - Google Patents

Abstract

When a requested access is data write into a memory array (100), a semiconductor storage device (10) sets the maximum count value in a carry up unit (111) of an address counter (110) to 128 bits. On the other hand, when the requested access is a data read-out from the memory array (100), the semiconductor storage device (10) sets the maximum count value in the carry up unit (111) of the address counter (110) to 256 bits. This reduces the size of a circuit configuration required for specifying a desired address in an EEPROM array (101) and a mask ROM array (102).

Description

SEMICONDUCTOR STORAGE DEVICE Field of Technology The present invention relates to sequential access semiconductor memory devices and address control methods in semiconductor memory devices which are accessed sequentially.

Background of Matter EEPROMs are known as semiconductor memory devices in which the data cells in the memory device can only be accessed sequentially. Because this type of semiconductor memory device is relatively inexpensive, it is used as a memory device for storing data in relation to the amount of consumable materials remaining or the amount of consumable materials used. In addition, there are also semiconductor memory devices that have been produced that have multiple storage areas, e.g., EEPROM areas and hidden ROM areas. In semiconductor memory devices having multiple data storage areas, the use of a hidden ROM area has the benefit of eliminating the need to write read-only data in the semiconductor memory device. However, sequential access semiconductor devices, when provided with a single area of data storage that has an area that can be written that is less than the read-only area, can not return to the start address of the writable area without counting to the final address of the first read-only area. The result is a problem since more time is required in the data writing process than in the data reading output. Further, because in a semiconductor memory device the address in which access is initiated is typically specified by the use of an address code, and the semiconductor memory devices are provided with a plurality of data storage areas, Address codes should be provided for each of the data storage areas, which tends to increase the scope of the circuit structure.

Disclosure of the Invention The present invention addresses the topics described above and the object thereof is to achieve a reduction in the time required for data writing in a semiconductor memory device and achieve a reduction in the circuit structure required for the specification of directions. A first aspect of the present invention in order to address the topics described above, provides a semiconductor memory device. The semiconductor memory device according to the first aspect of the present invention comprises an address counter wherein the maximum counter values are different at the time of reading the data compared to the time when the data is written, a non-volatile memory device which is accessed sequentially until the target address specified by the address counter is reached, a module data writing system that writes data, through a specific address unit, from said target address of said memory device and a data reading module for the reading output of data coming from an objective address of said memory device. Given the semiconductor memory device according to the first aspect of the present invention, an address counter having different maximum counter values at the time of data reading as compared to the time of data writing is used to specify the target address that is to be accessed, thus making it possible to achieve a reduction in the circuit structure required to specify the address. In the semiconductor memory device set forth in the first aspect of the present invention, the address counter may specify the starting address of the memory device after counting the counter values until reaching each of the maximum counter values. In this case, it is possible to return to the starting address of the memory device after the counter value has reached the maximum counter value. In the semiconductor memory device according to the First aspect of the present invention, the address counter can count external clock signals, synchronized with said external clock signals that are input from the outside of the semiconductor memory device. In the semiconductor memory device according to the first aspect of the present invention, the memory device is provided with a first memory area having a first terminating address, and a second memory area, having a second memory address. term and, following the first memory area, where the maximum counter value at the time of writing is a counter value corresponding to the first term address, and the maximum counter value at the time of reading can be a value where a specific value is added to the counter value corresponding to the second term address. In this case, because the address specification process is not carried out for the second storage area when writing data, it is possible to reduce the time required for data writing in the first storage area. In the semiconductor memory device according to the first aspect of the present invention, the address counter may specify the start address of the first storage area in the memory device after counting to each of the maximum counter values . In this case, the counter value can return to the start address of the first storage area after reaching the value of maximum counter. In the semiconductor memory device according to the first aspect of the present invention, the first storage area is a storage area in which data can be written, and the second storage area is a storage area from which it can only be stored. read any information In this case, when data writing is not only the address specification process carried out only for the first storage area, but also, when data is read, the address specification process is carried out for both storage areas, first and second. In the semiconductor memory device according to the first aspect of the present invention, the first storage area can be a 128 bit storage area where the data can be stored, the second storage area can be a storage area of 64 bits where the data can be stored and the address counter can be an 8-bit address counter, where, when written, the start address for the first storage area can be specified after the value of the bits MSB takes a "1" and, when it is read, the start address of the first storage area can be specified after the values of the eight bits take "1". In this case, after the counter value has reached 256 when data is read, or after the counter value has reached 128 bits when writing data, the address counter can return to the start address of the first storage area. A second aspect of the present invention provides a method of address control in a semiconductor memory device provided with a non-volatile memory device which is accessed sequentially, until an objective address is reached which is specified by a counter. direction that counts, synchronized with an external clock. The method of address control according to the second aspect of the present invention comprises determining whether a request for access to the memory device is a write request or a read request, and if the access request is a write request, specify the start address in the memory device when the external clock has counted up to the first maximum counter value, and if the access request is a read request, specify the starting address of the memory device when the external clock has counted up to the second maximum counter value, which is greater than the first maximum counter value. The address control method according to the second form of the present invention can not only provide the same effects as the semiconductor memory device according to the first form of the present invention, but the address control method according to with the second form of the present invention it can also be incorporated in a variety of ways, in the same way as the memory device semiconductor according to the first form of the present invention. The method according to the second form of the present invention can also be incorporated as a computer program or a computer-readable memory medium on which a computer program is registered.

Brief Description of the Drawings Fig. 1 shows a block diagram illustrating the functional internal structure of a semiconductor memory device according to the present embodiment. Fig. 2 shows an explanatory diagram illustrating schematically an internal structural map of a memory device provided in a semiconductor memory device according to the present embodiment. Fig. 3 is a timing flow diagram illustrating the temporal relationships between the restart signal EST, the external clock signal SCK, the data signal S DA, and the address counter value during execution of a reading operation. Fig. 4 is a flow chart illustrating the processing routine for a data reading process that is executed by a host computer and a semiconductor memory device according to the present embodiment. Fig. 5 is a flow chart illustrating relationships temporary between the reset signal RST, the external clock signal SCK, the data signal SDA, and the address counter value during the execution of a write operation. FIG. 6 is a flow diagram illustrating the processing routine for a data writing process that is executed by a host computer and the semiconductor memory device according to the present embodiment. Fig. 7 shows an explanatory diagram illustrating an example of an application of a semiconductor memory device according to the present embodiment.

BEST MODES FOR CARRYING OUT THE INVENTION The semiconductor memory device according to the present invention and the address control method in the semiconductor memory device will be explained below based on an example of modality, while reference is made to the figures.

Structure of the Semiconductor Memory Device The structure of the semiconductor memory device 4 according to the present embodiment example will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a bl ock diagram that ill Ustra the functional internal structure of a semiconductor memory device according to the present embodiment example. Fig. 2 is an explanatory diagram illustrating schematically an internal structural map of a memory device provided in the semiconductor memory device according to the present embodiment example. In the present embodiment example, a semiconductor memory device 10 is a sequential access type memory device that does not require the input of address data from the outside to specify the address to initiate access. The semiconductor memory device 10 comprises a memory device 100, an address counter 10, an input / output controller 120, an ID comparator 130, a read / write controller 140, an increment controller 150, a circuit load pumping 160 and a holding register 170. Each of these circuits is connected through a bus-type signal lines. The memory device 100 comprises a device EEPROM 101 and a hidden ROM device 102. The EE PROM 101 device is a memory area having the characteristics of an EEPROM wherein the data can be erased and written electrically. The hidden ROM device 102 is a memory area having the characteristics of a hidden ROM in which the data that is written in the manufacturing process can not be deleted or overwritten. The EEPROM device 101 and the hidden ROM device 102 of the memory device 100 are provided with a plurality of data cells (memory cells) for the storage of 1 bit data, as schematically shown in Fig. 2. In the present embodiment example, the memory device 100, as shown in Fig. 2, is provided with eight addresses (addresses for data values of 8). bits) in a row as the specific address units, where, for example, 8 data cells (8 bits) are arranged in a row, and 16 data cells (16 words) are arranged in a column, and thus can store 16 words x 8 bits (128 bits) of data. The hidden ROM device 102 has 8 data cells (8 bits) in a row, with 8 data cells (8 words) in a column, and thus is capable of storing 8 words x 8 bits (64 bits) of data. The address map of the memory device 100 will be explained with reference to Fig. 2. The memory device 100 in the present embodiment example is provided with an EEPROM device 101 and a hidden ROM device 102, as described above. The identification information (ID information) to identify each of the semiconductor memory devices is stored in the first three directions (first row, columns A0 to A2: 3 bits) in the device E EPROM 101. Writing is prohibited in the first row that includes the first three addresses, and so, for example, this row can not be overwritten after being transported from the factor. In the example in Fig. 2, the ninth address (08H) to the sixteenth address (0FH) and the seventeenth address (10H) to the twenty-fourth address (07H) of the EEPROM device 1 01, you can store 16 bits of data that can be overwritten under specific conditions. Note that in the present mode example, the rows comprising the ninth direction to the sixteenth address and the seventeenth direction to the twenty-fourth direction are known as the write control rows, and the eight directions in the ninth direction up the sixteenth address and the 8 addresses in the seventeenth address to the twenty-fourth address are known as write control storage addresses for specific address units. Furthermore, these specific conditions are the case where, for example, the information stored is information in relation to the amount of ink that has been consumed, and the value of the data per write is greater than the value of the data. existing, or the case where the stored information is information regarding the amount of ink remaining, and the value of the data to be written is less than the value of the existing data. The address 25 and so on in the device E EPROM 1 01 is a read-only area where writing is prohibited and can not be overwritten, for example, after transportation from the factory. Note that each of these address properties (this address map) is a mere example and that various address properties can be determined so that, in addition to the controlled writing area, there is also an area that allows writing for which the structure is not controlled. In the hidden ROM device 1 02, the information (data) is Write when the memory device is manufactured, and after the manufacture of the memory device, the writing can not be carried out in this area, even before transporting the factory. Note that the hidden ROM device 102 is a 64-bit data storage area, where the maximum address of the hidden ROM device 102 that can be specified logically is 192 (BFH), but the memory device 100 is provided with a structure of circuit that emits useless data (for example "0") to the 256th address (FFH) even if the maximum value for the hidden ROM device 102 is exceeded. The result is that the memory device 100 is a memory device that can easily used, provided with a virtual memory area of 128 words x 128 bits. The memory device 100 in the present embodiment example is provided with a plurality of rows, which are 8-bit units, as described above, where the columns of data cells are not independent of each row, but rather occur in what is called a data cell column that is bent backward in 8 bits units. That is, for convenience, the row that includes the ninth bit is known as the second byte, and the row that contains the seventeenth bit is known as the third byte, the result is that, in order to have access to the desired address in the memory device 100, it is necessary to have access sequentially from the beginning, that is, it is necessary to have access through the use of the so-called sequential access method, where you have direct access to the desired address, which is possible in the case of a random access method, is not possible in the sequential access method. A line of words and a line of bits (data) are connected to each of the data cells in the memory device 100, where the data is written to a data cell by selection (applying a selection voltage a) of the corresponding word line (row) and the application of a write voltage to the corresponding bit line. The data (a "1" or a "0") of the data cell are output by reading by selecting the corresponding word line (row) and connecting the bit line corresponding to the INPUT / OUTPUT controller 120, and detection after whether or not a current exists. Note that in the present example of the mode, the specific address unit can be considered as the number of addresses (number of data cells) that can be written by applying a write voltage to a single line of words. The column selection circuit 103 sequentially selects the columns (bit lines) for the INPUT / OUTPUT controller 120 according to the pulses of the external clock that are counted by the address counter 1 10. For example, the The column selection circuit 103 connects the bit lines according to the values of the four least significant bits of the values of the eight bits that indicate the number of the clock pulses counted by the address counter 1 10.

The row selection circuit 1 04 applies a selection circuit to the row (word line) sequentially according to the number of external clock pulses counted by the address counter 1 1 0. For example, the circuit row selection 1 04 selects lines of words according to the value of the four most significant bits of the values of the eight bits that indicate the number of clock pulses counted by the address counter 10. As described above, the semiconductor memory device 10 according to the present embodiment example, performs the access to the desired address according to the number of clock pulses that have been counted by the address counter 1 10 without carrying out the access to the memory device 100 by the use of address data. The address counter 10 is connected to a reset signal terminal RSTT, a clock signal terminal SCKT, the column selection circuit 103, the row selection circuit 1 04, and a write / read controller 140 The address counter 1 10 is reset to the initial value by the reset signal, which is input through the reset signal terminal RSTT, going to "0" (or down), and then counts number of clock pulses, synchronized with the falling edge of the clock pulses, which are input through the external clock signal terminal SCKT after the reset signal has been set to "1". The address counter 10 used in the present example of the mode is an 8-bit address counter which maps the clock counts corresponding to the number of data cells (number of bits) in a row in the memory device 100. Note that the initial value may be an Such a value exists that a relationship exists with the starting position of the memory device 100, and typically "0" is used as the initial value. The address counter 10 is provided with a 1 1 1 construction unit to set the maximum counter value for the number of clock pulses to be counted. In the address counter 10, when the clock count reaches the maximum counter value, the address counter 10 returns the counter value to the initial value, which corresponds to the start position in the memory device. 100. In other words, the address specified by the address counter 1 10. The address counter 1 10 used in the present example of the mode uses a maximum counter value when the data is being written to the memory device 100 which is different from that when the data is being read from the memory device 100. Specifically, when the address counter 1 10 receives notification, coming from the write / read controller 140, to the extent that the requested access is for data writing, then the Maximum counter value in the construction unit 1 1 1 is set to 128 bits. On the other hand, when the address counter 1 10 receives notification, coming from the write / read controller 140, that the The requested access is for reading data, then the maximum counter value in the building unit 111 is set to 256 bits. In the present example of the embodiment, a memory device 100 is used comprising an EEPROM device 101 and a hidden ROM device 102, as described above. The EEPROM device 101 is provided with 128 addresses, from the first address (OOH) to the 128th address (7FH) where the hidden ROM device 102 is provided with 64 addresses, from the 129th address (80H) to the 192th address (BFH) . Because it is not possible to write data to the hidden ROM device 102, when the data is being written, the maximum counter value for the address counter 110, which is the maximum address for the memory device 100 that can be specified by the address counter 110 is set at 228th address. The result is that it is possible to eliminate the address counts corresponding to hidden ROM device 102 where the data can not be written, making it possible to reduce the time required for data writing. On the other hand, when the data is being read, the maximum counter value for the address counter 110, that is, the maximum address in the memory device 100 that can be specified by the address counter 110, is set to 256a. address. The result is that it is possible to access the addresses corresponding to hidden ROM device 102, making it possible to read out that data that is stored in the hidden ROM device 102. Note that the hidden ROM device 102 is a 64-bit data storage area, and although the maximum address of the hidden ROM device 102 can be specified logically it is 192, as already mentioned above, after the maximum address of the hidden ROM device 102 is exceeded, the simulated data is issued until the address 256 (FFH) is reached. The INPUT / OUTPUT controller 120 is a circuit that either sends the write data (which has been input to the SDAT data signal terminal) to the memory device 100, or receives the read output data from of the memory device 100 and outputs this data to the SDAT data signal terminal. The INPUT / OUTPUT controller 120 is connected to the SDAT data signal terminal, the reset signal terminal RSTT, the memory device 100 and the write / read controller 140, and carries out the control in order to change the direction of the data transfer between advancing to the memory device 100 or going to the SDAT data signal terminal (i.e., the signal lines that are connected to the SDAT data signal terminal) according to the request from the write / read controller 140. An 8-bit hold register 170 that temporarily stores the write data that is input from the SDAT data signal terminal is connected to the input signal lines from the signal terminal of SDAT data from the INPUT / OUTPUT DA 120 controller. The 8-bit retention register 170 stores the data column (MSB) entered through the input signal lines from the SDAT data signal terminal until 8-bit values are stored, and when 8-bit values are in place, the 8 data bits that are held in the 8-bit retention register 170 are written to the EEPROM device 101. The retention log 8 bits 170 is a displacement register of the so-called FI FO type (first inputs / first outputs type), and therefore, when the 9th bit of the input data is retained, the first data bit that has already been retained is eliminated. When the power supply is turned ON, or when there is a restart, the INPUT / OUTPUT controller 120 sets the direction of the data transfer in relation to the memory device 1 10 to the reading output address, and prohibits the entry of data into the SDAT data signal terminal by placing the input lines between the 8 bit retention register 170 and the INPUT7SALI DA 120 controller in a high impedance state. This state is maintained until a write process request is input from the write / read controller 140. Accordingly, the data for the first four bits of the data stream, inputted through the data signal terminal SDAT is not written to the memory device 100 after a reset signal has been entered, but rather the data that is stored in the first four bits of the memory device 100 (where the fourth bit thereof "does not matter") is sent to the I D 130 comparator. The result is that the first four bits of the memory device end in a read-only state. The ID comparator 130 is connected to the clock signal terminal SCKT, the SDAT data signal terminal, and the reset signal terminal RSTT, and determines whether the identification data included in the input data stream that is it enters through the SDAT data signal terminal, whether or not it matches the identification data stored in the memory device 100 (the EEPROM device 101). More specifically, the ID comparator 130 receives the first three data bits of the operation code that is entered after the reset signal RST is input, or, in other words, receives the identification data. The ID comparator 130 has a 3-bit register (not shown) for storing the identification data that is included in the input data stream, and a 3-bit register (not shown) for storing the identification data in the data. three more significant bits that are obtained from the memory device 100 through the INPUT / OUTPUT controller 120, and determines whether the ID data agree or disagree when determining whether the values of both registers are identical or not. The I D comparator 130 sends an EN-enabling signal to the write / read controller 140 with both I D data matches. The I D 130 comparator clarifies the value in the register when enter the RST reset signal (that is, when RST = "0" or it is low). The write / read controller 140 is connected to the INPUT / OUTPUT controller 120, the ID comparator 130, the increment controller 150, the load pumping circuit 160, the clock signal terminal SCKT, the signal terminal SDAT data, and the RSTT reset signal terminal. The write / read controller 140 verifies that the write / read control data (the data in the fourth bit after the 3-bit ID data), inputted through the SDAT data signal terminal, is synchronized with the the fourth clock signal after the introduction of the Jeinicio signal RST, and there is a circuit that changes the internal operation of the semiconductor memory device 10 between either a write operation or a read operation. More specifically, when an access enabling signal AE N is input from the ID comparator 130, or a write enable signal WEN 1 is received from the incrementing controller WEN 1, the write / read controller 140 decodes the Write / read command that has been received. If the command is a write command, then the write / read controller 140 changes the data transfer direction of the bus signal lines for the IN / OUT co-controller 120 to the write address, and sends a signal WEN2 write enabler, which allows writing, to the load pumping circuit 160, in order to request that the write voltage is generated. In the present example of the mode, if the write data D1 that is written in a controlled write string is data having a characteristic that increases (increases) the value, a decision is made as to whether the write data Dl whether or not they are a value that is greater than the existing data FROM already written in the controlled writing string, and if the writing data D1 is data that has a characteristic of decreasing (decreasing) the value, then a decision is made as soon as a if the write data Dl has a value that is smaller than the existing data DE that is already stored in the controlled write string, in order to reduce or eliminate the corruption of the data, or the input of incorrect data, by the writing data Dl. This function is provided by an increment controller in the first case and by a decrement controller in the latter case. In the present example of the modality, the first case will be used as an example in the explanation below. The increment controller 150 is connected through the signal lines to the load pumping circuit 160, the reset signal terminal RSTT, and the read / write controller 140. The increment controller 150 has a 4-bit counter internal 151 and 8-bit internal registers 152 and 153. The increment controller 150 determines whether the write data D1 that is to be written in a controlled write string is or is not a value that is greater than the existing data DE already they find each other stored in the controlled write row, to further determine if the data to be written to the EEPROM 101 device has been written correctly (ie, it carries out a verification and validation process). The increment controller 150 reads the existing data DE from the controlled write string of the EEPROM device 101 with the synchronization with which the write data Dl is retained in the 8-bit retention register 170, and stores the existing data DE in the 8-bit internal register 152, which is provided within the increment controller 150. The increment controller 150 performs a bitwise comparison of the existing data DE that has had read output and the write data Dl that they have been entered into the 8-bit retention register 170 in order to determine whether or not the write data D1 is data of a value that is greater than that of the existing data DE. Note that in order to speed up the processing and reduce the range of the circuitry, the writing data entered is preferably the MSB. When the write data D1 is data of a value that is greater than that of the existing data DE, the increment controller 150 outputs a write enable signal WEN1 to the write / read controller 140. Note that when the writing rows When controlled, they comprise multiple rows, then the increment controller 150 emits the write enable signal WEN only when the write data Dl they are data of a value greater than that of the existing data DE in all rows of controlled writing. After the write data has been written, the increment controller 150 inspects whether the write has been carried out correctly or not, then the existing DE data, which is stored in the 8-bit internal register 152, is written again in the memory device 100. When the written data is inspected, the 4-bit counter 151, which is provided in the increment controller 150, has a delay of 8 bits, relative to the external clock signal, coming from of the write-waiting state before starting counting of the internal clock signals from the internal oscillator 162 that is provided in the load pumping circuit 160. The counter value that is counted by the 4-bit counter 151 is enter the column selection circuit 103 and the row selection circuit 104 to read out the existing data that has just been written. The load pumping circuit 160, as described above, is a circuit for providing the EEPROM device 101 with the write voltage necessary to write data through the column selection circuit 103 in the selected bit lines, based on the request signal from the write / read controller 140. The load pumping circuit 160 is provided with an internal oscillator that generates the operating frequency when the voltage is scaled, and produces the required voltage for writing by stepped elevation of the voltage obtained through the positive power supply terminal VDDT. Reading Output Process The reading output operation in the semiconductor memory device 10 according to the present embodiment example will be explained below with reference to Fig. 3 and Fig. 4. Fig. 3 is a timing diagram illustrating the temporal relationships between the values of the reset signal RST, the external clock signal SCK, the data signal SDA and the address counter when the read output operation is carried out. Fig. 4 is a flowchart illustrating the processing routine for the data reading output process that is carried out by the host computer and the semiconductor memory device 10 according to the present embodiment example. Procedures to verify identification information and to verify read / write commands, before the reading operation, they will be explained immediately. When the restart state (RST = 0 or low) is released (RST = 1 or high) (Step Sh100) by the host computer (in, for example, Fig. 8), the semiconductor memory device 10 initiates the process of memory side reading. The host computer inputs an SDA data signal, which includes a 4-bit operation code, into the SDAT data signal terminal of the semiconductor memory device 10, synchronized with the external clock signal. Plus specifically, the host computer first sends the 3-bit identification data to the semiconductor memory device 10 (Step Sf102). As shown in FIG. 3, the memory device 100 stores, in the first three bits, identification data IDO, ID1 and ID2, and in the fourth bit from the beginning, stores a command bit that determines writing or reading . The comparison of the identification data is carried out and described below. The ID comparator 130 of the semiconductor memory device 10 performs an ID recovery process which determines whether or not the entered identification data agree with the identification data which is stored in the memory device 100 (Sm100). Specifically, the ID comparator 130 receives the data that is input to the SDAT data signal terminal at the elevation edges of the three SCK clock signals after the reset signal RST has changed from low to high, or in other words, it receives the three bits of identification data, and stores this data in a first 3-bit register. At the same time, the ID comparator receives the data coming from the addresses in the memory device 100 specified by the counter values 00, 01, and 02 of the address counter 110, or in other words, receives the identification data that they are stored in the memory device 100 and store this data in a second 3-bit register. The ID comparator 130 determines whether the data of IDs stored in the registers, first and second, are identical or not, and if the identification data do not match (Stage Sml OO: Unmatched), the input signal lines between the 8-bit retention register 170 and the controller INPUT / OUTPUT D 120 will be maintained in a high impedance state by the INPUT / OUTPUT controller 120. The result is that access to the memory device 100 is not allowed and the data reading output process is terminated. On the other hand, if the identification data in the first and second registers are identical (Step Sm 100: coincidence), the ID comparator 130 issues an AEN access enabling signal to the write / read controller 140. The host computer enter the command bit (the read command, eg, a "0" bit) in the SDAT data signal terminal synchronized with the rising edge of the fourth clock signal SCK after the restart signal RST is changes from low to high (Stage Sh104). The read / write controller 140, having received the access enabling signal AE N, receives the command bit, which has been sent to the bus signal line through the SDAT data signal terminal and determines whether the command is or is not a write command. If the command bit that has been received is a write command, then the write / read controller 140 issues a read command to the INPUT / OUTPUT controller 120. The INPUT / OUTPUT controller 120, having received a read command, changes the data transfer direction for the memory device 100 to the read address (the output state) (step Sm102), in order to allow the transfer of data from the memory device 100. In addition, the write / read command controller 140 provides notification to the address counter 1 10 that the requested access is a data read. Having received this notification, the construction unit 1 1 1 of the address counter 1 10 establishes the maximum counter value in 256 bits. The host computer outputs, to the clock signal terminal SCKT of the semiconductor memory device 10, a number of SCK pulses of clock signal corresponding to the address for which access is desired or, in other words, corresponding to the address in where the pending read output data is stored. (Step Sh106) The address counter 1 10 of the semiconductor memory device 10 forms the SCK clock signals, synchronized with the falling edges thereof, to count the number of clock pulses entered (Sm 104). Note that because the counter value of the address counter 1 10 after the operation code is entered is "04", the existing data DE which is stored in 04H of the memory device 100 has read output. Although the memory device 100 of the semiconductor memory device 10 according to the present embodiment example has been directed from OOH to BFH, the Address counter 1 10, as already described above, counts up to 256 bits (address FFH) which is set in the construction unit 1 1 1. The addresses COH to FFH are a simulated region, where the corresponding addresses do not exist in the memory device 100, but rather when the simulated region is accessed, the value "0" is output to the SDAT data signal terminal. When the number of pulses corresponding to the address FFH or, in other words, 256, is counted by the address counter 1 10, the address in the memory device 100 which is indicated by the address counter 1 10 returns to the address OOH (Step Sm106). In other words, at the point where the values (bits) in the 8-bit register of the address counter 110 have all been addressed to "1", the OOH start address of the EPROM E 101 in the memory device 100 it is specified as the following access address. The existing data DE which is stored in the memory device is sequentially output to the SDAT data signal terminal via the INPUT / OUTPUT controller 120, synchronized with the falling edge of the clock signal SCK (Step Sm108), where the existing data emitted DE is maintained until the next falling edge of the clock signal SCK. With the falling edge of the clock signal SCK, the counter value in the address counter 1 10 is increased by one, and the result is that the existing data DE to be stored in the next address (data cell) of the 100 memory device are issued to the SDAT data signal terminal. This operation is repeated, synchronized with the clock signal SCK, until the desired address is reached. That is, because the semiconductor memory device 10 according to the present embodiment example is a sequential access type memory device, the host computer must output a number of clock pulses corresponding to the address to be read. or to be written, and the counter value of the address counter 10 must be increased to the counter value corresponding to the desired address. The result is that the existing data DE has sequential readout output from the addresses specified by the counter value of the address counter 1 10, which is increased sequentially in synchronization with the clock signal SCK. The host computer receives the data that is issued sequentially from the semiconductor memory device 10 (Step Sh108). As described above, because the memory device 100 in the present embodiment example is a sequential access memory, the data that is stored in the memory device 100 obtains read output sequentially until the memory is reached. desired address. By controlling the correlation between the data to be emitted by the semiconductor storage device 10 and the number of clock pulses to be emitted to the semiconductor memory device 10, the host computer specifies and receives the data for the desired address (Sh1 10). After the reading operation has been completed, a "0" or low reset signal is input from the host computer, originating a state where the semiconductor memory device 10 awaits receipt of an operation code. When the reset signal RST (= 0 or low) is inputted, the address counter 1 10, the controller of E NTRADA / SALI DA 120, the ID comparator 130, the write / read controller 140 and the increment controller 150 are initialized.

The Writing Process The operation written in the semiconductor memory device 10 according to the present embodiment example will be explained with reference to Fig. 5 and Fig. 6. Fig. 5 is a synchronization diagram which illustrates the temporal relationship between the RST reset signal, the external clock signal SCK, the data signal S DA, and the address counter value at the time a write operation is executed. Fig. 6 is a flow diagram illustrating the processing routine for the data writing process that is executed by the host computer and the semiconductor memory device 10 according to the present embodiment example. In the semiconductor memory device 10 according to the present embodiment example, the writing is carried out by the row unit (the 8-bit unit) or, in other words, carried out by a unit of specific address (an address unit of 8). After the restart state (RST = 0 or low) is cleared (RST = 1 or raised) by the host computer (shown in, for example, Fig. 8) (Step Sh200), the semiconductor memory device 10 releases the writing process of the memory side. Note that, strictly speaking, during the process of decoding the operation code it has not been determined whether the process will be a writing process or a reading process, for convenience in explanation, this will be called a "writing process" below , including the process of decoding the operation code. The host computer inputs, in the SDAT data signal terminal of the semiconductor memory device 10, an SDA data signal, which includes a 4-bit operation code, synchronized with the external clock signal. More specifically, the host computer first sends the 3-bit identification data to the semiconductor memory device 10 (Step Sf202). The I D comparator 130 of the semiconductor memory device 10 performs the I D recovery process which determines whether the entered identification data agree or disagree with the identification data that is stored in the memory device 100 (Sm200). Specifically, the I D 130 comparator obtains the data that is input to the S DAT data signal terminal, synchronized with the elevation edges of the three SCK clock signals after the RST reset signal has changed from low to high or, in other words, receives the 3-bit identification data, and stores this three-bit identification data in a first three-bit register. At the same time, the ID comparator 130 obtains data from the addresses in the memory device 100 specified by the counter values 00, 01 and 02 of the address counter 1 10. In other words, the ID comparator 130 it obtains the identification data that is stored in the memory device 100 and stores this data in a second 3-bit register. The ID comparator 130 determines whether the identification data stored in the registers, first and second, are identical or not, and if the identification data are identical (Step Sm200: Unmatched), then the state of high impedance of the Input lines between the 8-bit hold register 170 and the INPUT / OUTPUT controller 120 are maintained by the INPUT / OUTPUT controller 120. The result is that access to the memory 100 is not enabled and the data reading process. On the other hand, if the identification data stored in the first and second registers are identical (Step Sm200: Matching), then the ID comparator 130 issues an AEN access enabling signal to the write / read controller 140. The The host computer enters, in the SDAT data signal terminal, the command bit (the write command, for example, a "1" bit), synchronized with the elevation edge of the fourth signal of the SCK clock after the RST reset signal changed from low to high (Step Sh204). Having received the access enable signal AEN, the write / read controller 140 receives the command bit that was sent to the bus signal line through the data signal terminal CDAT, and determines whether this is a command of writing or not. If the command bit that has been received is a write command and if a write enable signal WEN1 has been received from the increment controller 150, then the write / read controller 140 outputs a write enable signal WEN2 towards the INPUT / OUTPUT controller 120. The INPUT / OUTPUT controller 120, having received the write enable signal WEN2, changes the direction of the data transfer with the memory device 100 to the write address (input mode) (Step Sm202) in order to allow the transfer of data with the memory device 100.

In addition, the write / read controller 140 provides notification to the address counter 1 10 so that the requested access is for data writing. Having received this notification, the counting unit 1 1 1 of the address counter 1 10 sets the minimum value to 128 bits. The host computer outputs, to the clock signal terminal SCKT of the semiconductor memory device 10, a number of clock signal pulses SCK corresponding to the address for which access is desired or, in other words, corresponding to the address for which are about to read the data. (Stage Sh206).

When the number of clock pulses corresponding to the address 7FH or, in other words, "128" has been counted by the address counter 110, the address in the memory device 100 which is signaled by the address counter 100 and is return to the OOH address. (Step Sm206). That is, at the point where the value of the eighth bit (the most significant bit) in the 8-bit register in address counter 1 10 is directed to "1", the next specified access address will be the start address OOH in the EEPROM 101 in the memory device 100. After the operation code has been entered, then, as shown in FIG. 5, 4 clock signals are input to the clock signal SCKT, and establishes a write waiting state. The host computer sends the write data to the SDAT data signal terminal of the semiconductor memory device 10. The address counter 1 10, synchronized with the falling edge of the clock signal SCK and therefore the counter value of the address counter 100 and will be 08 after the write wait state. Accordingly, the data that is received through the SDAT data signal terminal will be written in units of 8 bits starting at the address 08H in the memory device 100 according to this count. (Stage Sm208). In the present example of the embodiment, the 16-bit long write data is written to the memory area 100, which has eight bits in a row. At the time of the writing process, the first eight data bits starting with the most significant bits (MSB) of the write data Dl are sequentially retained in the 8-bit retention register 170, synchronized with the rising edge of the clock signal SCK. In addition, the data existing after the eighth address in the memory device 100 is sequentially output on the data output signal line (the SDAT data signal terminal) synchronized with the falling edge of the clock signal. SCK until the write enable signal WEN2 is output to the INPUT / OUTPUT controller 120. The existing data DE which is output on the data transmission signal line is input to the increment controller 150, and is used, together with the write data Dl that has been retained in the eight bit retention register 170, in determining whether or not the write data D1 in the increment controller 150 is a value that is greater than the existing data DE . This determination process is carried out after the rising edge of the SCK clock signal in the eighth cycle after the writing standby state. The INPUT / OUTPUT controller 120, having received the write enable signal WEN2, changes the data transfer direction for the memory device 100 to the write address, and releases the high impedance parameter for the signal lines between the eight bit retention register 170 and the INPUT / OUT 120 controller in order to allow data transfer. The result is that the values of the data of writing Dl ("O" or "1") are sent to each of the bit lines of the memory device 100, after the rising edge of the clock signal SCK in the eighth cycle subsequent to the writing standby state, the write / read controller 140 requests the load pumping circuit 160 to produce the write voltage, and the writing voltage that has been produced is applied to the bit lines selected by the column selector circuit 103, which , in the present example of the modality, are all the bit lines, with the result that the eight data bits ("1" or "0") stored in the 8-bit retention register 170 are all written to the once in the row of controlled writing. The counter value of the address counter 1 10 is incremented by 1 with the falling edge of the clock signal SCK in the eighth cycle, and the write data Dl to be written in the following directions (8-way value) (the second data byte) is acquired. In addition, although the clock is found shortly after the falling edge of the SCK clock signal in the eighth cycle, a verification process is carried out to verify whether the existing data that has just been written is in agreement or not with the Dl written data used in writing. That is, although the clock is low, the counter value for specifying the address of the eight existing data bits DE that have just been written is entered into the column selector circuit 103 and the row select circuit 104 by the four-bit counter 151 provided in the increment controller 150. The result is that the eight bits of the existing data that have just been written, are issued from the IN / OUT controller 120, and are stored in the 8-bit internal register 153, provided in the increment controller 150, through the INPUT / OUTPUT controller 120. The increment controller 150 carries out a check that the eight existing data bits DE that have been stored in the 8-bit internal register 153 match the eight bits of the write data Dl which are stored in the eight bit retention register 170. In the present example of the mode, the write data Dl are data that are 16 bits long and because there are 2 rows of controlled writing (8 addresses x 2), when the process described above is carried out twice, the writing of the write data Dl is completed in the row of controlled writing. After the writing of the write data Dl has been completed, then a reset signal RST (= 0 or low) is input to the reset signal terminal RSTT by the host computer, establishing a state where the wait is expected. reception of an operation code and completing the writing procedure. Note that the writing data that is sent from the host computer, except the data corresponding to the addresses to be changed, have the same values ("1" or "0" as the data already stored in the memory device 100. In other words, the address data that is not changed is over- write with the same values. When the reset signal RST (= 0 or low) is inputted, the address counter 1 10, the INPUT / OUTPUT controller 120, the ID comparator 130, the write / read controller 140 and the increment controller 150 they are initialized. An example of application of the semiconductor memory device and according to the present embodiment example will be described with reference to Fig. 7. Fig. 7 is an explanatory diagram illustrating an example of semiconductor memory device application in accordance with Fig. 7. with the present example of the modality. The semiconductor memory device 10 according to the present embodiment example is provided in a container for containing a consumable material, such as in ink containers 310, 31 1 and 312 to contain ink as a printed recording material. When each ink container 310, 31 1 and 312 is installed in a printing device, each ink container 310, 31 1, and 312 is connected through a bus connection to a host computer 300 that is provided in the device of impression. In other words, the SDA data signal line, the clock signal line SCK, the restart signal line RST, the positive power supply line VDD, and the negative power supply line Vss of the host computer 300 are connected to the semiconductor memory device 10 that is provided in each of the individual ink containers 310, -31 1 and 312. In the present application example, the information with respect to the amount of ink, i.e. the amount of ink remaining or the amount of ink consumed, is stored in the semiconductor memory device 10. As described above, given the semiconductor memory device 10 according to the present embodiment example , the maximum counter value of the address counter 10 will be different when the data is written from a data that is read and even when a plurality of different data storage areas are provided in the semiconductor memory device 10, the The scope of the circuit structure required to specify the address can be reduced, making it possible to reduce the size of the semiconductor memory device 10. In other words, when data is written, the value corresponding to the maximum address to which data can be written is set in the EEPROM 101 device as the maximum counter value, and when data is read, the maximum address of the hidden ROM device 102 (the number of logical addresses plus the number of virtual addresses) is set as the maximum counter value, it is possible to write data to the EEPROM device 101 and the reading of data from the EEPROM device 101 and the hidden ROM device 102, using a single address counter 1 10. Further, setting the maximum value of the memory capacity in the memory device 100 as 2o means that only two lines are required between the address counter 10 and the memory device 100, making It is possible to simplify the circuit to decode the address. In contrast, typically the EEPROM device 1 01 and the hidden ROM device 1 02 would each require the proportion of a circuit structure to decode the address, to which the problem of increasing the range of the circuitry has been presented. the semi-conductor memory device. Furthermore, when the maximum value of the memory capacity in the memory device is not the 2nd, then 3 or more control lines would be required between the address counter and the memory device, so that the range of circuitry. In addition, because the maximum counter value when the data is written is less than the maximum counter value when the data is read, it is possible to achieve an increase in the processing speed in writing data to the device. semiconductor memory 10. That is, when data writing requires more time in relation to reading data, when writing data, the address specification process is not carried out for the hidden ROM device 1 02 , when data can not be written, it is possible to achieve a reduction in the time required for data writing in the 1 0 semiconductor memory device. On the other hand, when reading data, the address specification process is carried out for the hidden ROM device 1 02, making it possible to read the desired data from the EEP ROM 1 01 device and the hidden ROM device 1 02. Other M odalities (1) In order to increase the processing speed when writing data to the semiconductor memory device 10, the processing time for writing the identification data is the most significant in the data for the EEPROM area 101. In the EEPROM area 101, the temporary identification data, for example, "1 1 1", is written in the first three bits in the EEPROM area 101 before writing the data and identification data. The host computer sends "11 1" as the identification data of the operation code to the semiconductor memory device 10, in order to start with the writing of the data in the EEPROM device 101. The writing of the data proceeds through the rows 2a to 16a of the EEPROM device 101 and completed by the writing of the identification data in the first row. In other words, when the data is written for addresses that start with 08H for 8-bit units and are completed by writing data to the 7FH addresses (the 16th row), the addresses will be 7FH (where the number of clock cycles entered is 128), so that the address that is specified by the address counter 1 10 with the input of the next clock pulse is OOH, the first address is the EEPROM device 101. The host computer then issues to the device. semiconductor memory 10, the data to be written in the first row, for example, eight data bits that include the identification information in relation to the color of the ink and the type of ink. He The result is that the desired identification data is written in the first row of the EEPROM device 101. The final writing of the identification data to be stored in the first row of the EEPROM device 101 makes it possible to use the normal access logic for the memory device. semiconductor 10 when the programming (writing the initial data) of the EEPROM device 101 is carried out. Furthermore, when it is verified whether the programming of the EEPROM device 101 and the hidden ROM device 102 were carried out correctly or not, the value maximum counter for the address counter 101 is set to the maximum address of the hidden ROM device 102 (the number of logical addresses plus the number of virtual addresses), making it possible to read out the data up to the BFH address of the ROM device hidden. (2) Although in the example of the modality described above an ink cartridge was used as an example of application, the present invention can provide the same effects for a toner cartridge instead. In addition, the same effects can be obtained when applied to a medium that stores monetary equivalence information, such as a pre-paid card. (3) The verification process of the above-mentioned example of the mode can use a 4-bit counter 151 and an internal oscillator 168, and can use the existing data DE 1 retained in an 8-bit internal register 153 and the write data DI 1 retained in the 8-bit retention log to carry out the verification process by the 8-bit unit. On the other hand, without providing1 the 4-bit counter 151 and the 8-bit internal register 153, the first write data bit DI 1 that is deleted per bit of the 8-bit hold register 170 in the most significant bit, and the existing DE1 data which is read out per bit in the MSB of a controlled write string of the memory device 100 can be carried out through bit comparisons. In such a case, increment controller 150 is not needed. (4) Although, in the example of the above-described embodiment, multiple different data storage areas were used as an example in the explanation, it is also possible to apply the present invention in a case where only the EEPROM device 101 is provided. In other words, in a case where writing is prohibited after a specific row in the EEPROM device 101 and where the data can be overwritten up to that specific row, setting the final address of that specific row as the maximum counter value makes it possible not only to prohibit writing to the EEPROM 101 device beyond the specific row, but also makes it possible to increase the processing speed in overwriting to the specific row. (5) Although writing data that is 16 bits long was used as an example in the explanation of the present embodiment example, it is possible to apply the present invention instead of similar to the data having a data length that is a multiple of the length of a row in the memory device 100, such as 24 bits long or 32 bits long, making it possible to obtain the same effects. Although a semiconductor memory device and a direction control method were explained in a semiconductor memory device, according to the present invention, previously based on several examples of the embodiment, the modalities of the present invention, above described, are to facilitate the understanding of the present invention and in no way to limit the present invention. The present invention may, of course, be modified or improved, or may include equipment components, without deviating from the spirit or range of the patent claims thereto.

Claims (10)

1. CLAIMS 1. A semiconductor memory device comprising: an address counter that counts counter values to specify a target address to be accessed, wherein the maximum counter values are different at the time of reading data compared to the time of data writing; a non-volatile memory device which is accessed sequentially until the target address specified by the address counter is reached; data writing module that writes data, by a specific address unit, from said target address of said memory device; and data reading module for outputting read data from a target address of said memory device. A semiconductor memory device as set forth in claim 1, wherein said address counter specifies the start address of said memory device after the counter value has counted any of said maximum counter values. 3. A semiconductor memory device as set forth in claim 2, wherein said address counter has an external clock signal, synchronized with said external clock signal, inputted from the outside of said semiconductor memory device. 4. A semiconductor memory device as set forth in claim 1, wherein said memory device comprises a first storage area having a first end address, and a second storage area having a second end address and following said first storage area. storage area, said maximum counter value at the time of data writing is a counter value corresponding to said first end address, and said maximum counter value at the time of reading data is a value where a value is added specific to the counter value corresponding to said second final address. 5. A semiconductor memory device as set forth in claim 4, wherein said address counter specifies the start address of said first storage area in said memory device after counting to any of said maximum counter values. 6. A semiconductor memory device as set forth in claim 5, wherein said first storage area is a storage area in which data can be written, and said second storage area is a storage area from which Only data can be read. 7. A semiconductor memory device as set forth in claim 6, wherein said first area of storage is a storage area in which 128 bits of data can be stored; said second storage area is a storage area in which 64 data bits can be stored, and said address counter is an 8-bit address counter, where, after the value of the eighth bit has become "1"at the time of data writing, it specifies the start address of said first storage area and, at the time of data reading, after the values of the eight bits have become" 1", it specifies the address of start of said first storage area. 8. A container of printed registration material removably attached to a printing device and containing a material. of printed record, said printer registration material comprising: a container unit for containing said print registration material; and a semiconductor memory device as set forth in any of claims 1 to 7. 9. A printing system comprising a printing device and a container of printed recording material as set forth in claim 8, attached removably. to said printing device, wherein: said printing device is provided with a host computer that is connected by bus to a device of semiconductor memory which is equipped in said container with recording material printed through a data signal line, a clock signal line, a reset signal line, a positive power supply line, and a supply line of negative energy, and sending, to said semiconductor memory device, quantity data in relation to the printed record material consumed in the printing device; and wherein said semiconductor memory device which is installed in said container of printed recording material stores, in a memory device, quantity data received in relation to said recording registration material. 10. A method of address control in a semiconductor memory device provided with a non-volatile memory which is sequentially accessed by an address counter, synchronizing the counts with an external clock until a specified target address is reached , said method comprising: determining whether a request for access to said memory device is a write request or a read request; specifying the start address of said memory device when said access request is a write request and said external clock has been counted up to a first maximum counter value; and specifying the first address in said memory device when said access request is a read request and said external clock has been counted up to a second counter value maximum that is greater than said first maximum counter value.