MX2007011359A - Metodo y sistema para optimizar entradas de memorias intermedias de traduccion adelantada. - Google Patents

Metodo y sistema para optimizar entradas de memorias intermedias de traduccion adelantada.

Info

Publication number
MX2007011359A
MX2007011359A MX2007011359A MX2007011359A MX2007011359A MX 2007011359 A MX2007011359 A MX 2007011359A MX 2007011359 A MX2007011359 A MX 2007011359A MX 2007011359 A MX2007011359 A MX 2007011359A MX 2007011359 A MX2007011359 A MX 2007011359A
Authority
MX
Mexico
Prior art keywords
translation lookaside
lookaside buffer
page
entry
existing
Prior art date
Application number
MX2007011359A
Other languages
English (en)
Inventor
James Norris Dieffenderfer
Thomas Andrew Sartorius
Jeffrey Todd Bridges
Victor Roberts Augsburg
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of MX2007011359A publication Critical patent/MX2007011359A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/652—Page size control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Se provee un sistema para optimizar entradas de memorias intermedias de traduccion adelantada; el sistema incluye una memoria intermedia de traduccion adelantada configurada para almacenar un numero de entradas, cada entrada que tiene un atributo de tamano, cada entrada hace referencia a una pagina correspondiente, y logica de control configurada para modificar el atributo de tamano de una entrada existente en la memoria intermedia de traduccion adelantada si una nueva pagina esta contigua con una pagina existente referida por la entrada existente; la entrada existente despues de tener su atributo de tamano modificado hace referencia a una pagina consolidada que comprende la pagina existente y la pagina nueva.
MX2007011359A 2005-03-17 2006-03-17 Metodo y sistema para optimizar entradas de memorias intermedias de traduccion adelantada. MX2007011359A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/083,691 US7366869B2 (en) 2005-03-17 2005-03-17 Method and system for optimizing translation lookaside buffer entries
PCT/US2006/010087 WO2006099633A2 (en) 2005-03-17 2006-03-17 Method and system for optimizing translation lookaside buffer entries

Publications (1)

Publication Number Publication Date
MX2007011359A true MX2007011359A (es) 2007-12-05

Family

ID=36685794

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2007011359A MX2007011359A (es) 2005-03-17 2006-03-17 Metodo y sistema para optimizar entradas de memorias intermedias de traduccion adelantada.

Country Status (9)

Country Link
US (1) US7366869B2 (es)
EP (1) EP1866773A2 (es)
JP (1) JP2008533620A (es)
KR (1) KR100944142B1 (es)
CN (1) CN101176078A (es)
IL (1) IL185963A0 (es)
MX (1) MX2007011359A (es)
TW (1) TWI307839B (es)
WO (1) WO2006099633A2 (es)

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US7895410B1 (en) * 2005-06-14 2011-02-22 Oracle America, Inc. Method and apparatus for facilitating adaptive page sizes
US8239657B2 (en) * 2007-02-07 2012-08-07 Qualcomm Incorporated Address translation method and apparatus
US7783859B2 (en) * 2007-07-12 2010-08-24 Qnx Software Systems Gmbh & Co. Kg Processing system implementing variable page size memory organization
US8028118B2 (en) * 2007-12-05 2011-09-27 Internation Business Machines Corporation Using an index value located on a page table to index page attributes
US8151076B2 (en) * 2008-04-04 2012-04-03 Cisco Technology, Inc. Mapping memory segments in a translation lookaside buffer
US20100030994A1 (en) * 2008-08-01 2010-02-04 Guzman Luis F Methods, systems, and computer readable media for memory allocation and deallocation
US8024546B2 (en) * 2008-10-23 2011-09-20 Microsoft Corporation Opportunistic page largification
US20100332788A1 (en) * 2009-06-30 2010-12-30 Li Zhao Automatically using superpages for stack memory allocation
JP2011018182A (ja) * 2009-07-08 2011-01-27 Panasonic Corp アドレス変換装置
WO2012015766A2 (en) 2010-07-28 2012-02-02 Rambus Inc. Cache memory that supports tagless addressing
US8527736B1 (en) * 2010-09-07 2013-09-03 Adtran, Inc. Systems and methods for improving address translation speed
KR101707927B1 (ko) * 2010-11-25 2017-02-28 삼성전자주식회사 메모리 시스템 및 그 운용방법
CN102486751A (zh) * 2010-12-01 2012-06-06 安凯(广州)微电子技术有限公司 一种在微内存系统上实现小页nandflash虚拟大页的方法
US8762671B2 (en) * 2011-06-28 2014-06-24 Hitachi, Ltd. Storage apparatus and its control method
US9753860B2 (en) * 2012-06-14 2017-09-05 International Business Machines Corporation Page table entry consolidation
US9811472B2 (en) 2012-06-14 2017-11-07 International Business Machines Corporation Radix table translation of memory
US9092359B2 (en) * 2012-06-14 2015-07-28 International Business Machines Corporation Identification and consolidation of page table entries
US20140075142A1 (en) * 2012-09-13 2014-03-13 International Business Machines Corporation Managing backing of virtual memory
US9330026B2 (en) 2013-03-05 2016-05-03 Qualcomm Incorporated Method and apparatus for preventing unauthorized access to contents of a register under certain conditions when performing a hardware table walk (HWTW)
US9436616B2 (en) * 2013-05-06 2016-09-06 Qualcomm Incorporated Multi-core page table sets of attribute fields
CN107533512B (zh) * 2015-06-29 2020-07-28 华为技术有限公司 目录中表项合并的方法以及设备
US10216644B2 (en) * 2016-11-04 2019-02-26 Toshiba Memory Corporation Memory system and method
GB2570474B (en) * 2018-01-26 2020-04-15 Advanced Risc Mach Ltd Region fusing

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6112285A (en) * 1997-09-23 2000-08-29 Silicon Graphics, Inc. Method, system and computer program product for virtual memory support for managing translation look aside buffers with multiple page size support
US20040117594A1 (en) 2002-12-13 2004-06-17 Vanderspek Julius Memory management method
US7003647B2 (en) 2003-04-24 2006-02-21 International Business Machines Corporation Method, apparatus and computer program product for dynamically minimizing translation lookaside buffer entries across contiguous memory

Also Published As

Publication number Publication date
IL185963A0 (en) 2008-02-09
WO2006099633A2 (en) 2006-09-21
EP1866773A2 (en) 2007-12-19
US20060212675A1 (en) 2006-09-21
KR100944142B1 (ko) 2010-02-24
US7366869B2 (en) 2008-04-29
TWI307839B (en) 2009-03-21
WO2006099633A3 (en) 2007-03-01
TW200707192A (en) 2007-02-16
CN101176078A (zh) 2008-05-07
KR20070113293A (ko) 2007-11-28
JP2008533620A (ja) 2008-08-21

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