MX2007006187A - Double data rate serial encoder - Google Patents

Abstract

A double data rate serial encoder (Fig.5) is provided. The serial encoder comprises a mux (508) having a plurality of inputs (510), a plurality of latches (502) coupled to the inputs of the mux, an enabler (504) to enable the latches to update their data inputs (518), and a counter (506) to select one of the plurality of inputs of the mux for output. In another aspect, the mux (508) provides a glitch-less output (520) during input transitions. The mux includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence provided by the counter.

Description

SERIAL ENCODER OF DOUBLE DATA TRANSFER RATE FIELD OF THE INVENTION The present invention relates generally to a series encoder for high data transfer rate serial communication links. Very specifically, the invention relates to a double data transfer rate serial encoder for Digital Mobile Screen Interface (MDDI) links.

BACKGROUND OF THE INVENTION In the field of interconnection technologies, the demand for increasing data transfer rates, especially in relation to video presentations, continues to grow. The Mobile Screen Digital Interface (MDDI) is a low-power, cost-effective transfer mechanism that allows the transfer of very high-speed data over a short-range communication link between a guest and a customer. The MDDI requires a minimum of only four cables plus power for bidirectional data transfer that delivers a maximum bandwidth of up to 3.2 Gbits per second. In one application, the MDDI increases reliability and decreases power consumption in collapsible phones by significantly reducing the number of cables passing over a device hinge to interconnect the digital baseband controller with an LCD screen and / or a camera. This reduction of cables also allows device manufacturers to lower development costs by simplifying the designs of sliding or folding devices. MDDI is a serial transfer protocol, and, as such, data received in parallel for transmission over an MDDI link needs to be serialized. What is needed, therefore, is a serial coder, integrable in an MDDI link controller, that supports the high speed data transfer rate of MDDI.

SUMMARY OF THE INVENTION In one aspect of the present invention, a double data transfer rate serial encoder is provided for the MDDI. The serial encoder comprises a multiplexer (mux) having a plurality of inputs, a plurality of closing circuits coupled to the inputs of the multiplexer, an enabler for enabling closing circuits in order to update its data inputs, and a counter to select one of the plurality of multiplexer inputs for output. In another aspect of the invention, the multiplexer provides an output without deformation signal during the input transitions. The multiplexer may include an optimized output selection algorithm based on an a priori knowledge of an input selection sequence provided by the counter. The input selection sequence can be the Gray code sequence. Further embodiments, features, and advantages of the present invention, as well as the structure and operation of the various embodiments of the present invention, are described in detail below with reference to the accompanying figures.

BRIEF DESCRIPTION OF THE FIGURES The accompanying figures, which are incorporated herein and form a part of the description, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the relevant art to do and use the invention Figure 1 is a block diagram illustrating an example of an environment using a Mobile Screen Digital Interface (MDDI) Interface. Figure 1A is a diagram of a digital data device interface coupled to a digital device and a peripheral device. Figure 2 is a block diagram illustrating an MDDI link interconnection according to an embodiment of the example of Figure 1. Figure 3 is a block diagram illustrating the internal architecture of the MDDI Guest Host Core of Figure 1 Figure 4 is a block diagram that illustrates the data flow within the MDDI Guest Core of FIG. 3. FIG. 5 is a block diagram illustrating an MDDI serial encoder in accordance with one embodiment of the present invention. Figure 6 is a circuit diagram illustrating an MDDI serial encoder according to another embodiment of the present invention. Figure 7 illustrates a multiplexer output selection algorithm in response to a Gray code entry selection sequence. Figure 8 is an example illustration of output deformation signals that may occur at the output of a multiplexer due to the selection of input transitions and data input transitions. Figure 9 is an example of a timing diagram that is related to the input clock, the selection inputs, the data inputs, and the multiplexer output of the multiplexer of Figure 6. The present invention will be described with reference to the accompanying figures. The figure in which an element appears first, is typically indicated by the digit to the left in the corresponding reference number.

DETAILED DESCRIPTION OF THE INVENTION The present disclosure shows one or more embodiments that incorporate characteristics of the invention. The described embodiments simply exemplify the invention. The scope of the invention is not limited to the described modalities. The invention is defined by the appended claims thereto. The described modalities, and references in the description to "one modality", "an exemplary embodiment", etc., indicate that the described modalities may include a particular characteristic, structure or feature but each modality does not necessarily include the particular feature, structure or feature. In addition, such phrases do not necessarily refer to the same modality. Even when a particular feature, structure or feature is described in relation to a modality, it is understood that it is within the knowledge of one skilled in the art to effect said characteristic, structure or feature in connection with other modalities whether or not they are explicitly described. The embodiments of the invention can be executed in hardware, wired microprogramming, software or any combination thereof. The embodiments of the invention can also be executed as instructions stored in a machine-readable medium, which can be read and executed through one or more processors. A machine readable medium can include any mechanism for storing or transmitting information in a machine readable form (e.g., a computing device). For example, a machine-readable medium may include read-only memory (ROM); random access memory (RAM); magnetic disk storage medium; optical storage medium; fast memory devices; electrical, optical, acoustic or other forms of propagated signals (for example, carrier waves, infrared signals, digital signals, etc.), and others. In addition, wired microprogramming, software, routines, instructions can be described in the present invention as performing some actions. However, it should be appreciated that such descriptions are simply for convenience and that said actions are in fact the result of computing devices, processors, controllers, or other devices that perform wired microprogramming, software, routines, instructions, etc.

Mobile Screen Digital Interface (MDDI) The mobile screen digital interface (MDDI) is a low power consumption and cost effective transfer mechanism that allows the transfer of serial data at very high speed over a short communication link. Scope between a guest and a client. Next, MDDI examples will be shown with respect to a camera module contained in a top folding frame of a mobile phone. However, it will be apparent to those skilled in the art that any module having functionally equivalent characteristics to the camera module could easily be substituted and used in embodiments of the present invention. In addition, according to the modalities of the i. 1 invention, a MDDI host can comprise one of several types of devices that can benefit from the use of the present invention. For example, the host could be a portable computer in the form of a handheld device, portable computer or similar mobile computing device. It could also be a Personal Data Assistant (PDA), a localization device, or one of many wireless phones or modems. Alternatively, the guest could be a portable entertainment or presentation device such as a portable CD or DVD player, or a gaming device. In addition, the guest may reside on a guest device or item of control in a variety of other widely used or planned commercial products for which a high-speed communication link with a customer is desired. For example, a guest could be used to transfer data at high speeds from a recording device video to a storage-based client for enhanced response, or to a larger high-resolution screen for presentations. A household appliance, such as a refrigerator that incorporates an on-board inventory or computer system and / or Bluetooth connections for others home devices, may have enhanced deployment capabilities when operating in a Bluetooth or Internet connected mode, or have reduced cabling needs for in-the-door screens (a client) and keyboards or scanner (client) while the electronic computer or control systems (guest) reside elsewhere in the cabinet. In general, those skilled in the art will appreciate the wide variety of modern electronic devices and appliances that can benefit from the use of this interface, as well as the ability to feed back older devices with information transport at higher data rates using limited numbers of available conductors on any existing or newly added connectors or cables. At the same time, an MDDI client can comprise a variety of useful devices for presenting information to an end user, or presenting information from a user to the guest. For example, a micro-screen incorporated in glasses or lenses, a projection device incorporated in a hat or helmet, a small screen or even a holographic element incorporated in a vehicle, such as in a window or windshield, or several loudspeaker systems , hearing aids or sound to present high quality sound or music. Other display devices include projectors or projection devices used to present information at meetings, or for films and television images. Another example would be the use of touch pads or touch-sensitive devices, speech recognition input devices, security scanners, and so on that can be used to transfer a significant amount of information from a device or system user. with little real "input" different to the touch or sound of the user. In addition, assembly stations for computers and equipment of carts or desktops and fasteners for cordless telephones can act as interface devices for end users or other devices and equipment, and can employ clients (input or output devices such as a mouse ) or guests to assist in the transfer of data, especially when high-speed networks are involved. However, those skilled in the art will readily recognize that the present invention is not limited to those devices, there being many other devices on the market, and proposed for use, which are intended to provide end users with high quality images and sound, either in terms of storage and transport or in terms of presentation in reproduction. The present invention is useful for increasing the performance of the data among various elements or devices to allow the high data rates necessary to obtain the desired user experience. Figure IA is a diagram of a digital data device interface 100 coupled to a digital device 150 and a peripheral device 180. The digital device 150 can employ, but is not limited to, a cell phone, a personal data assistant, a smart phone or a personal computer. In general, the digital device 150 can include any type of digital device that serves as a processing unit for digital instructions and the processing of digital presentation data. The digital device 150 includes a system controller 160 and a link controller 170. The peripheral device 180 may include, but is not limited to, a camera, a bar code reader, an image scanner, an audio device, and a sensor. In general, the peripheral device 180 can include any type of audio, video or image capture and display device in which the digital presentation data is exchanged between a peripheral and a processing unit. The peripheral device 180 includes control blocks 190. When the peripheral 180 is a camera, for example, the control blocks 190 may include, but are not limited to, lens control, white or intermittent LED control and shutter control. The digital presentation data may include digital data representing audio, images and multimedia data. The digital data interface device 100 transfers digital presentation data at a high speed over a communication link 105. In one example, an MDDI communication link can be used which supports bidirectional data transfer with a maximum bandwidth of 3.2 Gbits per second. Other high data transfer rates that are higher or lower than this exemplary speed can be supported, depending on the communication link. The digital data interface device 100 includes a message interpretation module 110, a content module 120, a control module 130 and a link controller 140. The link controller 140, which is located within the interface of digital data 100, and link controller 170, which is located within digital device 150, establish communication link 105. Link controller 140 and link controller 170 may be MDDI link controllers. The MDDI standard of the Association of Standards Video Electronics ("VESA"), which is incorporated in the present invention by reference in its entirety, describes the requirements of a high-speed digital packet interface that allows portable devices to transport digital images from small portable devices to screens larger external MDDI applies a miniature connector system and thin flexible cable ideal for linking computing, communications and entertainment devices to emerging products, such as supportable micro-screens. It also includes information on how to simplify connections between guest processors and a display device to reduce the cost and increase the reliability of these connections. The link controllers 140 and 170 establish a communication path 105 based on the VESA MDDI Standard. The US patent number 6,760,772, entitled Generation and Implementation of a Communication Protocol and Full Face for Transfer of High Speed Data Signals, issued to Zou et al. July 6, 2004 ("patent? 772") discloses a data interface for transferring digital data between a guest and a customer in a communication path using linked packet structures to form a communication protocol for presentation data . The embodiments of the invention shown in the Patent? 772 focus on an MDDI interface. The signal protocol is used by link controllers, such as link controllers 140 and 170, configured to generate, transmit and receive packets that form the communications protocol, and to form digital data in one or more types of data packets, at least one residing in the host device and coupled to the client through a communication path, such as communications path 105. The interface provides a high-speed, bidirectional, low power, and cost data transfer mechanism effective on a "short range" type data link, which leads to execution with miniature connectors and thin flexible cables.A modality of the link controllers 140 and 170 establishes the communication path 105 based on the teachings of the Patent 772. Patent 772 is incorporated by reference in its entirety in other embodiments. Link servers 140 and 170 may be a USB link controller or both may include a combination of controllers, such as, for example, an MDDI link controller and another type of link controller, such as, for example, a link controller USB Alternatively, the link controllers 140 and 170 may include a combination of controllers, such as an MDDI link controller and a single link for exchanging recognition message between the digital data interface device 100 and a digital device 150. link 140 and 170 can additionally support other types of interfaces, such as an Ethernet or RS-232 serial port interface. Additional interfaces can be supported, as will be known to those skilled in the art, based on the teachings shown herein. Within the digital data interface device 100, the message interpretation module 110 receives commands from, and generates response messages through the communication link 105 for the system controller 160, interprets the command messages, and guides the content of information of the commands to an appropriate module within the digital data interface device 100. The content module 120 receives data from the peripheral device 180, stores the data and transfers the data to the system controller 160 through the communication link 105 The control module 130 receives information from the message interpreter 130, and guides the information to the control blocks 190 of the peripheral device 180. The control module 130 can also receive information from the control blocks 190 and guide the information to the module of interpretation of messages 110. Figure 1 is a block diagram illustrating an exemplary environment that It creates an MDDI interface. In the example of figure 1, MDDI is used to interconnect modules on the hinge of a folding telephone 100. It should be noted that while certain embodiments of the present invention will be described in the context of specific examples, such as MDDI interconnects in a collapsible telephone, this is done for of illustration only and should not be used to limit the present invention to such embodiments. As will be understood by a person skilled in the relevant art based on the teachings shown herein, the embodiments of the present invention can be used in other devices including any that can benefit from having MDDI interconnections. Referring to Figure 1, a lower folding section 102 of the folding telephone 100 includes a Mobile Station Modem (MSM) baseband chip 104. MSM 104 is a digital baseband controller. An upper folding section 114 of the folding telephone 100 includes a Liquid Crystal Display (LCD) module 116 and a camera module 118. Referring still to Figure 1, an MDDI link 110 connects the camera module 118 to the MSM 10.

Typically, an MDDI link controller is integrated in each of the camera module 118 and MSM 104. In the example of FIG. 1, an MDDI Guest 122 is integrated in a camera module 112, while an MDDI client 106 resides in the MSM side of the MDDI link 110. Typically, the MDDI guest is the master controller of the MDDI link. In the example of Figure 1, the pixel data of the camera module 118 is received and formatted in MDDI packets by the MDDI Guest 122 before being transmitted in the MDDI link 110. The MDDI client 106 receives the MDDI packets and the -converts to pixel data of the same format as generated by the camera module 118. The pixel data is then sent to an appropriate block in the MSM 104 for processing. Referring still to Figure 1, a link MDDI 112 connects the LCD module 116 to the MSM 104. In the example of FIG. 1, the MDDI link 112 interconnects an MDDI guest 108, integrated in the MSM 104, and an MDDI client 120 integrated in the LCD module 116. In the example of Figure 1, deployment data generated by an MSM graphics controller 104 is received and formatted in MDDI packets by the MDDI guest 108 before being transmitted in the MDDI link 112. The MDDI client 120 receives the MDDI packets and the -converts in image data for use by the LCD module 116.

Fig. 2 is a block diagram illustrating the MDDI link interconnection 110 according to the example of Fig. 1. As described above, one of the MDDI link functions 110 is to transfer pixel data from the camera module 118 to the MSM 104. Accordingly, in mode 2, the frame interface 206 connects the camera module 118 to the MDDI guest 122. The frame interface 206 serves to transfer pixel data from the camera module 118 to the MDDI guest 122. Typically, the camera module 118 receives pixel data from a camera through a parallel interface, stores the pixel data, and then transfers it to the MDDI Guest 122 when the guest is ready. The MDDI guest 122 encapsulates the pixel data received in MDDI packets. However, in order for the MDDI Guest 122 to have the ability to transmit pixel data on the MDDI link 110, a serialization of the MDDI packets is necessary. In the embodiment of Figure 2, a serializer module 202, integrated within the MDDI Guest 122, serves to take out in serial form the MDDI packets in the MDDI link 110. At the MSM end of the MDDI link 110, a de-serializer module 204 , integrated within the MDDI client 106, reconstructs the MDDI packets from the serial data received over the MDDI link 110. The MDDI client 106 then removes the MDDI encapsulation and transfers the parallel pixel data through a raster interface 208 to an appropriate block of MSM 104.

MDDI Host Core Architecture The MDDI host kernel provides host-side hardware execution of the MDDI Specification as defined by the VESA (Electronic Video Standards Association). The MDDI Guest kernel is interfaced with an MDDI Guest processor and with an external connection that operates as specified in the MDDI Specification. Figure 3 is a block diagram illustrating the internal architecture of an MDDI 300 Guest Core of the MDDI Guest 122. The MDDI 300 Guest Core includes a Command Processor Block (CMD) 302, a Microprocessor Interface Block (MINT). 304, a block (REG) of Registers 306, an MDDI Packet Builder Block (MPB) 308, a Direct Access Memory Interface (DMA) block (DINT) 310, a Data Entry / Exit block (DIO) 312, and a DIO Adapter block 314. The function of each MDDI 300 Host Core block will be described with reference to Figure 3. The CMD 302 block is responsible for the processing of commands issued by the MDDI Guest 122 processor. The commands issued by The host processor includes tasks such as turning on / off the MDDI link and generating certain MDDI packets. The MINT 304 block is responsible for the interface with the MDDI Guest processor. The MDDI Guest processor uses the MINT 304 block to establish records, read registers, and issue commands to the MDDI 300 Host kernel. The MINT 304 block passes the processor commands to the CMD 302 block and registers the read / write commands to the REG 306 block. The REG 306 block stores several registers necessary for transmission of data on the MDDI link. Registers of the REG 306 block control the behavior of the MDDI link as well as the MDDI 300 Host kernel configuration. The MPB 308 block is responsible for creating the MDDI packets to be transmitted over the MDDI link as well as determining the transmission order. The MDDI packets are created from internal register values, and the data retrieved by the DINT block 310. The DINT block 310 is responsible for the interface with a DMA link of the MDDI Guest 122. The DINT block 310 issues burst requests to an external SDRAM memory of the MDDI Guest 122 for buffering data for the MPB block 308. In addition, 1 DINT block 310 assists the MPB block 308 in determining the order of the packet transmissions in the MDDI link. The DIO 312 block is responsible for handling the physical MDDI link. The DIO 312 block is responsible for the Guest-Client link protocol, data output, and round-trip delay measurements. The DIO block 312 receives data from the MPB block 308 and passes it to the DIO 314 adapter block for output. The DIO adapter block 314 receives parallel data from the DIO block 312 and outputs them serially in the MDDI link. In essence, the DIO 314 adapter block is responsible for the serialization of data required for transmission on the MDDI link. As shown in Figure 3, the DIO adapter block 314 receives an MDDI Input / Output clock signal (MDDI_IO_CLK) from the MDDI host, and outputs MDDI data (MDDI_DOUT) and MDDI strobe output signals (MDDI_STB_OUT). In one example, the DIO 314 adapter block outputs data at twice the MDDI Input / Output clock rate. Figure 4 is a block diagram illustrating the data flow outside the MDDI Host Kernel 300. For simplicity of illustration, certain blocks of the MDDI 300 Host Kernel have been omitted. Typically, at the start of the MDDI link, the output data is generated in its entirety within the DIO block 312 for the Guest-Client link protocol. Once the link protocol sequence is complete, the MPB 308 block is allowed to direct the data output stream which is received from three sources. An MPB_AUTOGEN block 402, a sub block of the MPB block 308, internally generates packets within the MPB block 308. The data of the MPB_AUTOGEN block 402 is received in an 8-bit parallel link. Such packages include, for example, filler packets, round trip delay measurements, and link closure packets. The DINT 310 block of the MDDI 300 Guest Core guides the MPB block 308 to packets received from an external SDRAM memory of the MDDI 122 Host. The DINT 310 block uses four parallel 32-bit links to guide data to the MPB 308 block. An Interface block (MDP) of MDDI Data Packages (MDPINT) 404, which is a sub-block of the MPB block 308, interfaces with an MDP block outside the MDDI Guest core and typically receives the video data packets for transmission. Block MDPINT 404 is interfaced with block MPB 308 using an 8-bit parallel link. Block MPB 308 determines the order of transmission of received packets from block DINT 310, block MPB_AUTOGEN 402, and block MDPINT 404. Block MPB 308 then directs data for transmission to block DIO 312 on a parallel link of 8 - bit. In turn, the DIO block 312 forwards the data, in an 8-bit parallel link, to the DIO adapter block 314. The DIO adapter block 314 serializes the data received from the DIO block 312 for transmission in the MDDI link. The embodiments of the DIO Adapter block 314 according to the present invention are discussed further below.

MDDI Series Encoder In essence, the DIO 314 Adapter block comprises a serial encoder for MDDI. Figure 5 is a block diagram illustrating a series encoder MDDI 500 according to one embodiment of the present invention. The series coder 500 includes a lock circuit block 502, an enable block 504, a counter block 506, and a multiplexer 508. A parallel data interface provides a parallel data stream 518 to the 500 series coder. Parallel data is received and stored by the closing circuits 502. The counter 506 issues an input selection sequence to control the output of the multiplexer 508. In the embodiment of FIG. 5, the counter 506 periodically provides the multiplexer 508 with a set of select signals 512 to select the output of multiplexer 508.

Using signals derived from the set of selected signals 512, the enabler 504 provides closing circuits 502 with a set of signals 514 to enable them to update their data inputs. A set of signals 510 couples closing circuits 502 to the inputs of the multiplexer 508. Accordingly, the closing circuit data inputs 502 and multiplexer inputs 508 are updated according to the input selection sequence generated by the 506 counter. The multiplexer 508 outputs a serial data stream 520 in the MDDI link. In one example, the multiplexer 508 is a multiplexer N: l having N inputs and a single output, where N is an integer of energy of 2. FIG. 6 is a circuit diagram illustrating an MDDI 600 series encoder according to FIG. to another embodiment of the present invention. In the embodiment of Figure 6, the MDDI 600 series encoder comprises a first layer of closing circuits 602, a second layer of closing circuits 604, a multiplexer 606, a counter 608, and an enabler 610. The first layer of closure circuits 602 comprises first and second closure circuit assemblies 612 and 614. Similarly, the second closure circuit layer 604 comprises first and second closure circuit assemblies 616 and 618. The first and second circuit sets of Closures 612 and 614 of the first layer of closure circuits 602 are coupled, respectively, to the first and second closure circuit assemblies 616 and 618 of the second layer of closure circuits 604. Each set of closure circuits 612, 614, 616 and 618 comprises a set of four closing circuits D. An input clock signal 640 is coupled to the clock input of each closing circuit D in the first and second closing circuit layers 602 and 60. 4. The multiplexer 606 has a plurality of data inputs coupled to the outputs of the second layer of closing circuits 604. In addition, the multiplexer 606 comprises a set of selected inputs that are provided by a counter 608. Typically, the multiplexer has 2N data entries, where N is the number of selected entries. In the embodiment of Figure 6, multiplexer 606 has 8 data inputs and 3 selected inputs bO, bl, and b2. The counter 608 comprises a plurality of closing circuits D. In the embodiment of FIG. 6, the counter 608 comprises a set of three closing circuits D 620, 622 and 624. The clock signal 640 provides an input to the counter 608. The outputs of closing circuits D 620, 622 and 624 correspond, respectively, to selected inputs bO, bl and b2 of the multiplexer 606. In addition, the outputs of the closing circuits D 620 and 624 are the inputs to the enabler 610. The signal of the input clock 640 controls the counter 608. The enabler 610 comprises a plurality of AND gates. In the embodiment of Figure 6, the enabler 610 comprises three AND gates 626, 628, and 630. The entrances to the gates AND 626, 628, and 630 are derived from outputs of the closing circuits D 620 and 624 of the counter 608 The outputs of AND 626 doors, 628 and 630 are respectively coupled to the second closure circuitry 618, the first closure circuitry 616, and the first and second closure circuitry sets 612 and 614. The operation of the serial encoder will now be described. MDDI 600. Assuming that the 600 series encoder has barely started, on the first rising edge of the input clock signal 640, the counter 608 emits. { b2, bl, b ?} =. { 0,0,1} . For this value of. { b2, bl, b ?} , the AND outputs 628 and 630 of the enabler 610 are correct and, consequently, the inputs of the first and second sets of closing circuits 612 and 614 of the first layer of closing circuits 602 as well as the inputs of the first set of closing circuits 616 of the second layer of closing circuits 604 can be updated. In addition, because the clock signal 640 is at the rising edge, the outputs of the first and second sets of the closing circuits 612 and 614 follow their corresponding inputs. Similarly, the outputs of the first closure circuitry 616 of the second closure circuit layer 604 also reflect their corresponding inputs. The inputs of the second closure circuitry 618 of the second closure circuit layer 604, however, remain unchanged. The multiplexer 606 selects the output of an input corresponding to the input selection value 001. At the next falling edge of the input clock signal 640, the counter 608 outputs. { b2, bl, b ?} =. { ?, l, l} . Given the . { b2, b ?} =. { ? l} , the inputs of the first and second closure circuit assemblies 612 and 614 can be updated. However, because the input clock signal 640 is at a falling edge, the outputs of the closing circuits 612 and 614 do not yet reflect the updated inputs. In other words, the outputs of the closing circuits 612 and 614 will remain the same. Accordingly, the inputs of the closing circuits 616 will also remain the same. The multiplexer 606 selects for output an input corresponding to the input selection value 011.

At the next two edges of rise and fall of the input clock signal 640, the counter 608 outputs. { b2, bl, b ?} =. { 0.1.0} Y . { b2, bl, b ?} =. { l, l,? } , respectively. No changes occur in the inputs of any set of closing circuits. At the next rising edge of the input clock signal 640, the counter 608 outputs. { b2, bl, b ?} =. { l, l, l} . For . { b2, b ?} =. { l, l} , the output of the AND gate 626 of the enabler 610 is correct and, consequently, the inputs of the second set of closing circuits 618 of the second closing circuit layer 604 are updated. In addition, because the input clock 640 is at the rising edge, the outputs of the closing circuits 618 follow their corresponding inputs. The multiplexer 606 selects an input corresponding to the input selection value 011 for output. For the next three edges of rise and fall, the counter changes through the sequence. { b2, bl, b ?} =. { l01, 100, 000.}. . The inputs and outputs of all closure circuit assemblies 612, 614, 616, and 618 remain the same throughout these transitions. Subsequently, the input selection sequence returns to. { b2, bl, b ?} =. { ?, 0, 1.}. and the cycle defined above starts again. According to the above description of the operation of the MDDI 600 series encoder, it is noted that the counter 608 changes at the rising edge or at the falling edge of the input clock signal 640 and that the multiplexer 606 outputs one bit at each input clock signal edge 640. Accordingly, the MDDI 600 series encoder is a double data rate encoder. In addition, the input selection sequence. { b2, bl, b ?} It has a simple bit that only changes in each transition of the counter. Accordingly, the input selection sequence emitted by the counter 608 represents a Gray code sequence. Figure 7 illustrates a multiplexer output sequence in response to the Gray code input selection sequence of the embodiment of Figure 6. According to the output sequence of the multiplexer of Figure 7, it is noted that multiplexer 606 selects sequentially for output the inputs coupled to the second set of closing circuits 618 during the first half of the input selection sequence and the inputs coupled to the first set of closing circuits 616 during the second half of the input selection sequence . Meanwhile, the enabler 610 allows updating of the first set of closing circuits 616 during the first half of the input selection sequence and the second set of closing circuits 618 during the second half of the input selection sequence. Accordingly, the first and second sets of closure circuits 616 and 618 are updated when they are not being selected for output by the multiplexer 606.

Output without deformation signal According to the present invention, multiplexer 606 of the MDDI 600 series encoder provides an output without deformation signal during the input selection transitions. Figure 8 is an exemplary illustration of output deformation signals that may occur at the output of a multiplexer due to transitions at the selection inputs and / or data inputs. In the example of Figure 8, a multiplexer 802 has four data inputs DO, DI, D2, D3 and two selection inputs SO and SI. A first output deformation signal 804 is due to a transition in the multiplexer selection inputs. In the example, the input selection sequence. { YES, SO} is changing from. { 0,0} to . { l, l} in order to change the multiplexer output DO to D3. However, due to an obliquity delay between the "0 to 1" transitions of SO and SI, the input selection sequence. { YES, SO} briefly take the value. { ? l} for which the DI data entry was incorrectly selected. A deformation signal "0" appears at the output of the multiplexer 802 when the output should remain at "1" throughout the transition. Typically, deformation signals of deformation signal type 804 may occur at the multiplexer output whenever more than one selection input changes values during an input selection transition. Accordingly, to avoid the occurrence of said deformation signals at the output of the multiplexer 606 of the MDDI 600 series encoder, the embodiments of the present invention employ a Gray code input selection sequence. Another type of output strain signal, illustrated as 806 in FIG. 8, occurs due to transitions in the data inputs of the multiplexer. In the example of figure 8, in an input selection cycle, the input selection sequence. { Sl, S ?} change of . { 0,0} to . { ? l} . However, due to the timing obliquity between the selection signals SI, SO and the data signal DO, the data signal DO changes values before the end of this selection period. A deformation signal "0" appears at the output of the multiplexer 802 when the output should remain at "1" throughout the transition. To avoid such deformation signals at the output of multiplexer 606 of the MDDI 600 series encoder, the embodiments of the present invention ensure that the data inputs to the multiplexer remain stable one clock cycle before being used. This is done by delaying the trajectories of the selection inputs to the output of the multiplexer. In addition to the two types of output distortion signal of the multiplexer that are illustrated in FIG. 8, yet another type of output deformation signal may occur at the output of a multiplexer. This type of strain signal, typically caused by a timing imbalance between the internal signals within the same multiplexer, causes the multiplexer to not select input during an input transition. As such, whenever the input transition is between data inputs having the value "1", deformation signals of this type can be seen at the output of the multiplexer. To avoid such deformation signals, the output of multiplexer 606 of the MDDI 600 series encoder is designed so that it remains at "1" along any input transition between data inputs, both with the value "1" at the time. of the transition.

Optimized Output Selection Algorithm The output of multiplexer 606 of the MDDI 600 series encoder is regulated by the following output selection algorithm: Output of the multiplexer = (sn (2) And sn (l) And sn (0) And d (0)) or (sn (2) And sn (l) And s (0) And d (l)) ó (sn (2) And s (l) And sn (0) And d (2)) or (sn (2) And s (l) And s (0) And d (3)) ó (s (2) Y sn (l) Y sn (0) Y d (4)) or (s (2) Y sn ((l) Y s (0) Y d (5)) ó (s (2) And s (l) And sn (0) And d (6)) or (s (2) And s (l) And s (0) And d (7)) or (sn (2) And sn (l) And d (l) And d (0)) or (sn (l) And sn (0) And d (4) And d (0)) ó (sn (2) And s (0) And d (3) And d (l)) or (sn (2) And s (l) And d (3) And d (2)) or (s (2) And sn (l) And d (5) And d (4)) or (s { l) And sn (0) And d (d) And d (2)) or (s (2) Y s (0) Y d (7) Y d (5)) or (s (2) Y s ((1) Y d (7) Y d (6)) where s (n) represents the value of the n-ava selection input of the multiplexer, sn (n) represents the inverse of s (n), and d (k) represents the value of the multiplexer k-ava data entry . For example, in the case of the Gray code input selection sequence of Figure 7, the data entries d (0), d (l), ..., d (7) of the above equation correspond respectively to D7, DO, D2, DI, D6, D5, D3, and D4. As is apparent to a person skilled in the art, the first eight terms of the above equation are related to the selection of the output of the multiplexer. The last eight terms ensure that the internal deformation signals of the multiplexer, as described above, do not appear during the input transitions. Furthermore, having the multiplexer inputs stable and using a Gray code input selection sequence ensures that the other two types of output deformation signal, as described above, do not occur. The previous output selection algorithm is optimized based on an a priori recognition of the input selection sequence of the multiplexer. In other words, due to an input selection sequence, the output selection algorithm is designed to provide a distort signal-free multiplexer output only for input transitions according to the input selection sequence. Accordingly, the output selection algorithm is not related to the provisioning of a strain signal free output for input transitions that are not within the input selection sequence. This design choice of the present invention reduces the number of terms in the output selection algorithm to a necessary minimum. Consequently, the physical size of the multiplexer is also reduced.

Example Timing Diagram Figure 9 is an example timing diagram of the input clock, selection inputs, data inputs, and multiplexer output of multiplexer 606. In the example of Figure 9, the sequence of entry selection. { S2, Sl, S ?} it conforms to the Gray code entry selection sequence illustrated in Figure 7. In Figure 9, it may be noted that the input selection sequence. { S2, S1, S0} changes at each rising or falling edge of the entry clock and that a simple selection entry changes at each transition. The output of the multiplexer is without deformation signal and emits a data byte every four cycles of the input clock. The data bits DO, ..., D7 are exemplary sequences which are used for illustration purposes only and do not necessarily correspond to actual sequences in the execution.

Conclusion Although several embodiments of the present invention have been described above, it should be understood that they have been presented as a way of example only, and not of limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the present invention should not be limited by any of the exemplary embodiments described above, but should be defined solely in accordance with the following claims and their equivalents.

Claims (3)

1. NOVELTY OF THE INVENTION Having described the present invention, it is considered as a novelty and, therefore, the content of the following is claimed as a priority: CLAIMS 1. - A serial encoder of double data transfer rate, comprising: a multiplexer (mux) having a plurality of inputs; a plurality of closing circuits, having data inputs, coupled to the plurality of inputs of the multiplexer; an enabler, coupled to the closing circuits, to allow the closing circuits to update their data inputs; and a counter, coupled to the multiplexer, for selecting one of a plurality of multiplexer inputs for output. 2. - The encoder according to claim 1, characterized in that the multiplexer is a multiplexer N: l having N inputs and an output, where N is an integer power of 23. - The encoder according to claim 1, characterized in that the multiplexer has eight inputs. 4. - The encoder according to claim 1, characterized in that the multiplexer provides an output without deformation signal during the selection input transitions. 5. The encoder according to claim 1, characterized in that the counter provides the multiplexer with input selection values according to a Gray code sequence. 6. The encoder according to claim 5, characterized in that the multiplexer includes an optimized output selection algorithm based on an a priori recognition of the code sequence Gray. 7. The encoder according to claim 6, characterized in that the output selection algorithm provides an output without deformation signal only during the input transitions according to the Gray code sequence, thereby reducing the size of the multiplexer. 8. - An encoder according to claim 7, characterized in that the output selection algorithm selects the output of the multiplexer according to the following: exit = (sn (2) And sn (l) And sn (0) And d (0)) or (sn (2) And sn { l) And s (0) And d (l)) o (sn (2) And s (l) And sn (0) And d (2)) or (sn (2) And s (l) And s (0) And d (3)) ó (s (2) Y sn (l) Y sn (0) Y d (4)) or (s (2) Y sn ((l) Y s (0) Y d (5)) ó (s (2) And s (l) And sn (0) And d (6)) or (s (2) And s (l) And s (0) And d (7)) or (sn (2) And sn (l) And d (l) And d (0)) or (sn (l) And sn (0) And d (4) And d (0)) ó (sn (2) And s (0) And d (3) And d (l)) or (sn (2) And s (l) And d (3) And d (2)) or (s (2) And sn (l) And d (5) And d (4)) or (s (l) And sn (0) And d (5) And d (2)) or (s (2) Y s (0) Y d (7) Y d (5)) or (s (2) Y s ((l) Y d (7) Y d (6)) wherein s (n) represents a bit of an input selection value; sn (n) represents the inverse of s (n); and d (k) represents a bit of an input of the multiplexer. 9. - The encoder according to claim 1, characterized in that the counter changes in an ascending edge or a falling edge of an input clock. The encoder according to claim 9, characterized in that the multiplexer emits a bit on each edge of the input clock. 11. - The encoder according to claim 1, characterized in that only a subset of the closing circuits are updated while another subset of the closing circuits are being selected for output by means of the multiplexer. 12. - The encoder according to claim 5, characterized in that the enabler enables the closing circuits based on the input selection values generated by the counter. 13. - The encoder according to claim 1, characterized in that the encoder receives parallel input data and sends it in serial form on a serial communications link. 14. - The encoder according to claim 1, characterized in that the serial communication link is a Digital Mobile Screen Interface (MDDI) link. 15. A serial encoder, comprising: means for storing a plurality of input bits; means for generating an input selection sequence; and means for serially issuing said plurality of input bits according to said input selection sequence. 16. The serial encoder according to claim 15, further comprising: means for updating the plurality of input bits in said storage means. 17. - The serial encoder according to claim 15, characterized in that said means for emission provide an output without deformation signal during the input transitions in said input selection sequence. 18. - The serial encoder according to claim 15, characterized in that said input selection sequence is a Gray code sequence. 19. - The serial encoder according to claim 18, characterized in that said emission means include an optimized output selection algorithm based on an a priori knowledge of the Gray code sequence. 20. The serial encoder according to claim 19, characterized in that the output selection algorithm provides an output without deformation signal only during the input transitions according to the Gray code sequence. 21. The serial encoder according to claim 17, characterized in that said input transitions occur in either an ascending edge or a falling edge of an input clock. 22. - The serial encoder according to claim 21, characterized in that said means of emission in series emit a bit on each edge of the input clock. 23. A system, comprising: a multiplexer (mux) having a plurality of inputs; a plurality of closing circuits, having data inputs, coupled to the plurality of inputs of the multiplexer; an enabler, coupled to the closing circuits, to enable the closing circuits to update their data inputs; and a counter, coupled to the multiplexer, for selecting one of a plurality of multiplexer inputs for output.