MX170084B - PERIPHERAL CONTROLLER AND INTERFACE ADAPTER - Google Patents
PERIPHERAL CONTROLLER AND INTERFACE ADAPTERInfo
- Publication number
- MX170084B MX170084B MX1388288A MX1388288A MX170084B MX 170084 B MX170084 B MX 170084B MX 1388288 A MX1388288 A MX 1388288A MX 1388288 A MX1388288 A MX 1388288A MX 170084 B MX170084 B MX 170084B
- Authority
- MX
- Mexico
- Prior art keywords
- adapter
- main memory
- dma
- transfer
- data
- Prior art date
Links
Abstract
La presente invención se refiere a en un sistema de computación que comprende un sistema de barra colectora, una memoria principal conectada al sistema de barra colectora, y una pluralidad de dispositivos conectados a dicha barra colectora, el sistema, además, comprende un controlador acoplado al sistema de barra colectora para transferir datos entre cada uno de los múltiples dispositivos periféricos y la memoria principal por medio de operaciones de acceso de memoria directa (DMA) y un adaptador, que tiene una memoria intermedia conectada entre cada uno de los dispositivos periféricos y el controlador; el controlador comprende un controlador de secuencias para responder a una señal de demanda de cada uno de los adaptadores múltiples para generar una solicitud individual DMA para la transferencia DMA de una cantidad limitada de datos entre la memoria principal y el adaptador; y, cada adaptador incluye medios para generar una señal de demanda solamente cuando la memoria intermedia del adaptador preparada para dar servicio a la transferencia DMA de una cantidad limitada de datos, y medios para responder a la solicitud de una transferencia DMA entre la memoria principal y el adaptador para que transfiera dicha cantidad limitada de datos durante dicha solicitud.The present invention relates to in a computing system comprising a busbar system, a main memory connected to the busbar system, and a plurality of devices connected to said busbar, the system, furthermore, comprises a controller coupled to the busbar system to transfer data between each of the multiple peripheral devices and the main memory by means of direct memory access (DMA) operations and an adapter, which has a buffer memory connected between each of the peripheral devices and the controller; the controller comprises a sequence controller to respond to a demand signal from each of the multiple adapters to generate an individual DMA request for the DMA transfer of a limited amount of data between main memory and the adapter; and, each adapter includes means for generating a demand signal only when the adapter's buffer ready to service the DMA transfer of a limited amount of data, and means for responding to the request for a DMA transfer between main memory and the adapter to transfer said limited amount of data during that request.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
MX1388288A MX170084B (en) | 1988-11-21 | 1988-11-21 | PERIPHERAL CONTROLLER AND INTERFACE ADAPTER |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
MX1388288A MX170084B (en) | 1988-11-21 | 1988-11-21 | PERIPHERAL CONTROLLER AND INTERFACE ADAPTER |
Publications (1)
Publication Number | Publication Date |
---|---|
MX170084B true MX170084B (en) | 1993-08-06 |
Family
ID=19742149
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MX1388288A MX170084B (en) | 1988-11-21 | 1988-11-21 | PERIPHERAL CONTROLLER AND INTERFACE ADAPTER |
Country Status (1)
Country | Link |
---|---|
MX (1) | MX170084B (en) |
-
1988
- 1988-11-21 MX MX1388288A patent/MX170084B/en unknown
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