LU80587A1 - DIGITAL FREQUENCY DIVIDING METHOD - Google Patents

Description

D. 5ο.171

----- GRAND-DUCHÉ DE LUXEMBOURG

Brevet N »............. g A ...... 1 7 du .2.S .... nO.V & 5 £) J? & 13.1O yJssM # Monsieur le Ministre de l'Economie Nationale et des Classes Moyennes

Titre délivré: ........................................ jgn ",. . “C ^ aan Service de la Propriété Industrielle

LUXEMBOURG

Demande de Brevet d'invention I. Requête Σί3 SQC · 'tfêt.O dite .: SÏKMEHS BSRXjLÎÎ üîTD IiUiT * · ^ ... CES!?., ..... mtv0.1 ^ haohûrDlatz .... 2 ^ ..A ..... 3ooo KüKICH 2, ..... Allonaçne Fg-3S -.......

... raie, - - uepras snfcâa par .... I-! onsisur J & QgRâÆ. de. J'uy.sert (2> ... sa .... Qualité .... de .... m.andataire ..................... .................................................. .................................................. ...................................... ........

dépose ........ ce ........ VlngtrIRl.it ..... llOv.INêhre ..... 1.9oO .... SC.iXcintC “d ..... ... (3) à ........ 15 ............ .... heures, au Ministère de l'Économie Nationale et des Classes Moyennes, à Luxembourg: 1 . la présente requête pour l'obtention d'un brevet d'invention concernant: ..... "procedure aii.r ._ .. dig-1.talenJErecnienstei.5ung" ........... .................................................. ................_ (4) déclare, en assumant la responsabilité de cette déclaration, que l '(es) ir.ver.teur (s) est (sont):, 1, - 1.1ôl j u.ll.A. t; al ".2 2.1 ,. ä ΙΖ.Ι, .ΙΙγ ^ .. 13 - -3, * ............. (5) ........... ........... ige 3 ZMp.315q .................................. .................................................. .................................................. .................................................. .........

..... 2.- ~ r-? ·? - .;> QQ \ lltl 3, .... 11: .- ôbt.ilj; .A ".. .12, ...... 1 .3 · 3 xCm ..... il.r ....................

..................... 1.1.1 · .- .: ..- ·· Ί.; · '.A: /] a ..... .................................................. .................................................. .................................................. ........

2. la délégation de pouvoir, calée de ....... ". ·; Λ.ν..ΐ | ................................. llo.COCOt ·! ^ .. ..- !!? .........

3. la description en langue ............. ρΛ..ι eNr .'........................ ..... de l'invention en deux exemplaires; 4 ............. 6 ................. planches de dessin, en deux exemplaires; 5. la quittance des taxes versées au Bureau ne l'Enregistrement à Luxembourg, le ...... 2.3 ....- ..: -..- .. 1 :: 3 ..... 15.2.8 .................................................. ...............................................- .. ...........................-...................... ................................

revendique pour la susdite demande de brevet la priorité d'une (des) demandées) de (6) ........................... lé 1 1 h ......................................... dépcsée's) en (7). ..... M 'hZ Al 1.1lin ....................................... .....

le 8b .... ûé · - -: 1 ::: 3 13 1.1 ........... (. 3. E_2.7 13,, 13.3., 8} ,, et.1 e le: ................. (8) ............... 137.7 .......... Cio. , ...... P, 27, 33,% 53..8) ............................... .................................................. .....................................

au nom de J Ί il .g. h O ........................... ..................... ........................----- ----- - ............... .............................. (9) élit domicile pour lui (elle) et, si désigné, pour son msrdsisire, à Luxembourg ......................................

...... 3 5, .1! .................................................. .................................................. ... ............................................... ................................ (] 0) sollicite la délivrance d'un brev al d'invention pour l ' objet décrit et représenté dans les annexes susmentionnées, - · avec ajournement de cette délivrance à .............. · ~ Ί ................ ..... mois.

Le; 1 ......: - 1 * 1 3-3 ...... 1 ........ 1 .....: ......

Π. Pièces-verbal de Dépôt

La susdite demande de brevet d’invention a été déposée su Ministère de l’Économie Nationale et. des Classes Moyennes, Service de la Propriété Industrielle à Luxembourg, en date du:

2E 13? S

? r- - -dmli - '. re à ... .15 ........... heures / ’\ de l'Érc remis Nationale et ei5 Clasoes Moyennes, P- d.

1 / 02K j;: w. : j D, 5ο.171

DEMANDING PRIORITY

^ the patent / ßütfdi / - application

* IN: THE FEDERAL REPUBLIC OF GERMANY

Dated: NOVEMBER 30, 1977

Dated: NOVEMBER 30, 1977

PATENT APPLICATION

in

Luxembourg

Applicant: SIEMENS AKTIENGESELLSCHAFT BERLIN AND MÜNCHEN

Re: "Procedure for digital frequency division".

tr ♦ · * t SIEMENS AKTIENGESELLSCHAFT Our mark

Berlin and Munich VPA 77 P 6801

International Version 5 Digital Frequency Division Procedure

The invention relates to a method for digital frequency division with a division ratio of 7 <1 and a circuit arrangement with a programmable counter to which an input pulse row is fed.

In frequency synthesis, e.g. the carrier generation in TF technology, the task arises to multiply an existing frequency by multiplying by g, e.g. to convert.

This task would be ideal, i.e. free of unwanted secondary waves, solved if the same periods could be counted from N periods of the original frequency f Z. This is not possible if Z is not an integer in N.

So far, therefore, with a frequency divider, an upper Zk 1 Bri / 20.6.1978 * - 2 - VPA 77 P 6801

Foreign version f wave spectrum of the fundamental frequency generated and the Z harmonics are screened out. Known disadvantage of this method is the decreasing energy of higher harmonics with Z and the associated high filter expenditure for suppression of the entire harmonic spectrum in addition to the desired "frequency Z * | j.

The object of the present invention is to create a method for digital frequency division, by means of which frequency division is possible directly without multiplication even in the case of non-integer division ratios, the respectively desired harmonic being obtained with the greatest possible amplitude.

Another object of the present invention is to provide a digital frequency divider for non-integer division ratios.

To solve this problem, the method according to the invention is such that the denominator and numerator of the division ratio are always opposite in terms of even and odd numbers, that a periodic output pulse series is formed from the input pulse series with the aid of gate circuits, so that the narrowest pulse 25 hzw . the narrowest pause of this pulse series is regarded as a unit time value, and that all the pulses and pauses occurring in the output pulse series are single or integer multiples of this time value with regard to their duration E, and that the number of 30 available time values per period is always even, that if the number of time values can only be divided once by two, and an odd harmonic is to be obtained at the output, the period of the output pulse series in the middle of a time interval and 35 in all other cases begins at the beginning, that the - * e h- - 3 - VPA 77 P 6801

Foreign version of the calf periods of the output pulse series are constructed axially symmetrically with respect to one another with regard to their pulse sequence, that furthermore, with an even-numbered counter of the division ratio, the two quarter-periods 5 of each half-period are also formed axially symmetrically to one another, and that with an odd-numbered counter the other quarter of the half-period compared to that first quarter is inverted.

10 This gives a pulse train with the maximum achievable part of the desired harmonics.

In a further embodiment of the invention, the procedure is such that pulses 15, each with a time value width, are added or subtracted at the transitions from pulse to pause in such a way that the secondary waves lying next to the desired harmonics of the output voltage are weakened.

20 As a result, the damping of the secondary waves lying directly next to the desired harmonic can be increased considerably. Frequency generators using this method also require little selection effort. This method is particularly suitable for generating the • 25 primary tertiary group pilot frequency 1552 kHz, which is generated from secondary group carriers 2108 and 2356 kHz by means of the derivative '1552 kHz = ^ »2356 kHz + ^» 2108 kHz.

30 Each frequency division can be multiplied by a fraction | be understood.

Each divider generates an output period lasting N input periods and a desired harmonic can be seen from it. Z = 1, 2 ....

*

V

»- 4 - VPA 77 p 6801

Foreign version

The period of the simplest divider consists of an impulse and a pause. For the fundamental wave with Z = 1, the optimum has been found with the same pulse and pause length, ie a symmetrical square wave voltage.

5

So far, the simple divider has also been used for harmonics with Z> 1, but as the number of harmonics increases, their energy share decreases, and the desired one can only be separated from the neighboring ones with a high level of filtering.

The integrated digital modules offer the option of providing the period N with Z pulses and pauses in order to save filter effort.

15

The ideal pulse sequence with Z pulses and pauses of equal length can only be approximated because Z is not an integer in N.

20 The state of the output can be determined with one or both edges of the square wave voltage of the input. The period consists of N or 2N time intervals that are an entire input period or a half ^ long. For this purpose, impulses or pauses can be selected, 25 which all contain the same spectrum. The maximum of the desired harmonics can be obtained as follows.

= The number of time intervals is chosen to be an even number, which is always possible with both edges.

30 If the number can only be divided once by two and an odd harmonic is desired, the period is left in the middle of a time interval, otherwise it starts with the beginning.

35 The phase angles for the fundamental wave are determined by the period * *% ^ - 5 - VPA 77 P 6801

Foreign versions are measured from the beginning to the middle of each time interval and are to be multiplied by the ordinal number of the harmonics.

5 The time intervals of the first period, the phase angles of which result in positive harmonics for the selected harmonic, are selected as pulses.

The pulse sequence of the second quarter is to be formed corresponding to 10 of the first. Only even-numbered harmonics occur if, starting from the end of the first period quarter ^, the same switching states are present in both quarters. Only odd harmonics occur in different switching states. The second-15th half of the period is symmetrical to the first.

Now an attempt is made to increase the damping of the closest harmonic compared to the desired one. For this purpose, either a single pulse can be added or removed at the beginning and end of each composite pulse. This results in shortenings, extensions or only shifts, the number of connected impulses is retained and the 25 cosine values for the desired and the nearest harmonics are calculated and multiplied by 4 for the time intervals in question in the first period, because - every quarter is to be changed accordingly. For added pulses, the values are added to the original spectrum, for subtracted ones.

30th

The digital frequency divider according to the invention is designed in such a way that the counter can be programmed to a predetermined, repeating cycle of pulse groups, which consist of a number of only whole as well as whole and 35 half pulses, and that for t - 6 - VPA 77 P 6801

Foreign version is caused to count half pulses as a whole, that input pulses are fed to the first input of a gate circuit, and via its second input a signal can be supplied which, in the presence of an In-5 version at the output of the gate, causes the gate output to have the programmable counter is connected and that control signals are supplied to a logic circuit and that the output of the logic circuit is connected to the reset input of the counter, to the input of a first 10 bistable multivibrator and to the inputs of digital dividers for generating the control signals that the one Control signal the group change and the other control signal signals the change from a group with half and full pulses to a group of only 15 pulses and vice versa and that the outputs of the digital divider and the counter are connected to the logic circuit.

These measures have the advantage that the 20 desired harmonics can be generated directly even with non-integer division ratios while at the same time high attenuation of the neighboring undesired harmonics.

The control signal which causes the inversion can preferably be generated at the gate by a further bistable flip-flop stage, the one input of which is controlled by a counter output and the second input of which is controlled by a further inversion stage which is controlled as a function of the control signal.

The logic circuit can consist of an exclusive OR gate of two NAND gates and an inversion gate so that the two control signals are present at the two inputs of the exclusive 0DER-35 gate and its output * * w - 7 - VPA 77 P 6801

Foreign version is connected to one input of the first NAND gate, that the output of the first NAND gate is connected to the input of a second NAND gate, and that the second input of this second NAND gate is connected to the output of an inversion gate connected is.

The first divider for the first control signal consists of two bistable flip-flops, the inverted output of the second flip-flop being connected to the input of the first flip-flop and the set inputs of both flip-flops being connected to an output of the second divider.

15 The second divider consists of two shift registers of the same number of bits, the output (4th stage) of the second shift register being connected to the reset input of the first shift register and the third stage of the first shift register being connected to the input of the first stage of the second shift register.

The invention is explained in more detail with the aid of the block diagram according to FIG. 7 and the diagrams according to FIGS. 1 to 6, 8 and 9.

25th

The correctness of the method according to the invention is proven on the basis of the pulse diagrams according to FIG. 1 and the associated calculations.

30 If a frequency division is followed by a multiplication, a divider would be favorable, which gives the desired harmonic preferentially. The Fourier analysis of a periodically occurring rectangular pulse is assumed. This can be composed of an even or odd number 35 of narrow pulses. Is the * - 8 - VPA 77 P 6801

Foreign version

Pulse duration equal to the pause, the fundamental wave appears with the maximum energy. Only odd harmonics appear. Since the break can also be made up of short breaks, the period can consist of 5 a sum of equal time intervals. The corresponding phase angle lies in the middle of each time interval. Pulses and pauses can be set so that only odd or odd harmonics occur. In both cases, the first half of the period is symmetrical to the second.

The divider should e.g. give the eleventh harmonic of the 62 input periods output period. The shortest time intervals are given by the half-period of a symmetrical square-wave voltage of the input. The corresponding phase angle for the fundamental wave of the output period lies in the middle of each time interval. The phase angles for the eleventh harmonic are eleven times as large and the ones that lie in the first and fourth quadrants result in the selection for the pulse train with the maximum energy of the desired harmonic. At the beginning and end of each pulse so composed, either a pulse that takes a time interval can be added or removed. This results in either an extension, a shortening or just a shift. With the same number of contiguous pulses, a slightly changed pulse sequence can be found, in which the nearest secondary waves, the 9th and 13th harmonics, are further attenuated by 30 without significantly weakening the 11th harmonic.

1 shows an arbitrary semi-periodically axially symmetrical further input pulse width. A = pulse height, 35 p = time value. According to Fourier, the nth harmonic is - 9 - VPA 77 P 6801

Foreign version see iL = ψ S ± ÏU! E.

η π n

Fig. 2 shows a pulse diagram, in which one thinks of the rectangular pulses of the pulse width composed of two pulses. Then according to Fig. 2 j 2λ sin n Sr Aß = —--—- [cos n ïf + ô sin n ^ + cos (-n sin 10 §Ü ,, sin n ® p, sin 2-n § π n 2 π n Λ 2A sin np An ~ π n 15

The following generally applies to an even number g of partial pulses of the same length; Z = g-1 sin n n.

20 A = - ^ --— &. 2.X cos Ζ · η · § = - · sil ^ PB (1) η π n 2: - g η n 'Z = 1.3 ...

Fig. 3 shows a pulse diagram in which the rectangular pulses are thought to be composed of three pulses.

25 2A sin η £

An = --jj— (cos ng + j sin ng + cos-n S + j 2A sin n · § 2 «sin -ng) + --— ^ (cos η = ψ + j sin n ^ + cos -n ^ + 3 sin -η. 2A SlP 2a g 2A Sln n §, 2n 35 ^ η π η π n · 2 cos n ^ * * '* «- 10 - VPA 77 P 6801 αΊ ·„ „£ foreign version 2A sin n 3 Λ / 1.. .. 2όν Αη = π - η 2 (j + cos η ^).

In general, for an odd number of u pulses of equal length, 5 ^ Zi = u-1 ν #! ^ · 2 <2 + ΣΙ cosZngHMiïU * (2)

Zi = 2; 4 ...

10 From FIGS. 1 ... 3 it can be seen that an axis of symmetry can be drawn at the angle π.

With p ^ there is the fundamental wave with the maximum attainable part because sin ^ = 1.

15

There are no even harmonics because the sine is an even multiple of | becomes 0.

A period is formed from an even number z of equal time intervals-20 de Z ^, which can either be an impulse or a pause. A pulse contains an amplitude, a pause -an · There are four time intervals with the phase angles α, ττ-α, - (π-α), - <x if the positive angles from the beginning 0 and the negative ones from En-25 de 2n the period.

From this, a sum amplitude An can be determined with the angle nY. The exponential notation gives: 30

An βχράη'Τ ^ expjna + anexp; 3n (7T-a) + anexp-ôn (TE-cc) + an exp-jna 35 = an (exp ^ na + exp-jna) + an (exp0nn.exp-, ina -exp-jnn «expdna) sr * - 11 - VPA 77 P 6801

International version A 2 cos na + 2 cos n7i * cos na η n

An = 2 cos na (an + an cos ηπ). (3) 5 All harmonics are phase or counter phase with respect to the start of the period. There are only odd harmonics if the amplitudes of α and π-α have different signs. One switching state in the first quarter of the period is followed by the other in the second four-tenth. The halves of the period are symmetrical to each other.

n »odd:

An = 2 cos na cos na 15 n * even;

An = 2 cos na 1 ^ + (- ^) - 13 = 0.

20 There are only even harmonics if the same switching states are available.

62

The invention will now be further explained with the aid of a divider.

25th

The output period is 62 input periods long. It is possible to determine the switching state of the output with every edge of the symmetrical square wave voltage of the input.

30th

With this, 124 possible individual pulses or pauses are to be used to synthesize a pulse sequence with only the eleventh harmonic as the basic frequency.

> «Ψ - 12 - VPA 77 P 6801

Foreign version

The ideal pulse sequence, in which eleven identical output periods result from 62 input periods, can only be approximated.

5 In Fig. 4, the phase angles of the 62 half-waves are numbered through to the half of the period. It is only hinted that this takes place in the second half of the period with a negative sign.

10 For the eleventh harmonic, the angles are eleven times larger than for the fundamental wave. Since 0 and multiples of 2π are identical, it is easy to count through. The angles are retained, only they are now assigned to other half-waves. For example, the angle for the basic

A

15 wave = -gg of the half wave 1 is equal to the angle for the eleventh harmonic of the half wave -25. If a pulse lasted from 1 ... 31 and -1 ... 31, the fundamental wave would be present with the maximum attainable component and its amplitude A, j can generally be calculated from the Fourier analysis 20 of a rectangular pulse, and according to Formula 1.

Z = g-1 A- = sin p = ~ sin Ç «2 cos Z § 1 π * π g Z._ g Z = 1, 3 ...

25 For the amplitude AQ of the nth harmonic: si „„ 2 235 = 1

An = V —Τ '* · 2 Z_ cos Zin 1 30 Z-1, 3 ...

* 2A T3

A1 —- sinp 2A.sinnS, ^ r _____ P

A "= 7— * A ^ = W7 ...... -". n «2 / cos z n ~ n A1 n ^ (sin 2) .27cosZE n ZL · g π g 'Z— g

V

»- 13 - VPA 77 P 6801

Foreign version

Because the angles are preserved, both ^> cos are identical, 2A. sin n |

An = ~ sin P —T§ c n * sin “5 g p: Angular sum of the individual pulses of the first period quarter O ... ^ selected for the pulse train.

10 For § the angle φ can be used for half of the single

S

ses be introduced, A, --sin p & n .. (4) η π * n «sm φ v '15 This formula only applies to the desired harmonic

2A π Sin 11 * T25 2A

= - sin § --- = - 0.987211 11 Tt £ 4 * τι π 11 sin TJ25 20

With this result, the formula to be derived from the pulse sequence and valid for any odd harmonic can be checked, 25 dashed lines were introduced in Fig. 6:

A positive impulse from J ... π and three negative impulses. For example, the pulse with the angle has the same negative pulse with the

Angle π -.

cosn ^ 2? "cosn (π - = cosn: ¾ - (cosnTicosn + 35 + sense T2ÏÏ *"% - 14 - VPA 77 P 6801

International version cos n - cos ηπ cos n = 2 cos n for n »odd number * 0 for η = even number.

5 The following applies to the amplitude at the pulse introduced by J π: 2A sln n? _____ 3π 2Â sln n t ®n * ~ 5 - COS n -¾. = —---- · 10 • cos η (π - 5j)

? A sin n J

= · (Cos η π cos n ^ + sin ηπ sin n 15 2k sin n?, Cos nS_____ - ......— 'cos ηπ π η 1 β, ·· «ν, π 2Α 1 sin η 1 a_ = - ----- cos ηπ η π η 20 aQ = 0 for n = even, because sin n ^ = 0 2A sln nf aQ = —— -2n— because cos η π = -1.

There are no even harmonics.

25th

To calculate the value of the given nth harmonic, the values for the impulses up to J with the factor 4 and the double value for the broad impulse have to be considered, because the second half of the period provides the same proportions.

π ¥ \ - 15 - VPA 77 Ρ 6801

Foreign version V-τ l (sin η -ri5 * cos η τϋ + sin η -Μ 008 η fi + + sin η ^ | j * cos η - 0.25 sin η jf) (5) 5 Α9 * - τρ0.033849048 Α ^ = ^ .0.987211130 10 Α13 = ^ -0.032102377.

In order to increase the attenuation of the auxiliary waves with respect to the fundamental wave, a further corrected pulse series can be created after determining a pulse series in which the desired harmonic is optimally contained, as was shown previously in some examples, as is shown in the pulse diagram according to FIG. 5 shows.

The formula for the corrected pulse series is: 20

An =! Tn (sin n ï! Rcosn îlS + sin n ^ -cos n f | S + + sin n cos n tIS "°» 2 ^ sin n Ψ (6) 25

Ag - 0.013582732 A ^ = 0.964442733- ^ 30 A13 - 0.004575759 ^

The previous examples have been given on the premise that the original input pulse train 35 is symmetrical. In the event that for the original

-V

- 16 - VPA 77 P 6801

Foreign version of the input pulse series asymmetry is present, then an embodiment is also given with reference to Figure 6.

5 The change in the pulse series shown in Fig. 6 is shown by adding or subtracting pulses.

Due to the asymmetry shown, 2 £ wide Im-10 pulses must be added in the first half of the period and subtracted in the second.

For the pulse with the angle cc + 6, there is one pulse each in the three other period quarters.

15

The exponential form gives: expjna expjnS + expjnn exp-jna expjn <5- (exp-jna expjnS + exp-jnn expjna expjn £) = 20 expjnS (expjna + expjnn exp-jna-exp-jna-exp-jna expjna) = expjn <$ [expjna (1-exp-jnn) -exp-jna (1-expjmi)] * expjn $ (1-cos ηπ) (expjna-exp-jna) = 25 (cos n ό + j sin n £) ( 1-cos ηπ) 2 j sin na = 2 (1-cos ηπ) sin na (-sin n <S + j cos n <5).

30 There are no even harmonics, because cos ηπ = 1. Despite asymmetry, spurious waves only appear at twice the frequency spacing of the fundamental frequency.

* k * ♦ - 17 - VPA 77 P 6801

Foreign version

The surcharge for odd multiples is complex.

a ^. ^ .4 si | .....- (- sin n <S + j cos nS) (sin n + sin n 5 (7) a = ££. £ (-sin2nS + d 1 sin2 n $) (sin n + sin n ^). η τι n tL υ <£

The symmetry loss of e.g. 20 dB of the input voltage, i.e. the fundamental wave is ten times larger than the second harmonic, corresponds to an angle S-Φ 15 ag = ~ (0.000051697-j 0.003555146) a11 = ^ (“0.000222376 + d 0.012511628) a13 “(0» ° 0 ° 106826-0 0.005085521).

20th

The 20 dB symmetry attenuation gives the following amplitudes and attenuations compared to the 11th harmonic.

25 | Ag | = ^ .0.014090306 36.7 dB

UJ- ^ * 0.964301528

| a15 | = --0.006912968 42.9 dB

30th

Fig. 7 shows the circuit arrangement with the programmed divider. The counter B, which consists of a 4-bit shift register, is supplied with the input pulses via the exclusive-OR gate A. The outputs of the third and third stages of counter B lead to logic circuit L. This logic circuit consists of two% - 18 - VPA 77 P 6801

Foreign version of NAND gates C, E and an inversion stage D and an exclusive OR gate F. The interconnection of the individual gates is such that the output of the third stage of the counter B with one input of the NAND gate 5 ter C and the output of the fourth stage of counter B is connected to the input of inversion stage D. The second input of the first NAND gate C is driven via the output of the exclusive OR gate F. The outputs of the NAND gate C and the inversion stage D 10 are each led to one of the inputs of the second NAND gate E, the output of this NAND gate having the reset input of the counter B having the input of a first bistable multivibrator H and is connected to the inputs of the digital dividers T1, T2 described in more detail below. The outputs of the two dividers T1 and T2 are also connected to the inputs of the second exclusive OR gate F. The output of the second divider T2 is also passed via a further inversion gate J to the control inputs of a second bistable flip-flop G whose output is connected to the second input of the first exclusive-OR gate A. Another input (clock input) of this second bistable flip-flop G is also connected to the output of the second stage of counter B. A delay element 0 is switched on between the output of the logic circuit L and the inputs (clock inputs) of the first divider T1 in order to delay the activation of this divider T1 compared to the divider T2.

30th

The first divider T1 consists of two further bistable flip-flops K, L, the flip-flops being connected to one another in such a way that the inverted output of the second flip-flop L is connected to a control input of the 35 first bistable flip-flop K, while the% 19 VPA 77 P 6801

Foreign version of non-inverted output of the first further flip-flop K and the inverted output of this flip-flop is each linked to a control input of the second further bistable flip-flop L.

5

The second divider T2 consists of two further 4-bit shift registers, the reset input of the first shift register M with the output of the fourth stage of the second shift register N and the output of the third stage of the first shift register M with the control input of first stage of the second shift register N is connected.

The circuit works as follows.

15

The programmable counter B is programmed so that it can count 2 1/2, 3 and 3 1/2 input pulses. 21/2 and 3 input pulses correspond to a count of 3 and 31/2 input pulses to 4. For 20 programming, two control signals are necessary, one for counting states 3 and 4 and the other for half and full input pulses for the input pulses to be counted responsible is.

25 The cyclical alternation between a pulse group of 2 1/2, 3 1/2 and 3 pulses in a predetermined order enables the realization of a non-integer division factor, which allows the desired harmonic to be extracted with high amplitude, the neighboring harmonics are very strongly damped.

The control signals SI, SII for switching from pulse groups with half pulses to pulse groups with only 35 whole pulses are generated by the frequency components «« ► - 20 - VPA 77 P 6801

Foreign version delivered T1 and T2. The control signal SI indicates the change in the period from, for example, 31/2 to 2 1/2 or 3 pulses, while the control signal SII is decisive for switching groups with half pulses to groups with pure whole pulses.

The first exclusive-OR gate A at the input of counter B always causes an inversion of the input signal when the output of the second bistable multivibrator G changes its output state. In the present case, this change is always triggered by the control pulse applied on the input side, which comes from the second counter stage of counter B, unless inversion stage J blocks the bistable flip-flop. When changing a count with half input pulses to one with only whole ones, the bistable flip-flop G is blocked via the inversion stage J by the control signal SII and thus the In-20 version of the input signal is prevented. The counts 3 and 4, corresponding to 2 1/2 and 3 or 3 1/2 input pulses, are determined via the logic circuit L. The count 3 is recognized via gate C and thus counter B is reset via the reset input. In this case 25, the output of the exclusive OR gate F is at a logic 1, caused by the two control signals SI and SII present at the inputs. The polarity of SI and SII is always opposite.

30 At count 4, the reset pulse is generated via inversion level D. In this case, the gate C is blocked via the exclusive OR gate F (logic 0 at the output). The control signals SI and SII present at the two inputs have the same polarity.

* ψ% - 21 - VPA 77 P 6801

Foreign version

The control signal I is generated by means of a counter circuit consisting of the flip-flops K and L.

This is a divider with the division factor 3: 1 », which is additionally controlled by the counter circuit -5 consisting of the 4-bit shift registers M and N. The counter circuit (M and N) is used to generate the control signal II and is designed as a divider with the division factor 11: 1 (pulse / pause = 3/8). If whole numbers are to be counted (3x3 input pulses), 10 the counter (K and L) is held by the counter circuit (M and N) via its set input to "ln (” 0 ”at the ö output) The input of the dividers (K and L) is preceded by a delay stage 15 fe 0, since the set pulse on the set inputs of the divider (K and L) must already be at H0 "before the positive Edge of the clock is present at the input of this divider.

20 Fig. 8 shows in the first row the input pulses, which are divided into groups of 2 1/2, 3 and 3 1/2 input pulses with a corresponding predefined cycle, whereby for the sake of simplicity not the individual pulses, but only the pulse groups 25 are shown. The desired output pulses, which are obtained at the output of the first bistable multivibrator H and essentially correspond to the number of erase pulses at the reset output of the counter B, are then recorded in the second line, while in the 30 lines 3 and 4 those of the Control signals SI and SII generated by dividers T1 and T2 are shown. The control signal SI is positive, which corresponds to a logical 1, as long as pulse groups of 2 1/2 pulses are present at the input, while for pulse groups of 3 1/2 35 and 3, the control signal SI is negative, which is a logical * À ¥ - 22 - YPA 77 P 6801

See international version 0 corresponds. The control signal SU, on the other hand, is negative as long as pulse groups with half pulses occur at the input of counter B and becomes SI only positive if pulse groups with pure integer-5 pulses, in the present case with three pulses each, appear. From this it can be seen that a 0 is only present at the output of the second exclusive OR gate F if the pulse group occurs with 3 1/2 pulses, because only in this case the two inputs of the second exclusive OR OR gate F are assigned a logical 0. In this case, the NAND gate C is blocked, as described above, so that the counter B can count to 4.

15 Fig. 9 shows a more detailed representation of the pulse diagrams. The first line shows the input pulses at input A1 of the first exclusive OR gate A, while the second line shows the pulse diagram for input A2. In the third row, the output pulses at the first exclusive OR gate A are labeled A3. With each polarity change of the pulses A2, an inversion occurs at the output of the exclusive OR gate A, which results in the half-pulses shown. The fourth line shows the pulse diagram for the output pulses at the second counter stage Q1 of the counter B, while in the fifth line the erase pulses at the output of the NAND gate E are shown. At the end of each counting process of counter B, such an erase pulse is generated. The sixth 30 line shows the output pulses at the first bistable multivibrator H, which result from the reset pulses present at the input of the multivibrator by division 2: 1. The seventh line finally shows the pulse diagram as obtained at the inversion output Q of the first bistable multivibrator K of the divider T1, while * «* - 23 - VPA 77 P 6801

Foreign version in the eighth line receives the diagram for the output of the fourth counter stage Q3 of the first counter M of the second divider T2. This second divider is controlled by its wiring in such a way that first the logical 1 to the third stage is counted in the first count 5 M, then in the second counter N to the fourth stage and since the first counter M is now set to zero, four times the logical 0 in the second counter N is counted. This results in a division ratio of 11: 1 10 with a pulse pause ratio of 8: 3.

7 claims 9 figures

Claims (7)

1, method for digital frequency division hei a division ratio ^ 4. 1 and a circuit arrangement 5 with a programmable numerator, which is supplied with an input pulse series, characterized in that the denominator and numerator of the division ratio with respect to odd and even numbers are always opposite that from the input 10 series of pulses is formed with the aid of gate circuits, a periodic output pulse series, that the narrowest pulse or the narrowest pause of this pulse series is regarded as a unit time value, and that all pulses 15 and pauses occurring in the output pulse series are single or integer multiples with respect to their duration E. of this time value, and that the number of available time values per period is always an even number, that if the number of time values can only be divided once by two and an odd 20 harmonic is to be obtained at the output, the period of the output pulse series is in the middle of one Time stoodes and in all other cases at the beginning that the two half-periods of the output pulse series are built up axially symmetrical to each other with respect to their pulse train, that furthermore, with an even-numbered numerator of the division ratio, the two quarter-periods of each half period are also axially symmetrical to each other, and that in the case of an odd-numbered counter, the other quarter of the half-period is inverted by -30 above the first quarter. 1. VPA 77 P 6801 international version 2. VPA 77 P 6801 foreign version the secondary waves lying next to the desired harmonics of the output voltage are weakened. 2. The method according to claim 1, characterized in that primarily at the transitions from pulse to pause, pulses with one each 35 Time value width are added or subtracted such that * ♦ 4 3. VPA 77 P 6801 foreign version is controlled. 3. Circuit arrangement for carrying out the method 5 according to one of claims 1 or 2, characterized in that the counter (B) on a predetermined, repeating cycle of pulse groups which consist of a number of only whole as well as whole and half pulses, is programmable-10 bar and which is caused to count half pulses as a whole, that input pulses are fed to the first input (1) of a gate circuit (A) and via the second input (2) of which a signal can be supplied which, when present an inversion at the output (3) of the 15 gate (A) causes the gate output (A) to be connected to the programmable counter (B) and that control signals (SI, SIl) are fed to a logic circuit (L) and that the output of the Logic circuit (L) with the reset input of the counter (B), with the input 20 of a first bistable multivibrator (H) and with the inputs of digital dividers (T1, T2) for generating the control signals (SI, SII) is connected that d As a control signal (SI) the group change and the other control signal (SII) the change from a group with 25 half and whole pulses to a group of only whole pulses and vice versa and signaled that the outputs of the digital dividers (T1, T2) as well of the counter (B) are connected to the logic circuit (L). 4. VPA 77 P 6801 international version 4. Digital frequency divider according to claim 3, characterized in that the control signal causing the inversion at the gate (A) is generated by a further bistable flip-flop (G), one input of which has a counter output and the second input of which is a further inversion stage (J) is controlled, which depends on the control signal (SII) * ♦ A 5 · Digital frequency divider according to one of the preceding claims, characterized geke η n -5 that the logic circuit (L) consists of an exclusive OR gate (F), two NAND gates (C, E) and an inversion gate (D) that the two control signals (SI, SII) are present at the two inputs of the exclusive-OR gate (F) and its output is connected to the one input of the first NAND gate (C), that the output of the first NAND Gate (C) is connected to the input of a second NAND gate (E) and that the second input of this second NAND gate (E) is connected to the output of an inversion gate (D) 15. 6. Digital frequency divider according to one of the preceding claims, characterized in that the first divider (T1) for the first 20 control signal (Sl) consists of two bistable flip-flops (KL), the inverted output of the second flip-flop (L) with the input the first flip-flop (K) is connected and the set inputs of both flip-flops (KL) are connected to an output of the second divider (T2). * * Λ * 7. Digital frequency divider according to one of the preceding claims, characterized in that the second divider (T2) consists of two shift registers (MN) of the same number of bits, 5 the output of the second shift register (N) with the reset input of the first shift register (M ) and the stage of the first shift register is connected to an input of the second shift register.