LU502057B1 - Parallel layer assignment method based on via-aware for vlsi - Google Patents

Abstract

The invention relates to a parallel layer assignment method based on via-aware for VLSI. The method puts forward a strategy based on region portioning, which may keep loads in all regions uniform by perception the number of nets in the regions, thus improving the efficiency of the strategy. The method also puts forwards a via optimization strategy, which determines the priority of nets in using routing resources according to the difference in the number of 3D equivalent routing results of nets, thus effectively reducing the number of via of the layer assignment result.

Description

PARALLEL LAYER ASSIGNMENT METHOD BASED ON VIA-AWARE FOR VLSI LU502057

BACKGROUND OF THE INVENTION

[0001] 1. Technical Field

[0002] The invention relates to the technical field of computer-aided design of integrated circuits, in particular to a parallel layer assignment method based on via-aware for VLSI.

[0003] 2. Description of Related Art

[0004] In physical design of VLSI, layer assignment is as an important stage in which each segment in each net is allocated to a proper metal layer. During layer assignment, via are used to connect wires located on different routing layers. The number of via is an important influence factor on the fabrication cost. The fabrication cost will be reduced with the decrease in the number of via. In addition, with the constant increase of the scale of integrated circuits, the number of nets to be processed is increased remarkably, and the increase of the runtime of layer assignment algorithms has become an important constraint restraining the efficient design of routing results. With the development of multi-core processors, the parallel algorithm can make use of the computing capacity of modern processors more efficiently to handle the routing problem of VLSI. The efficiency of the algorithm can be improved by shortening the runtime, and the fabrication cost can be reduced by minimizing the number of via.

BRIEF SUMMARY OF THE INVENTION

[0005] The objective of the invention is to provide a parallel layer assignment method based on via-aware for VLSI to improve the efficiency of a strategy and effectively reduce the number of via of a layer assignment result.

[0006] To fulfill the above objective, the technical solution of the invention is as follows: a parallel layer assignment method based on via-aware for VLSI comprises the | |;500057 following steps:

[0007] S1: a via-oriented layer assignment stage:

[0008] Partitioning a routing region and marking out nets suitable for parallel routing, and performing parallel routing for layer assignment based on the principle of a minimum number of via;

[0009] S2: a negotiation-based via-aware layer assignment stage:

[0010] Sorting, ripping up and rerouting illegal nets appearing in a routing result after S1 by iteration until no illegal net exists, wherein the illegal nets are nets which use overflow edges; and

[0011] S3: a post optimization stage:

[0012] Sorting all nets according to a via optimization strategy, and then ripping up and rerouting the nets one by one; if the number of via is reduced after rerouting, using a new layer assignment result; otherwise, reserving a layer assignment result before net ripping up.

[0013] In one embodiment of the invention, S2 specifically comprises the following steps:

[0014] S21: sorting the illegal nets appearing in a routing result after S1;

[0015] S22: for the illegal nets, partitioning a routing region and marking out nets suitable for parallel routing, and then ripping up and rerouting the nets in parallel; and

[0016] S23: determining whether illegal nets exit in the layer assignment results in S22; if so, sorting the illegal nets, and performing S22 again.

[0017] In one embodiment of the invention, a region partitioning algorithm is used to partition the routing region in S1.

[0018] In one embodiment of the invention, a region partitioning algorithm is used to partition the routing region in S22.

[0019] In one embodiment of the invention, in S21, the illegal nets appearing in | 5902057 the routing result after S1 are sorted according to the via optimization strategy.

[0020] In one embodiment of the invention, the partitioning algorithm is implemented as follows:

[0021] Input: DX, DY

[0022] Output: DX, DY

[0023] (1) initialize DX, DY, iteration, k, m

[0024] (2) loop

[0025] (3) if ((region+regionz) > (regions+regions))

[0026] (4) DY +=k;

[0027] (5) otherwise, DY -= k;

[0028] (6) if ((region+regions) < (regionz+regions))

[0029] (M)DX+=k,

[0030] (8) otherwise, DX -= k;

[0031] = (O)ifiteration<m go loop

[0032] (10) end loop

[0033] Wherein, DX is a vertical demarcation line, DY is a horizontal demarcation line, region, represents the number of nets in the routing region i, iteration is the number of a current iteration, m is an upper bound of iteration, and k is a degree of adjustment for each partitioning, has an initial value set to the upper bound of iteration, and is updated in each cycle according to the following formula:

[0034] k=k—[iteration/a |

[0035] In the formula, & js a constant.

[0036] In one embodiment of the invention, after S1, Nr is set for each net and is calculated according to the following formula:

[0037] Nr = viacount | Nod LU502057

[0038] Wherein, Nod represents a length of the nets in a 2D routing reuslt, viacount represents the number of via of the nets in a 3D routing result, and Nr is a value for evaluating the number of equivalent routing results of the nets; the larger Nr, the greater the number of equivalent routing results of the nets; the smaller Nr the smaller the number of equivalent routing results of the nets.

[0039] In one embodiment of the invention, the via optimization strategy is used in S2 and S3, that is, all the nets are sorted in an increasing order according to Nr of the nets, and routing resources are preferentially used by nets with a smaller Nr .

[0040] In one embodiment of the invention, in S2, as for nets not suitable for parallel routing after the routing region is partitioned, if Nr of the nets is less than an average value of Nr of all the nets, the nets are routed before parallel routing; or, if Nr of the nets are greater than the average value, the nets are routed after parallel routing.

[0041] Compared with the prior art, the invention has the following beneficial effects: the method of the invention puts forward a strategy based on region portioning, which may keep loads in all regions uniform by perception the number of nets in the regions, thus improving the efficiency of the strategy; and the method of the invention also puts forwards a via optimization strategy, which determines the priority of nets in using routing resources according to the difference in the number of 3D equivalent routing results of nets, thus effectively reducing the number of via of a layer assignment result.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0042] FIG. 1 illustrates a grid graph model used in the invention, wherein FIG. 1(a) illustrates a two-layer routing space, FIG. 1(b) illustrates a 3D grid model established according to a routing region in FIG. 1(a), and FIG. 1(c) illustrates a 2D grid model obtained by compressing the 3D grid model in FIG. 1(b).

[0043] FIG. 2 is a flow diagram of a parallel layer assignment algorithm based on | |;500057 via-aware.

[0044] FIG. 3 is a schematic diagram of region partitioning.

[0045] FIG. 4 illustrates a 3D routing result of nets, wherein each point represents 5 a pin, each horizontal line represents a wire, and each vertical line represents via.

DETAILED DESCRIPTION OF THE INVENTION

[0046] The technical solution of the invention will be specifically described below in conjunction with the accompanying drawings.

[0047] The invention provides a parallel layer assignment method based on via-aware for VLSI, comprising the following steps:

[0048] S1: a via-oriented layer assignment stage:

[0049] À routing region is partitioned, nets suitable for parallel routing are marked out, and parallel routing for layer assignment is performed based on the principle of a minimum number of via;

[0050] S2: a negotiation-based via-aware layer assignment stage;

[0051] Illegal nets appearing in a routing result after S1 are sorted, ripped up and rerouted by iteration until no illegal net exists, wherein the illegal nets are nets which use overflow edges;

[0052] S21: the illegal nets appearing in the routing result after S1 are sorted;

[0053] S22: for the illegal nets, a routing region is partitioned, nets suitable for parallel routing are marked out, and then the nets are ripped up and rerouted in parallel,

[0054] S23: whether illegal nets exit in the layer assignment results in S22 is determined; if so, the illegal nets are sorted, and S22 is performed again.

[0055] S3: a post optimization stage:

[0056] All nets are sorted according to the via optimization strategy, and then the nets are ripped up and rerouted one by one; if the number of via is reduced after rerouting, | 502057 a new layer assignment result is used; otherwise, a layer assignment result obtained before net ripping-up is reserved.

[0057] In S1 and S22, a partitioning algorithm is used to partition the routing region, and the partitioning algorithm is shown in Table 1.

[0058] Table 1 “Algorithm 1: region partitioning algorithm “Input DX, DY Output: DX, DY 1: Initialize DX, DY, iteration, k, m 2: loop 3: if ((regionl+region2) > (region3+region4)) 4: DY +=k; 5: otherwise, DY -= k; 6: if ((regionl+region3) < (region2+region4)) 7: DX += k, 8: otherwise, DX -= k; 9: if iteration <m go loop 10: end loop

[0059] DX is a vertical demarcation line, DY is a horizontal demarcation line, region, represents the number of nets in the routing region i, iteration is the number of a current iteration, m is an upper bound of iteration, and k is a degree of adjustment of each partitioning, has an initial value set to the upper bound of iteration, and is updated in each cycle according to the following formula:

[0060] k=k-[iteration/a |

[0061] In the formula, & is a constant. LU502057

[0062] In S21 and S23, the via optimization strategy is used to sort the illegal nets appearing in a routing result after S1 and in the rerouting result in S22.

[0063] After S1, Nr is set for each net and is calculated according to the following formula:

[0064] Nr = viacount / Nod

[0065] Wherein, Nod represents a length of the nets in a 2D routing result, viacount represents the number of via of the nets in a 3D routing result, and Nr is a value for evaluating the number of equivalent routing results of the nets; the larger Nr , the greater the number of equivalent routing results of the nets; the smaller Nr the smaller the number of equivalent routing results of the nets.

[0066] In S3, the via optimization strategy is used, that is, all the nets are sorted in an increasing order according to Nr of the nets, and routing resources are preferentially used by nets with a smaller Nr.

[0067] In S2, as for nets not suitable for parallel routing after the routing region is partitioned, if Nr of the nets is less than an average value of Nr of all the nets, the nets are routed before parallel routing; or, if Nr of the nets is greater than the average value, the nets are routed after parallel routing.

[0068] The specific implementation of the invention is described below.

[0069] 1. Routing region model:

[0070] A grid graph model is used to describe global routing and layer assignment. FIG. 1(a) illustrates a two-layer routing space, the routing region in each layer is partitioned into smaller routing units g-cell, and the task of global routing is to configure wires reasonably to connect the routing units g-cell at different positions. To facilitate the study of a routing result in the layer assignment stage in the global routing process, a 3D grid model shown in FIG. 1(b) is established according to FIG. 1(a). Wherein, each node v represents a routing unit g-cell, and each edge e represents the wire or via connecting 502057 adjacent routing units g-cell. The horizontal edges for connecting the routing units g-cell in the same layer represent wires, and the vertical edges for connecting the routing units g-cell in different layers represent via. The 3D grid model is compressed into a 2D grid model shown in FIG. 1(c). Wherein, nodes v,, and V,, in FIG. 1(b) are compressed into node v, in FIG. 1(c), and edges €, and e;, in FIG. 1(b) are compressed into edge €, in FIG. 1(c). The task of layer assignment is to generate a 3D routing result based on a 2D routing result, a wire is allocated to one of €,, and €,, in a 3D grid according to a routing request at €, , and an allocation result should meet the requirements of a layer assignment strategy.

[0071] 2. Congestion constraints:

[0072] To guarantee routability, the configuration of too many wires on some layers should be avoided during layer assignment, so a layer assignment algorithm follows the following constraints to prevent a routing region against excessive congestion:

[0073] TWO(S“)=TWO(S) (1)

[0074] MWO(S")=| MWO(S)x(2/k) | (2)

[0075] Wherein, 55 represents a given 2D global routing result, and st represents a layer assignment result of S TWO ana MWO represent a total wire overflow and a maximum wire overflow respectively. The two formulas are used in the negotiation-based via-aware layer assignment stage and the post optimization stage to ensure that the total wire overflow of a 3D net routing result is equal to the total wire overflow of a 2D net routing result and the maximum wire overflow of each layer in the 3D net routing result is 2/k of the maximum wire overflow of the 2D net routing result. The first constraint ensures that wire overflows in a 3D routing region will not over wire overflows in a 2D routing region. The second constraint ensures that the maximum wire LU502057 overflow of edges in the 2D routing region is uniformly allocated to corresponding edges in the 3D routing region. When a routing result meets the formulas of the congestion constraints, the congestion of the routing space and the minimization of the number of via > may be handled at the same time in the earlier stage of routing.

[0076] 3. Algorithm summary:

[0077] Layer assignment in this application is designed based on a dynamic planning algorithm. Specifically, the algorithm regards a 2D routing result of each net as a 2D routing tree, and each edge of each 2D routing tree is allocated into a 3D routing space through the dynamic planning algorithm to obtain a 3D routing tree, so as to obtain a 3D routing result.

[0078] FIG. 2 illustrates a flow diagram of a parallel layer assignment algorithm based on via-aware. The parallel layer assignment algorithm based on via-aware comprises three stages: a via-oriented layer assignment stage, a negotiation-based via-aware layer assignment stage and a post optimization stage. Wherein, a parallel layer assignment algorithm based on routing region partitioning is used in the via-oriented layer assignment stage and the negotiation-based via-aware layer assignment stage.

[0079] In the via-oriented layer assignment stage, the algorithm partitions a routing region and nets suitable for parallel routing are marked out first. In this stage, only the number of via of each net is taken into consideration, while the congestion of the routing region is not taken into consideration. After this stage is finished, a net routing result will avoid, to the maximum extent, the generation of via. However, due to the fact that the congestion of the routing region is not taken into consideration in this stage, edges in the 3D routing region may overflow. If the routing result of one net passes through an overflow edge, the net is called an illegal net.

[0080] In the negotiation-based via-aware layer assignment stage, illegal nets are ripped up and rerouted by iteration to reduce overflows in the 3D routing region. | 502057 Meanwhile, in order to effectively reduce the number of via generated after the illegal nets are rerouted, the algorithm sorts all the illegal nets first.

[0081] In the post optimization stage, the algorithm sorts all nets according to a via optimization strategy, and then rips up and reroutes the nets one by one. If the number of via is reduced after rerouting, a new layer assignment result is used. Otherwise, a layer assignment result obtained before net ripping up is reserved.

[0082] 4. Parallel layer assignment strategy based on region partitioning:

[0083] Partitioning of the routing region is extremely critical for the parallel layer assignment algorithm based on region partitioning. If a portioning strategy of the routing region is too complicated, the early-stage preparation cost of the parallel algorithm may be greatly increased, and even the total runtime of the parallel algorithm may be longer than that of a serial algorithm. In addition, the partitioning result has a direct impact on the parallelism of nets. If the numbers of nets in different regions are not equal or the number of nets crossing multiple regions is too large, the efficiency of the parallel layer assignment algorithm based on region partitioning will be reduced.

[0084] A region partitioning method adopted by the parallel layer assignment algorithm is shown in FIG. 3, wherein the solid box represents a global routing region, which is partitioned into four regions 1, 2, 3 and 4 by a horizontal demarcation line and a vertical demarcation line. The vertical demarcation line is referred to as DX, and the horizontal demarcation line is referred to as DY.

[0085] The selection of the position of the demarcation line DX and the position of the demarcation line DY is of great importance. Due to the fact that nets are not uniformly distributed in the global routing region, the number of nets in each region is not determined by the area (routing resource) of this region. If the positions of DX and DY are selected improperly, nets in these regions will be seriously out of balance in number. So,

the parallel layer assignment algorithm adopts a strategy based on net number perception | U502057 to adjust DX and DY to proper positions. An algorithm for adjusting DX and DY is shown in Table 1.

[0086] region, represents the number of nets in a region 7. In the initial adjustment stage of DX and DY, there is a great difference in the number of nets in these regions, and these regions are not equal at this moment. So, DX and DY need to be adjusted by a larger step in the initial stage of iteration to accelerate uniform partitioning of the regions. With the increase of iteration, the numbers of nets in these regions will become uniform gradually, and the adjustment degree should be decreased gradually in the iteration process to more accurately determine the positions of the boundaries that make all regions uniform. The initial value of the adjustment degree À may be set according to the degree of difference in number of the nets in these regions before adjustment or according to the scale of the nets. In this embodiment, the initial value of Æ is set to the upper bound of iteration and is updated in each cycle as follows:

[0087] k=k-[iteration/a | (3)

[0088] iteration is the number of a current iteration. Æ is the degree of adjustment of each partitioning. Œis a constant and is set to the upper bound of iteration in this specification.

[0089] 5. Via optimization strategy:

[0090] In the layer assignment stage, there are generally multiple routing results for one net. FIG. 4(a) and FIG. 4(b) illustrate two nets in a 3D routing space, wherein the net in FIG. 4(a) is called net a, and the net in FIG. 4(b) is called net b. To minimize the number of via of the nets, net a has only one routing result shown in FIG. 4(c); net b has multiple equivalent routing results shown in FIG. 4(d), FIG. 4(e) and FIG. 4(f), and these equivalent routing results of net b may be selected as required. If the routing resource of edge €, is enough for only one wire, the routing resource should be preferentially used LU502057 by net a because net b has other routing results not using edge €, . If the right to use the routing resource is preferentially assigned to net b while the net b selects the routing result in FIG. 4(e), edge €, will no long possess an available routing resource after the net b is routed, so when net a is routed according to the algorithm, edge €, cannot be selected due to wire congestion, and the routing result of net a needs extra via to meet the congestion constrains. If the routing resource is allocated to net a preferentially, the net b still has two feasible routing results in FIG. 4(d) and FIG. 4(e), so the congestion constrains can be met without extra via.

[0091] According to the above routing results, the smaller the number of via of net a, the smaller the layer difference between nodes. Net a has only one optimal routing result; net b has a larger number of via, the layer difference between nodes of net b is large, and net b has multiple equivalent routing results. As can be seen from the above routing results, if nets having more equivalent routing results are routed preferentially, the nets having more equivalent routing results may preempt routing resources from nets with less equivalent routing results, which in turn generate more via.

[0092] How to evaluate the number of equivalent routing results of nets is critical. Obviously, it is not enough to evaluate the number of equivalent routing results of nets merely according to the number of via for a net, and the length of a net in a 2D routing result also needs to be taken into consideration. So, the number of equivalent routing results of a net should be evaluated in terms of both the length of the net and the number of via of the net. Nris set for each net to evaluate the number of equivalent routing results of the net, and Nr is calculated according to the following formula:

[0093] Nr = viacount / Nod (4)

[0094] Wherein, Nod represents a length of the nets in a 2D routing result,

viacount represents the number of via for the nets in a 3D routing result, and Nr isa | 502057 value for evaluating the number of equivalent routing results of the nets; the larger Nr , the greater the number of equivalent routing results of the nets; the smaller Nr the smaller the number of equivalent routing results of the nets.

[0095] To ensure that nets with less equivalent routing results use routing resources preferentially, the algorithm sorts all nets in an increasing order according to Nr of the nets in the negotiation-based via-aware layer assignment stage and the post optimization stage, and then layer assignment is performed.

[0096] After region partitioning, the routing result may generate some nets crossing multiple parallel routing regions, and these nets are not suitable for parallel routing. Due to the fact that Nr of part of the nets not suitable for parallel routing is greater than that of most nets in the parallel routing regions, Nr of the other part of the nets is smaller than that of most nets in the parallel routing regions and the nets not suitable for parallel routing should be routed before or after parallel routing of nets in the parallel routing regions, the order of Nr of all the nets is disrupted in the routing process. So, in order to prevent the order of Nr of all the nets from being disrupted in the routing process, the algorithm divides all the nets not suitable for parallel routing into two groups according to /VF of these nets. Nets with V7 being smaller than an average value are routed before parallel routing, and nets with Nr being larger than the average value are routed after parallel routing.

[0097] The above embodiments are preferred ones of the invention. All variations which are made according to the technical solution of the invention and fulfill functions not beyond the scope of the technical solution of the invention should also fall within the protection scope of the invention.

Claims (9)

Claims LU502057

1. À parallel layer assignment method based on via-aware for VLSI, comprising the following steps: S1: a via-oriented layer assignment stage: partitioning a routing region and marking out nets suitable for parallel routing, and performing parallel routing for layer assignment based on the principle of a minimum number of via; S2: a negotiation-based via-aware layer assignment stage: sorting, ripping up and rerouting illegal nets appearing in a routing result after S1 by iteration until no illegal net exists, wherein the illegal nets are nets which use overflow edges; and S3: a post optimization stage: sorting all nets according to a via optimization strategy, and then ripping up and rerouting the nets one by one; if the number of via is reduced after rerouting, using a new layer assignment result; otherwise, reserving a layer assignment result before net ripping up.

2. The parallel layer assignment method based on via-aware for VLSI according to Claim 1, wherein S2 specifically comprises the following steps: S21: sorting the illegal nets appearing in the routing result after S1; S22: for the illegal nets, partitioning the routing region and overflow edges marking out nets suitable for parallel routing, and then ripping up and rerouting the nets in parallel; and S23: determining whether illegal nets exit in the layer assignment results in S22; if so, sorting the illegal nets, and performing S22 again.

3. The parallel layer assignment method based on via-aware for VLSI according to Claim 1, wherein a region partitioning algorithm is used to partition the routing region in

SL. LU502057

4. The parallel layer assignment method based on via-aware for VLSI according to Claim 2, wherein a region partitioning algorithm 1s used to partition the routing region in S22.

5. The parallel layer assignment method based on via-aware for VLSI according to Claim 2, wherein in S21, the illegal nets appearing in a routing result after S1 are sorted according to the via optimization strategy.

6. The parallel layer assignment method based on via-aware for VLSI according to Claim 3 or 4, wherein the partitioning algorithm is implemented as follows: input: DX, DY output: DX, DY (1) initialize DX, DY, iteration, k, m (2) loop (3) if ((Gegion+region2) > (regionsz+regiony)) (4) DY += k, (5) otherwise, DY -= k; (6) if ((regionitregions) = (regionz+regiony)) (7) DX += k; (8) otherwise, DX -= k; (9) if iteration <m go loop (10) end loop wherein, DX is a vertical demarcation line, DY is a horizontal demarcation line, region, represents the number of nets in the routing region i, iteration is the number of a current iteration, m is an upper bound of iteration, and k is a degree of adjustment for each partitioning, has an initial value set to the upper bound of iteration, and is updated in each cycle according to the following formula:

k =k [iteration / a | LU502057 in the formula, X js a constant.

7. The parallel layer assignment method based on via-aware for VLSI according to Claim 1, wherein after S1, Nr is set for each net and is calculated according to the following formula: Nr = viacount / Nod wherein, Nod represents a length of the nets in a 2D routing result, viacount represents the number of via of the nets in a 3D routing result, and Nr is a value for evaluating the number of equivalent routing results of the nets; the larger Nr , the greater the number of equivalent routing results of the nets; the smaller Nr the smaller the number of equivalent routing results of the nets.

8. The parallel layer assignment method based on via-aware for VLSI according to Claim 7, wherein the via optimization strategy is used in S2 and S3, that is, all the nets are sorted in an increasing order according to Nr of the nets, and routing resources are preferentially used by nets with a smaller Nr.

9. The parallel layer assignment method based on via-aware for VLSI according to Claim 7, wherein in S2, as for nets not suitable for parallel routing after the routing region is partitioned, if Nr of the nets is less than an average value of Nr of all the nets, the nets are routed before parallel routing; or, if Nr of the nets are greater than the average value, the nets are routed after parallel routing.