LU501057B1 - Control of semiconductor switches in a voltage converter circuit arrangement - Google Patents

Abstract

A technique for controlling the semiconductor switches (112; 114) of a circuit arrangement, in particular as a step-down converter (100), step-up converter or flyback converter on a direct current source or on an alternating current source, during a period comprising a fixed period of time (ton) of a magnetization phase (140) and a changeable one Duration (toff) of a demagnetization phase (142) of an inductor (104) is provided. The step-down converter circuit arrangement (100) comprises a first semiconductor switch (112) which is conductive during the magnetization phase (140) and a second semiconductor switch (114) which is conductive during the demagnetization phase (142), the inductor (104), a capacitor (106) in parallel with a electrical consumers (108) and at least one current measuring point (110-1; 110-2) in the current path of one of the semiconductor switches (112; 114). A current value is measured across the current measuring point (110-1; 110-2) during a specified time of the period and compared to a specified reference current value. Depending on the result of the comparison, the duration (toff) of the demagnetization phase (142) is changed.

Description

Control of semiconductor switches of a voltage converter

circuit arrangement

The invention relates to a technique for controlling the semiconductor switches of a

Circuit arrangement for voltage conversion between a power source and an electrical consumer. In particular, a current control method is a

Two-switch step-down converter circuit arrangement provided with current signal information from only one semiconductor switch path.

A step-down converter circuit arrangement 10 with a diode 12 as shown in FIG. 1 is known from the prior art. The buck converter

Circuit arrangement can be on the border (also: border gap, English: "Boundary Conduction Mode", BCM for short) between a non-gap

Operation and intermittent operation of an inductance L (also: choke) are operated in order to achieve low-loss switching of a semiconductor switch (S), with a metal-oxide-semiconductor field effect transistor (MOSFET) usually being used. In this case, the step-down converter circuit arrangement is operated in the vicinity of the gap limit of the inductor current I. in such a way that both a zero current switching (ZCS) and a zero voltage switching (zero voltage switching) ZVS) Turn on the

Semiconductor switch S is made possible. The choke L of the conventional

Step-down converter circuit arrangement and the output capacitance of the

Semiconductor switch Coss form a series resonant circuit. This

Series resonant circuit is within half the period of its

Natural frequency reloaded, so that when the sign of the inductor current IL changes, the output capacitance Coss is doubled to the value of the step-down converter

Input voltage Vin, minus the buck converter output voltage Vout is reloaded. As a result, when the semiconductor switch is switched on again

S the switching voltage as well as the inrush current and thus the switching losses are reduced.

As shown in Fig. 2, the inductor current of the conventional gaps

Step-down converter circuit arrangement during each switching period of the

Semiconductor switch S. The temporal relationships are made up as follows: fon = rss (1), tory = GE-D+ton (2), tres = 10 * JL * Cogs (3).

In order to ensure that the semiconductor switch S switches with as little loss as possible, the period of a switching cycle Ts must not be shorter than:

Tsmin = ton + toss + tres (4).

In particularly loss-optimized applications, a conventional buck converter circuit arrangement with diode 12, as shown in FIG. 1, is replaced by a half-bridge circuit with at least two active ones

Semiconductor switches (S1, S2) are used, as shown in FIG. The

Diode 12 from FIG. 1 replaced by the second semiconductor switch S2. The

The circuit of FIG. 4 can also be used as a full-bridge buck converter

Power factor correction circuitry (in short: "full-bridge buck PFC circuit" with buck converter in English: buck" and

Performance factor correction in English: "power factor correction", short: ,PFC*).

In Fig. 3 is an idealized timing of the control of the

Semiconductor switches S1 and S> according to an idealized lossless circuit

4 for a positive input voltage Vin.

The condition for turning off the first semiconductor switch S1 and the

Switching on the second semiconductor switch Sz is that in this idealized case

Exceeding an upper current threshold In of the inductor current IL Die

Current threshold In is specified by a current controller for the respective operating point of the circuit arrangement.

The condition for turning off the second semiconductor switch S2 and that

Switching on the first semiconductor switch S4 is that in this idealized case

Falling below a lower current threshold li of the inductor current IL. The

current threshold |; is statically specified and ensures that Coss is completely reloaded.

In contrast to the circuit arrangement of FIG. 1, the

Semiconductor switch S2 switched on until a complete reloading of

Coss to zero volts (0V). After that, the first semiconductor S1 is switched on and the second semiconductor switch Sa is switched off at the same time, so that the current IL can commutate from the second semiconductor switch Sa to the first semiconductor switch S1 and the slope of the current becomes positive again.

In the dissertation "Current Mode Control structure: Current-Mode Control:

Modeling and Digital Application” by Jian Li (April 14, 2009, Blacksburg Virginia) is an alternative method for idealized generation of switching times (Ton) of the first semiconductor switch S4 and the second semiconductor switch S2 for the idealized lossless buck converter shown in FIG.

Circuitry described. Fig. 6 (a) shows peak current mode control (PCMC* for short), Fig. 6 (b) shows idealized valley current mode control Fig. 6(c) shows an idealized constant on-time control, Fig. 6(d) shows an idealized constant off-time control time control”) and Fig. 6(e) shows an idealized hysterical

Control ("hysteric control").

The conventional methods for generating the switching signals for

Step-down converter topologies, which are operated with two semiconductor switches, require all the information about the course of the current through the inductance L in order to generate the switching signals with comparators. There are two conventional ones

Ways to do this, each with significant disadvantages.

According to a first conventional switching signal control, the current IL is directly connected to a current measuring resistor (short: measuring resistor; also: shunt*) in

Path from IL measured using a circuit that routes the signal to the

measurement potential. The disadvantage of the first conventional switching signal

control is that the circuitry for isolation is usually very expensive. For example, a Hall measurement is conventionally used. A further disadvantage of the first conventional switching signal controller is that the circuit for potential isolation usually has only a small bandwidth and reproduces the signal in a distorted manner.

According to a second conventional switching signal control, the current is with

Current transformers in the individual switch paths measured using additional circuitry to demagnetize the current transformers and additional circuitry to measure the current bidirectionally. The disadvantage of the second conventional switching signal controller is that the circuit is complex and has many components. Disadvantage of the second conventional

Switching signal control is also that current transformers are usually more expensive than current measuring resistors (also: "shunts").

The invention is therefore based on the object of specifying a technique for controlling the semiconductor switches of a circuit arrangement for voltage conversion between a power source and an electrical consumer in which a

Potential for measurement circuits and/or control circuits (in particular

Control circuits) can be placed on a low-noise potential, such as a negative intermediate circuit voltage. Alternatively or additionally, there is the task of a suitable current measurement with only one

Measuring resistor and / or only a small additional circuit to generate the

To achieve semiconductor switch signals for the semiconductor switch.

The problem is or the problems are solved with the features of the independent claims. Expedient refinements and advantageous developments of the invention are specified in the dependent claims.

Exemplary embodiments of the invention are described below in part

described with reference to the figures.

According to a first aspect, a step-down converter circuit arrangement for the power supply of an electrical load comprises an inductance connected between a first node and a second node, a capacitance connected between the second node and a third node, and a capacitance connected between the second node and the third node in parallel with the capacity switched

DC voltage output for connecting the consumer. The buck converter

Circuit arrangement further comprises an input unit for connecting a current source feeding the step-down converter circuit arrangement, wherein the

Input unit a first pole, which is considered at least in a positive half-wave

Positive pole acts, and a second pole which acts as a negative pole at least in the positive half-wave. The buck converter circuit arrangement further comprises a first semiconductor switch, which is arranged to selectively conductively connect the first pole to the first node, and a second one

A semiconductor switch arranged to selectively conductively connect the first node and the third node via a fourth node. The step-down converter circuit arrangement also comprises at least one current measurement point, which in a the first node, the second

Node and the third node comprehensive current path is arranged behind the third node. The buck converter circuit arrangement also includes a control unit, which is designed to the first

Semiconductor switch for a specified time (ton) a

Magnetization phase of the inductance is conductive at least in the positive half-wave and during a variable period of time (tor).

to switch the demagnetization phase of the inductance non-conductive at least in the positive half-wave, and to switch the second semiconductor switch non-conductive during the specified time duration (ton) of the magnetization phase of the inductance at least in the positive half-wave and during the variable time duration (tor) of the demagnetization phase of the inductivity at least to turn on in the positive half-wave.

The specified duration (ton) of the magnetization phase of the (for example first) inductance is specified for each circuit arrangement of the first, second and third aspect as a function of a specified maximum current through the inductance. Alternatively or in addition, the changeable

Duration (tof) of the demagnetization phase of the (e.g. first)

Inductance for each circuit arrangement of the first, second and third

Aspect depending on a comparison of a predetermined minimum

Current through the inductor and one across the at least one

Current measuring point measurable current changeable.

The step-down converter circuit can also be referred to as a step-down converter circuit.

The power supply of the electrical consumer can be a direct current

Supply and / or include a DC power supply. At least the positive half-wave can be supplied with direct current and/or with

correspond to DC voltage.

Alternatively or additionally, the power supply can be an AC

Include supply and / or an AC voltage supply. The

The AC power supply and/or the AC power supply may include the positive half cycle and a negative half cycle.

The inductor can include a coil and/or a choke.

The capacitance can be a capacitor, in particular one

smoothing capacitor include.

The electrical consumer can also be referred to as a load.

The current measuring point can include a measuring resistor. The

Measuring resistor can also be referred to as current measuring resistor or technically as "shunt". Alternatively or in addition, the current measuring point can include a current transformer (English: "Current Sense Transformer").

Furthermore, as an alternative or in addition, the current measuring point can comprise a Hall sensor and/or an inductive current converter.

The conductive state of each semiconductor switch can also be referred to as closed and/or closed. Alternatively or additionally, the non-conductive state of each semiconductor switch can also be referred to as open.

A combination of a duration, ton, of the magnetization phase of the

Inductance and the changeable period of time, tof, directly following in time, of the demagnetization phase of the inductance can be defined as a period, Tperiod, of the

Circuitry are called.

The fourth node may be grounded and/or connected to a ground.

Examples of the (e.g. buck converter)

Circuit arrangements can enable low-loss switching of the, in particular first and second, semiconductor switches, in particular on the

Boundary (English: "boundary conduction mode", short: BCM) of a gapping

Operation (English: "discontinuous conduction mode", short: DCM) to a non-intermittent operation (English: "continuous conduction mode", short: CCM).

The modification of a conventional (e.g. step-down converter) circuit arrangement can be kept as simple as possible, in particular by adding one or more current measuring points (e.g. one or more measuring resistors) to suitable (preferably particularly low-interference with regard to a reference potential)

locations in the circuit. Alternatively or additionally, one or a few isolated current measurements at the one or more current measuring points at specific times of a period to determine the /

Switching time / s of at least two semiconductor switches are sufficient.

The input unit of the buck converter circuitry feeding

Power source may comprise an AC power source with the first pole acting as a negative pole in a negative half cycle and with the second pole acting as a positive pole in the negative half cycle. The step-down converter circuit arrangement can also have a third semiconductor switch, which selectively conductively connects the fourth node via a fifth node to the first pole, and a fourth semiconductor switch, which connects the fourth node via the fifth

Node with the second pole selectively conductively connects include. The

The control unit can be designed to switch the third semiconductor switch non-conductive and the fourth semiconductor switch conductive during the positive half-wave. The control unit can also be designed to turn on the third semiconductor switch and the fourth during the negative half-wave

Semiconductor switch to switch non-conductive. The control unit can also be designed to during the specified period of time (ton) of

Magnetization phase in the negative half-wave the first

Semiconductor switch non-conductive and to switch the second semiconductor switch conductive. The control unit can also be designed to, during the changeable time period (tor) of the demagnetization phase in the negative

Half wave the first semiconductor switch conductive and the second

Semiconductor switch to switch non-conductive.

According to a second aspect, a step-up converter

Circuit arrangement for the power supply of an electrical consumer connected between a first node and a second node inductance, a connected between a third node and a fourth node capacitance, and between the third

Node and the fourth node connected in parallel to the capacity

DC voltage output for connecting the consumer. The

The step-up converter circuit arrangement also includes an input unit for connecting a step-up converter circuit arrangement that feeds

Current source, wherein the input unit has a first pole, which acts as a positive pole at least in a positive half cycle, and a second pole, which acts as a negative pole at least in the positive half cycle. The step-up converter

The circuit arrangement further comprises a first semiconductor switch which is arranged to selectively conductively connect the first pole to the first node; a second semiconductor switch arranged to switch the first

selectively conductively connect the node and the fourth node through a fifth node and a sixth node; a third

A semiconductor switch arranged to selectively conductively connect the second node and the third node; and a fourth

A semiconductor switch arranged to selectively conductively connect the second node and the fifth node. The step-up converter

The circuit arrangement also includes at least one current measuring point, which in one comprises the fourth node and the fifth node

Current path and / or the fourth semiconductor switch and the fifth node comprehensive current path is arranged. The step-up converter

Circuit arrangement also includes a control unit, which is designed to function as a buck converter for the step-up buck converter

Circuit arrangement the first semiconductor switch during a specified

Duration (ton) of a magnetization phase of the inductance at least in the positive half-wave conducting and during a variable time duration (torr) of a demagnetization phase of the inductance at least in the positive half-wave

To switch half-wave non-conductive, in the function as step-down converter, the second semiconductor switch during the specified period of time (ton).

Magnetization phase of the inductance, at least in the positive half-cycle, is non-conductive and during the variable time period (tor) of

To turn on the demagnetization phase of the inductance at least in the positive half-wave, and in the function as a step-down converter the third

To switch semiconductor switch conductive and to switch the fourth semiconductor switch non-conductive.

The control unit is also in a function as a step-up converter

Step-up converter circuit arrangement is designed to conduct the first semiconductor switch and the second at least in a positive half-wave

Semiconductor switch to switch non-conductive, wherein the control unit in the

Function as a step-up converter is also designed to the fourth

Semiconductor switches during the specified time period (ton) of

Magnetization phase of the inductance at least in the positive half-wave conductive and during the variable period of time (tor) of

To switch the demagnetization phase of the inductance non-conductive at least in the positive half-wave, and in the function as a step-up converter the third

Semiconductor switches during the specified time period (ton) of

Magnetization phase of the inductance, at least in the positive half-cycle, is non-conductive and during the variable time period (tor) of

To switch demagnetization phase of the inductance at least in the positive half-wave conductive.

The step-up converter circuit arrangement can also be referred to as a step-up converter (also in English: “buck-boost converter”).

The power supply of the step-up converter circuitry can be a

DC power source and / or include a DC voltage source. The positive

Half-wave can be a positive DC source and/or a positive

correspond to DC voltage source.

Alternatively or additionally, the power supply of the step-up converter

Circuit arrangement an AC power source and / or

Include AC voltage source. The AC power source and/or the

AC voltage source can have the positive half cycle and a negative one

be assigned half-wave. In the negative half-wave, the first pole can dem

Negative pole corresponding and the second pole to the positive pole.

The input unit of the step-up converter circuitry feeding

Power source may comprise an AC power source with the first pole acting as a negative pole in a negative half cycle and the second pole acting as a positive pole in the negative half cycle. The step-up converter

Circuit arrangement can further comprise a fifth semiconductor switch, which selectively conductively connects the sixth node to the first pole, and a sixth semiconductor switch, which selectively conductively connects the sixth node to the second pole. The control unit can be designed to switch the fifth semiconductor switch non-conductive and the sixth semiconductor switch conductive during the positive half-wave. The

Control unit can also be designed to during the negative

Half-wave conducting the fifth semiconductor switch and the sixth

Semiconductor switch to switch non-conductive.

The control unit is designed to function as a step-down converter during the specified period of time (ton) of the magnetization phase in the negative half-wave, making the first semiconductor switch non-conductive and the second

To switch semiconductor switch conductive. The control unit can also be designed to function as a step-down converter during the changeable

Duration (tor) of the demagnetization phase in the negative half-wave to switch the first semiconductor switch conductive and the second semiconductor switch non-conductive.

The control unit can also be designed to function as a

Boost converter during the specified time period (ton) of

Magnetization phase in the negative half-wave the first

Semiconductor switch non-conductive and to switch the second semiconductor switch conductive. The control unit can also be designed to switch the first semiconductor switch non-conductive and the second semiconductor switch conductive in the function as step-up converter in the negative half-wave.

According to a third aspect, a flyback converter circuit arrangement for powering an electrical load comprises a first inductance and a second inductance, the first inductance and the second inductance being inductively coupled, the first inductance and the second inductance being galvanically isolated, and the second inductance to a first

node is connected. The flyback circuitry further includes one between the first node and a second

Node-connected capacitance and one connected between the first node and the second node in parallel with the capacitance

DC voltage output for connecting the consumer. The flyback

Circuit arrangement further comprises an input unit for connecting a current source feeding the flyback converter circuit arrangement, wherein the

Input unit a first pole, which is considered at least in a positive half-wave

Positive pole acts, and a second pole which acts as a negative pole at least in the positive half-wave. The flyback converter circuit arrangement further comprises a first semiconductor switch which is arranged to selectively conductively connect the first inductor to the second pole at least in the positive half-cycle, and a second semiconductor switch which is connected between the second

Node and the second inductance is arranged to the second

To connect inductance and capacitance either conductively. The flyback

The circuit arrangement also includes at least one current measuring point, which in one comprises the first semiconductor switch and the current source

Current path and / or in the second node and second

Semiconductor switch comprehensive current path is arranged. The flyback

Circuit arrangement also includes a control unit, which is designed to the first semiconductor switch during a specified period of time (ton) a

Magnetization phase of the first inductor and the second inductor conductive and during a variable period of time (tor) one

to switch the demagnetization phase of the first inductor and the second inductor non-conductive, and to switch the second semiconductor switch non-conductive during the fixed period (ton) of the magnetization phase of the first inductor and the second inductor at least in the positive half-wave and during the variable period of time (tor) the demagnetization phase of the first inductance and the second inductance at least in the positive

to switch half-wave conductive.

The flyback converter circuit arrangement can also be referred to as a "flyback converter".

The power supply of the flyback converter circuitry can be a

DC power source and / or include a DC voltage source. The positive

Half-wave can be a positive DC source and/or a positive

correspond to DC voltage source.

Alternatively or additionally, the power supply of the flyback converter

Circuit arrangement an AC power source and / or

Include AC voltage source. The AC power source and/or the

AC voltage source can have the positive half cycle and a negative one

be assigned half-wave. In the negative half-wave, the first pole can dem

Negative pole corresponding and the second pole to the positive pole.

The input unit of the flyback converter circuit feeding

Power source may comprise an AC power source with the first pole acting as a negative pole in a negative half cycle and the second pole acting as a positive pole in the negative half cycle.

According to a first embodiment of the third aspect with

AC source, the flyback converter circuit arrangement can also have a third semiconductor switch, a fourth semiconductor switch, a fifth

Semiconductor switch and a sixth semiconductor switch, wherein the third

Semiconductor switch is configured to selectively connect the first inductor to the first pole, wherein the fourth semiconductor switch is configured to selectively connect the first inductor to the second pole, wherein the fifth semiconductor switch is configured to selectively connect the first semiconductor switch to the second pole to connect, and being the sixth

Semiconductor switch is arranged to selectively connect the first semiconductor switch to the first pole.

According to the first embodiment of the third aspect with

AC source, the control unit can be designed to the third

Semiconductor switch and the fifth semiconductor switch each during the specified period of time (ton) of the magnetization phase in the positive

Half-wave conducting and during the variable time period (torr) of

To switch the demagnetization phase of the positive half-wave non-conductive, and to switch the third semiconductor switch and the fifth semiconductor switch non-conductive during the negative half-wave. The control unit can also be designed to control the fourth semiconductor switch and the sixth

To switch the semiconductor switch non-conductive during the positive half-wave, and to switch the fourth semiconductor switch and the sixth semiconductor switch conductive during the specified time duration (ton) of the magnetization phase in the negative half-wave and not during the variable time duration (torr) of the demagnetization phase of the negative half-wave -to switch conductive.

According to a second embodiment of the third aspect with

AC source, the flyback converter circuit arrangement further comprise a third inductor and a third semiconductor switch, wherein the third

Semiconductor switch is designed to selectively connect the third inductance to the first node and the second node.

According to the second embodiment of the third aspect with

AC source, the control unit can be designed to the second

Semiconductor switch to turn non-conductive during the negative half-wave. The

Control unit can also be designed to switch the third semiconductor switch during the positive half-wave and during the defined time period (ton) of the magnetization phase of at least the first inductance in the negative

half-wave non-conductive and during the variable time period (tor) of

Demagnetization phase at least the first inductance of the negative

to switch half-wave conductive.

The duration ton of the magnetization phase can be constant for each of the circuit configurations according to the invention as a function of a maximum current through the inductance, for example for a

Operating time of the (e.g. buck converter) circuit arrangement can be set for an electrical load and/or for an operating point of the respective (e.g. buck converter) circuit arrangement.

Alternatively or additionally, tor, tofiset, torr + toffset and/or a minimal

Current through the inductances of the circuitry depend on tolerances of individual components and/or delays in drivers.

One or each of the semiconductor switches of one or each circuit arrangement can be a MOSFET, in particular an n-channel MOSFET, a bipolar

transistor, a thyristor and/or an insulated gate bipolar transistor

Electrode (IGBT) include.

The control unit of one or each circuit arrangement can also be configured to operate the circuit arrangement in continuous operation (CCM), discontinuous operation (DCM), and/or on a boundary between continuous and discontinuous operation (BCM). .

The CCM may include average current control.

The at least one current measuring point of one or each circuit arrangement can include at least one measuring resistor.

The at least one current measuring point of one or each circuit arrangement can be arranged in the current path of the first semiconductor switch. the

The control unit can also be designed to measure at least one current value during the magnetization phase in the positive half-cycle and/or in the negative half-cycle across the at least one current measuring point.

The at least one current value can include exactly one current value at a specified point in time of the magnetization phase, preferably at the start of the magnetization phase and/or in the vicinity of a

Switching time from the non-conductive to the conductive state of the first

semiconductor switch.

Alternatively or additionally, the at least one current measuring point of one or each circuit arrangement can be arranged in the current path of the second semiconductor switch. The control unit can also be designed to measure at least one current value during the demagnetization phase in the positive half-wave and/or in the negative half-wave via the at least one current measuring point.

Alternatively or additionally, the at least one current measuring point can have two

Current measuring points, one in each case in the current path of the first semiconductor switch (S1) and one in the current path of the second semiconductor switch (Sz) include described.

The control unit of one or each circuit arrangement can also be designed to turn on at least one or each semiconductor switch in a voltage-free state and/or in a current-free state of the inductance.

The de-energized state is also referred to as "zero voltage switching" (ZVS for short). Alternatively or additionally, the de-energized state is also referred to as "zero current switching" (ZCS for short).

The control unit of one or each circuit arrangement can have a digital

signal processor (DSP), a microcontroller with control software, a field

Programmable Gate Array (FPGA), and/or an application specific

Integrated circuit (ASIC) include. The application-specific built-in

A circuit is also referred to as an "application-specific integrated circuit" (ASIC for short).

According to a fourth aspect, a method for controlling the

Semiconductor switches of a circuit arrangement during a

Magnetization phase and a demagnetization phase provided an inductance. The method can be carried out by means of a circuit arrangement according to the first, second and/or third aspect.

The method comprises the step of measuring a current value across at least one current measurement point of one of the circuit arrangements of the first, second and/or third aspect, the current value during a specified point in time of a period which has a specified length of time (ton).

Magnetization phase and a variable time period (torr) a

Includes demagnetization phase of an inductance is measured. The defined duration (ton) of the magnetization phase of the inductance is in

Defined as a function of a predetermined maximum current through the inductance. The method also includes the step of comparing the measured current value with a value specified for the time of the measurement

reference current value. The method further includes the step of changing the variable time duration (tor) of the demagnetization phase of the inductance in

Dependence on a result of comparing the measured one

current value with the reference current value.

The invention is explained in more detail below with reference to the drawings using preferred exemplary embodiments.

Show it:

Fig. 1 shows a first schematic embodiment of a conventional buck converter circuit arrangement with a

semiconductor switch and a diode;

FIG. 2 shows an idealized current curve through the inductance and an idealized voltage curve across the semiconductor switch of the conventional buck converter circuit arrangement of FIG. 1;

3 shows an idealized current curve through the inductance and an idealized voltage curve across a semiconductor switch of the conventional buck converter circuit arrangement of the following FIG. 4;

4 shows a second schematic exemplary embodiment of a conventional buck converter circuit arrangement with two

semiconductor switches;

5 shows a third schematic exemplary embodiment of a conventional buck converter circuit arrangement with two

semiconductor switches;

6 idealized current curves through the inductance and idealized

Voltage curves across a semiconductor switch of the conventional buck converter circuit arrangement of FIG. 5;

7A and 7B show a schematic exemplary embodiment of a step-down converter circuit arrangement according to the invention

Direct current source during a magnetization phase or a demagnetization phase, wherein the inventive

Step-down converter circuit arrangement comprises two semiconductor switches and at least one measuring resistor;

8A to 8D show a schematic exemplary embodiment of a step-down converter circuit arrangement according to the invention

Alternating current source during a positive half-wave (FIGS. 8A and 8B) and during a negative half-cycle (FIGS. 8C and 8D) and in each case a magnetization and demagnetization phase, the step-down converter circuit arrangement according to the invention having four

comprises semiconductor switches and at least one measuring resistor;

9A to 9H show a schematic exemplary embodiment of a step-up converter circuit arrangement according to the invention

AC source used as a step-up converter (FIGS. 9A to 9D) and as a step-down converter (FIGS. 9E to 9H), the step-up converter circuit arrangement according to the invention comprising six semiconductor switches and at least one measuring resistor;

10A and 10B show a schematic first exemplary embodiment of a flyback converter circuit arrangement according to the invention

AC source during a positive half cycle (Fig. 10A) and during a negative half cycle (Fig. 10B) and one each

On and demagnetization phase, wherein the inventive

Flyback converter circuit arrangement according to the first

Embodiment includes five semiconductor switches in the circuit of a first inductor and a semiconductor switch in the circuit of a second inductor and at least one

measuring resistor in one of the two circuits;

11A and 11B show a schematic second exemplary embodiment of a flyback converter circuit arrangement according to the invention

AC source during a positive half cycle (Fig. 10A) and during a negative half cycle (Fig. 10B) and one each

On and demagnetization phase, wherein the inventive

Flyback converter circuit arrangement according to the second

Embodiment at least one semiconductor switch in

Circuit of a first inductor and each include a semiconductor switch in the circuit of a second and third inductor and at least one measuring resistor in one of the circuits.

12 shows an exemplary current curve for the inductance and the two

Semiconductor switch of the step-down converter circuit arrangement of FIGS. 7A and 7B, the duration (tor) of the demagnetization phase being variable due to a lower reference current; and

13 shows an exemplary method for controlling the semiconductor switches of the buck converter circuit arrangement of FIGS. 7A and 7B.

In the following exemplary embodiments, at least one

Current measuring point used at least one measuring resistor. Each of the

As an alternative or in addition, exemplary embodiments can also be any other

Use an example of a current measuring point (e.g. a Hall sensor).

7A and 7B show a buck converter according to the invention

Circuit arrangement 100 connected to a direct current source with a positive pole 102-1 and

Negative pole 102-2 is connected. The buck converter circuit arrangement 100 comprises a first semiconductor switch (S1) 112, which during a

Magnetization phase 140, shown in FIG. 7A, of an inductance 104 conducting and during a demagnetization phase 142, shown in FIG. 7B, of

Inductor 104 is non-conductive. A second semiconductor switch (Sz) 114 can be electrically conductively connected to the inductance 104 via a first node 122 during the demagnetization phase 104.

The control of the semiconductor switch positions for the buck converter

Circuit arrangement 100 of FIGS. 7A and 7B can be summarized as follows:

The inductor 104 is electrically conductively connected via a second node 124 to an electrical consumer 108 and to a capacitance 106 connected in parallel to the electrical consumer 108 up to a third node 126 . About a fourth node 128 they are electrical

Consumer 108 and the capacity 106 optionally with the second

Semiconductor switch (S2) 114 and the negative pole 102-2 of the direct current source can be connected.

The circuit of the two semiconductor switches 112; 114 is from a

Control unit 150 controlled depending on a measured current value.

The current value is optionally measured via a first measuring resistor 110-1 or a second measuring resistor 110-2. Above the first

Measuring resistor 110-1, the current value can optionally during the

Magnetization phase 140 and the demagnetization phase 142 are measured. The current value can only be measured via the second measuring resistor 110 - 2 during the magnetization phase 140 .

The buck converter circuit arrangement 100 of FIGS. 7A and 7B can optionally only have the first measuring resistor 110-1 or the second

Include sense resistor 110-2.

8A, 8B, 8C and 8D show a step-down converter according to the invention

Circuit arrangement 100, which is connected to an alternating current source with a first pole 102-1 and a second pole 102-2. The buck converter

Circuit arrangement 100 of FIGS. 8A to 8D includes all elements of

buck converter circuitry 100 of Figs. 7A and 7B, and the first

Semiconductor switch (S1) 112 and the second semiconductor switch (S2) 114 can be switched accordingly during a positive half-wave.

The buck converter circuit arrangement 100 of FIGS. 8A to 8D includes two further semiconductor switches (Ss) 116 and (S4) 118, which function as pole converters, in particular as rectifiers, of the AC power source.

In Fig. 8A and 8B, the current paths during the magnetization phase 140 of the inductance 104 and during the

Demagnetization phase 142 of the inductance 104 is shown.

In Fig. 8C and 8D, during a negative half cycle, the current paths of the

Magnetization phase 144 of the inductor 104 and during the

Demagnetization phase 146 of the inductance 104 is shown.

The control of the semiconductor switch positions for the buck converter

Circuit arrangement 100 of FIGS. 8A to 8D can be summarized as follows:

Step-down converter, AC power source, switch positions

half wave | Magnet. phase positive On Conductive | non- non- | Conductive

Leading Leading

From Non- Conductive

Conductive Negative To Non- Conductive Conductive | Not-

Leading Leading

From Executive | Not-

Conductive

The measuring resistor 110-1 leads in every half cycle and every

magnetization phase 140; 142; 144; 146 electricity. The measuring resistor 110-2 only leads in the magnetization phase 140; 144 every half wave

Electricity. A third measuring resistor 110-3 of the step-down converter circuit arrangement 100 arranged on the AC source only carries current when the second semiconductor switch (Sz) 114 is switched on, ie in the

Demagnetization phase 142 of the positive half-wave and in the ... magnetization phase 144 of the negative half-wave.

The circuitry of the four semiconductor switches 112; 114; 116; 118 is controlled by a control unit (not shown) depending on a measured current value across at least one of the measuring resistors 110-1; 110-2; 110-3 controlled.

The buck converter circuit arrangement 100 of FIGS. 8A to 8D can optionally have only the first measuring resistor 110-1, only the second measuring resistor 110-2, only the third measuring resistor 110-3, or a subset of two of the three

gauge resistors 110-1; 110-2; 110-3.

9A through 9H show a step-up converter circuit arrangement 200 which is connected to a first pole 102-1 and a second pole 102-2 of an AC power source. The step-up converter circuit arrangement 200 comprises six semiconductor switches (S1; So; Sa; Sa; Ss; Se) 112; 114; 116; 118; 202; 204, the

Via multiple nodes 122; 124; 126; 128; 130; 132 optionally with the

Inductance 104, the AC source, and the electrical load 108 and parallel capacitance 106 can be electrically conductively connected.

In Fig. 9A to 9D are the current curves for the use of the step-up converter

Circuit arrangement 200 as a step-up converter during the

Magnetization phase 140 and the demagnetization phase 142 in the positive half-wave and during the magnetization phase 144 and the

Demagnetization phase 146 shown in the negative half-wave.

Controlling the semiconductor switch positions for the buck converter

Circuit arrangement 200 of FIGS. 9A to 9D as a step-up converter can be summarized as follows:

Step-up converter as step-up converter, AC source,

Switch positions phase positive Open Conductive | non- | non- | Leading | non- | Conductive

Leading | Leading Leading

From Executive | Non- Conductive Negative To Non- | Leading | non- | Leading | Leading | Not-

Leading Leading Leading

From Executive | Not-

Conductive

The third semiconductor switch (S3) 116 and the fourth are thus used as step-up converters of the step-up converter circuit arrangement 200

Semiconductor switch (S4) 118 for switching between magnetization phase 140; 144 and demagnetization phase 142; 146. The first, second, fifth and sixth semiconductor switches (S1) 112, (Sz2) 114, (Ss) 202 and (Se) 204 are used as step-up converters in the step-up converter circuit arrangement 200 as pole rectifiers, in particular as rectifiers for switching between positive and negative half-wave.

When used as a step-up converter of the step-up converter circuit arrangement 200, in each magnetization phase 140; 144 by the first

Measuring resistor 110-1 current, and in each demagnetization phase 142; 146 through the second measuring resistor 110-2 current.

In Fig. 9E to 9H are the current curves for the use of the step-up converter

Circuit arrangement 200 as a step-down converter during the

Magnetization phase 140 and the demagnetization phase 142 in the positive half-wave and during the magnetization phase 144 and the

Demagnetization phase 146 shown in the negative half-wave.

Controlling the semiconductor switch positions for the buck converter

Circuit arrangement 200 of FIGS. 9E to 9H as a step-down converter can be summarized as follows:

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step-up converter as step-down converter, AC power source,

switch positions

half wave | Magnet.- | S1 S2 S3 Sa Ss Se phase positive Open Conductive | non- | Leading | non- | non- | Leading Leading Leading | Conductive

From non- | Conductive Conductive Negative On Non- | Leading Leading | Not-

Leading Leading

From Executive | Not-

Conductive

The first semiconductor switch (S1) 112 and the second one are therefore used as step-down converters in the step-up converter circuit arrangement 200

Semiconductor switch (S2) 114 for switching between magnetization phase 140; 144 and demagnetization phase 142; 146. The Fifth and Sixth

Semiconductor switches (Ss) 202 and (Se) 204 are used when used as step-down converters in the step-up step-down converter circuit arrangement 200 as pole rectifiers, in particular as rectifiers for switching between the positive and negative half-wave.

When used as a step-down converter of the step-up converter circuit arrangement 200, in each magnetization phase 140; 144 and everyone

demagnetization phase 142; 146 current through the second sense resistor 110-2.

The two measuring resistors 110-1; 110-2 are shown by way of example only. Analogous to the step-down converter arrangement 100 of FIGS

be provided circuit diagram.

The step-up converter circuit arrangement 200 connected to a

Alternating current source can be used as a boost-buck converter circuit arrangement 200 by limiting it to one (for example the positive) half-wave

Can be read connection to a DC power source, in which the fifth and sixth semiconductor switches (Ss) 202 and (Se) 204 by a galvanic

Separation and a conductive connection are substituted for the choice of the positive half-cycle and vice versa for the choice of the negative half-cycle.

10A and 10B show a first embodiment of a flyback converter

Circuit arrangement 300 with connection to an AC power source during the positive or negative half-wave. The flyback converter circuit arrangement 300 comprises two circuits which are inductively coupled via a first inductance 104 and a second inductance 302 . The first inductor 104 is selectively connected to the poles 102-1 via a first semiconductor switch (S1) 112; 102-2 of the AC power source.

In the first exemplary embodiment, the second inductance 302 is the flyback converter

Circuit arrangement 300 optionally via a second semiconductor switch (Sa) 114 to an electrical load 108 and a parallel connected

Capacity 106 connected.

Controlling the semiconductor switch positions for the first

10A and 10B can be summarized as follows:

Flyback converter (1st embodiment example), AC power source,

Switch positions phase positive Open Conductive | non- | Leading | non- | Leading | Non- Conductive Conductive Conductive

From non- | Leading | Non- Non- Conductive Conductive Conductive Negative On Conductive | non- | non- | Leading | non- | Conductive

Leading | Leading Leading

From non- | Leading Non- Non-

Leading Leading Leading

In the first exemplary embodiment, the first semiconductor switch (S1) 112 and the second semiconductor switch (Sz) 114 are thus used for switching between

magnetization phase 140; 144 (current flow in the left circuit of the

10A and 10B) and demagnetization phase 142; 146 (current flow in each case in the right-hand circuit of FIGS. 10A and 10B).

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The four other semiconductor switches (Ss) 116, (Sa) 118, (Ss) 202 and (Se) 204 act in the first exemplary embodiment of the flyback converter circuit arrangement 300 together as a pole converter, in particular as a rectifier.

In the first embodiment of FIGS. 10A and 10B, the flyback converter

Circuit arrangement 300 flows through the first measuring resistor 110-1 im

circuit of the first inductor 104 and the AC source during each magnetization phase 140; 144 electricity. while everyone

demagnetization phase 142; 146 flows through the second measuring resistor 1102-2 in the circuit of the second inductor 302, the electrical

Consumer 108 and the capacity 106 current.

11A and 11B show a second embodiment of a flyback converter

Circuit arrangement 300 with connection to an alternating current source during the positive or negative half-wave. The flyback converter circuit arrangement 300 comprises two circuits which are inductively coupled via a first inductance 104 and a second inductance 302 or a third inductance 304 .

The first inductance 104 is selectively connected to the poles 102-1 via a first semiconductor switch (S1) 112; 102-2 of the AC power source.

The second inductance 302 is selective via a second semiconductor switch (S2) 114 and the third inductance 304 is selective via a third

Semiconductor switch (Ss) 116 in the second exemplary embodiment of the flyback converter

Circuit arrangement 300 is connected to an electrical consumer 108 and a capacitance 106 connected in parallel.

Controlling the semiconductor switch positions for the second

Embodiment of the flyback converter circuit arrangement 300 of FIGS. 11A and 11B can be summarized as follows:

flyback converter (2nd embodiment example),

AC power source, switch positions

half wave | Magnet. phase positive On Conductive | non- | Not-

Leading | Conductive

From non- | Conductive Conductive Negative On Conductive | non- | Not-

Leading | Conductive

From Non- Conductive

Conductive

In the first exemplary embodiment, the first semiconductor switch (S1) 112 is used to switch between the magnetization phase 140; 144 (current flow

In each case in the left-hand circuit of FIGS. 11A and 11B in the positive and negative half-wave). The second semiconductor switch (Sz) 114 is used for

Switching between magnetization phase 140 and

Demagnetization phase 142 during the positive half-wave (current flow in the right-hand circuit of FIG. 11A). The third semiconductor switch (Ss) 116 is used for

Switching between magnetization phase 144 and

Demagnetization phase 146 during the negative half cycle (current flow in the right-hand circuit of FIG. 11B).

In the second embodiment of Figs. 11A and 11B flows through the first

Inductance 104 is alternating current, and the selectively conducting circuit of the second inductance 302 and third inductance 304 acts as a pole converter, in particular as a rectifier.

In the second embodiment of FIGS. 11A and 11B the flyback converter

Circuit arrangement 300 flows through the first measuring resistor 110-1 im

circuit of the first inductor 104 and the AC source during each magnetization phase 140; 144 electricity. while everyone

demagnetization phase 142; 146 flows through the second sense resistor 1102-2 in the circuit of the second inductor 302 during the positive

Half-wave or the third inductance 304 during the negative half-wave, the electrical load 108 and the capacity 106 current.

A flyback converter circuit arrangement 300 connected to a

DC source can be selected according to the choice of a half-wave of the first or second embodiment, for example, by each of the first semiconductor switch (S1) 112 and the second semiconductor switch (S2) 114 to

Switching between the magnetization phases are used. The other

Semiconductor switch (Ss) 116, as well as the other in the first embodiment

Semiconductor switches (S4) 118, (Ss) 202 and (Ss) 204 can each be replaced by specified circuitry, for example according to FIG

Switching in the positive half cycle of the tables above.

In the following, for each exemplary embodiment, the step-down converter

Circuit arrangements 100 are described with a direct current source according to FIGS. 7A and 7B and with an alternating current source according to FIGS. 8A to 8D.

In the exemplary embodiment, the buck converter circuit arrangement 100 is operated at the boundary gap (English: “Boundary Conduction Mode”, or “BCM” for short). The time ton for magnetizing the inductance (L) 104 is kept proportional to the power and is specified by a voltage regulator which is intended to keep the output voltage of the circuit, for example across the electrical load 108, constant.

The time tor for demagnetizing the inductance (L) 104 is in the

Exemplary embodiment of the step-down converter circuit arrangement 100 set.

For example, a zero current signal

Detection", short: ZCD) generated, which is conventionally generated by the

Charge reversal of a diode 12 is caused.

In a buck converter circuit arrangement 100 (also: buck converter

Topology), in which the function of the diode 12 is implemented by a semiconductor switch 114, however, ZCD cannot be generated without a controller 150, since the semiconductor switch 114 does not block by itself.

In a preferred embodiment, the time at which the second

Semiconductor switch 114 should switch off, determined (for example calculated) in advance (for example before the end of a changeable period of time tor of the demagnetization phase, at the end of which the second semiconductor switch 114 is switched off) and the determination (for example calculation) by measuring and/or controlling (in particular rules ) of the current, in particular by means of a

Measuring resistor 110-1, 110-2 or 110-3 at a fixed point in time within a period of one magnetization phase and one demagnetization phase.

The duration tor of the demagnetization phase, in which the first semiconductor switch is open and the second is closed, is conventionally determined according to formula (2).

The conventional determination may differ from an actual one due to tolerances and other factors such as delays in drivers

Lead current value in the inductor (L) 104 compared to a predetermined current value of an ideal lossless buck converter circuit arrangement 100.

It will thus be checked which actual current value was reached in the inductance (L) 104 at the end of the demagnetization phase.

The required information of the current can, for example, from the

Current path of the semiconductor switch (S2) 114 of FIGS. 7A and 7B can be used. A measuring voltage which is proportional to the current through the semiconductor switch 114 can be generated with the aid of the measuring resistor 110 - 1 .

Alternatively or additionally, by means of the measuring resistor (for example referred to as “shunt R1” in FIGS. 7A and 7B) 110-2 in the current path of the first

Semiconductor switch (S1) 112 a current value during the period ton of

Magnetization phase of the inductance 104 are measured. In the

Embodiment of Fig. 7A is the semiconductor switch (S1) 112 during the

Duration ton of the magnetization phase at a positive input voltage

Vin connected to positive pole 102-1 and negative pole 102-2.

The arrangement of the first measuring resistor 110-1 and/or the second

Measuring resistor 110-2 between the electrical load 108 and the

Negative pole 102-2 and/or near one connected to node 128

Grounding can also be referred to as a “Low Side Path” arrangement.

12 shows an example of a measured current curve through the inductance 104 of the step-down converter circuit arrangement 100 of FIGS. 7A and 7B with a positive input voltage Vin with a time-controlled curve comprising the fixed time duration (ton) 1202 of the magnetization phase, variable

duration (torr) 1204-1; 1204-2; 1204-3 the demagnetization phase and the resulting period (Tperiod) 1206-1; 1206-2; 1206-3 and a corresponding change (tofset) 1208 (also: settling time, time correction and/or

Actuator of a current controller for correcting the current limit) of the changeable

durations.

The information necessary to be able to correct the lower current threshold 1214 is contained in the current through a measuring resistor, for example

Sense resistor 110-2 in the current path of the first semiconductor switch 112 of FIG. 7A. The current 1210 flows through the first semiconductor switch 112 during the magnetization phase (ton) 1202. The current 1214 at the time am

At the beginning of the magnetization phase, it should be kept constant at a (for example negative) reference value (Irer) 1218 . It is therefore advantageous, for example, to have the stream 1210 as close as possible to the

Switching time from the demagnetization phase to

to measure the magnetization phase.

The solid line lv at reference numeral 1210 designates the current through the first semiconductor switch 112, which in the magnetization phase (ton) 1202 corresponds to the current through the inductance (L) 104. During the demagnetization phase 1204-1; 1204-2; 1204-3 the current IL am flows

Numeral 1212 through the inductor (L) 104 and the second

Semiconductor switch 114.

ler (t-1) at reference number 1216-1 denotes the measured current error two switching cycles ago, and ler at reference number 1216-2 the last measured current error.

The measured (also read) current value 1214 is fed into the controller 150, for example a DSP or microcontroller, to determine the

Duration tor of the demagnetization phase and/or the period duration Tperiod.

Fig. 13 shows an embodiment of a method for controlling the

semiconductor switch 112; 114 of the buck converter circuit arrangement 100 of FIGS. 7A and 7B during a magnetization phase and a

Demagnetization phase of an inductor 104.

The method can be controlled by the control unit 150, for example comprising a

DSP and/or microcontroller. Alternatively or in addition, the method can be referred to as a rule structure.

With the help of the control unit 150, for example a DSP, from the

Information on the input voltage (Vin) 1302 and output voltage (Vout) 1304, which is compared at reference number 1312 with a reference output voltage (Vout_rer) 1306, and a (e.g. proportional-integral) controller 1318, which sets or determines the duration ton of the magnetization phase, a period Tperiod VOrcalculated (for example at reference number 1316 and/or according to formula (2) added to ton), with which the current IL through the inductance 104 would have to reach the lower current threshold 1218.

After the period has ended, both semiconductor switches 112 and 114 are off, and a short time later the first semiconductor switch (S1) 112 is switched on again.

The measuring resistor 110-2 (also: shunt R1) is current-carrying, and the current value 1214 is measured directly after the switching of the first semiconductor switch (S1) 112. If the measured current value 1214 at the reference sign 1314 deviates from the reference current value 1218, a current controller (also: "lbux controller"

or “Ip controller” for short) 1320 enters a deviation toftset, which is added to the previously calculated period at reference number 1322. The time period T period one

period at reference numeral 1322 and the duration ton der

Magnetization phase at reference number 1324 are at reference number 1326 of a pulse wave modulation (English: "pulse width modulation", short:

PWM) supplied, which the semiconductor switches (e.g. 112 and 114 im

Embodiment of the step-down converter circuit arrangement of FIGS. 7A and 7B), in particular at high frequency, controls.

The current value 1214 approaches the reference current value 1218 at the measurement time of the next period (also: in the next pulse). The current controller 1320 adjusts the current 1214 in the measuring point to the reference current 1218. As

Reference current value 1218 becomes the lower one according to FIG. 12, for example

limit value of the (e.g. triangular) inductor current IL 1210; 1212 used.

The timing of the measurement of the current value 1214 described above is merely an example. The procedure can be used at any other point

current edge, for example current edge 1210, by adjusting a determination of reference current value 1218.

By means of a different choice of reference current value, for example

Average current can be regulated.

For example, the buck converter circuitry 100 in a

average current as a reference current in continuous operation (CCM).

Alternatively or additionally, for example using a

Current transformer and / or by flipping the reference potential, for example, the ground shown at node 128 in Fig. 7A and 7B, a

Current measurement by the second semiconductor switch (Sz) 114 can be used, for example as input value 1214 in the method of Fig. 13.

For example, the (e.g. triangular) current 1210; 1212 can be measured by the inductance 104. Due to a permanent current flow, in particular both in the magnetization phase and the demagnetization phase in Fig. 7A and 7B, the use of the measuring resistor 110-1 can result in higher losses than when using the measuring resistor 110-2, which is only in the

magnetization phase of FIG. 7A is live.

8A through 8D show a generalization of the buck converter circuit 100 for an AC power source, also known as a buck converter as a bridgeless PFC

Topology” can be designated.

In the positive half-wave shown in FIGS. 8A and 8B, according to the

Step-down converter circuit 100 of FIGS. 7A and 7B current values can be measured either via the measuring resistor 110-2 during the magnetization phase 140 or through the measuring resistor 110-1 during the entire period. Alternatively or additionally, one or more current values during the demagnetization phase 142 at a measuring resistor 110-3 im

Current path of the second semiconductor switch (S2) 114, or via (not shown)

Current transformers in the current paths of the first semiconductor switch (S1) 112 and/or the second semiconductor switch (S2) 114 are measured.

The semiconductor switches (Ss) 116 and (S4) 118 in Figs. 8A to 8D serve as

Pole changers and are switched on alternately depending on the polarity of the input voltage.

With a positive input voltage, the fourth semiconductor switch (Sa) 118 is switched on and the regulation and functionality of the semiconductor switches (S1) 112 and (S2) 114 behaves as described for the positive DC source.

With a negative input voltage, the fourth semiconductor switch (Sa) 118 is turned off and the third semiconductor switch (Siz) 116 is turned on. The second semiconductor switch (S2) 114 is now switched on in order to be able to magnetize the inductance 114 at reference number 144, and the semiconductor switch (S1) 112 is switched on for the demagnetization phase 146.

With a negative input voltage, the current direction through the measuring resistor 110-2 (also: shunt R1) is more positive than the current direction with a negative input voltage

input voltage reversed. In this case, a specified point in time of the measurement must be different (e.g. compared to a positive

DC source) do not change. The current measured by the measuring resistor 110-2 (also: shunt R1) shows the current through the inductance during the magnetization phase 140 of the positive half-cycle in FIG. 8A and/or the magnetization phase 144 of the negative half-cycle in FIG. 8C.

A reference potential (English: "ground", short: GND) can be used in the buck converter

Circuit arrangement 100 of FIGS. 8A to 8D to the negative contact

Supply voltage are placed, which can describe, for example, the neutral conductor.

In order to use the usually lower-interference potential of the measuring resistor 110-1 (also: shunt R3) and the capacitance 106, the

Current information about the measuring resistor 110-1 (also: shunt R3) can be used. A possible downside of current measurement across the

Measuring resistor 110-1 is that the four semiconductor switches (S1, S2, Ss and Sa) 112, 114, 116 and 118 must all be driven in an electrically isolated manner.

The circuit complexity is therefore lower for the reference potential shown near the measuring resistor 110-3 (also: shunt R4).

If the current information of the measuring resistor 110-3 (also

shunt R4), the time of measurement depends on the polarity. The second

Semiconductor switch (Sz) 114 leads to the positive input voltage

Demagnetizing current 142 and with a negative input voltage

Magnetization current 144. The current direction through the measuring resistor 110-3 (also: shunt R4) is independent of the polarity of the supply voltage.

The method for controlling the semiconductor switches of a circuit arrangement during a magnetization phase and a demagnetization phase of an inductance 104 can be used for other circuit arrangements, for example the step-up converter and flyback converter circuit arrangements 200 or 300 of FIGS. 9A to 9H, FIGS. 10A and 10B and FIG. 11A and 11B.

For each circuit arrangement 100; 200; 200, a changeable period of time, for example tor of the demagnetization phase, can be adjusted (also: corrected) by means of the method. The method is particularly suitable for

circuit arrangements (also: topologies) 100; 200; 300, which can be switched quasi-resonantly. The method can, for example,

Flyback converter circuit arrangements 300, in particular with a pole rectifier (for example a rectifier or synchronous rectifier) at

Step-up converter circuitry 200 with a second

Semiconductor switch (S2) 114 instead of a diode, with step-down converter

Circuit arrangements 100 as described here and in boost converter

Circuit arrangements (English: "Boost Converter" or "Step-up Converter") are used.

The control of the step-up converter circuitry 200 as

Boost converter circuit arrangement with direct current source and/or

Alternating current source can also refer to the circuit diagrams of the German

Patent applications 102020117180.3, boost converter for a

Power supply of an electrical consumer and power supply and

Method for step-up conversion of the input voltage in a

Power supply of an electrical consumer”, 10 2020 120 530.9 “Boost converter circuit arrangement, power supply and method for

Step-up conversion of an input voltage” and 102020126471.2, Boost converter circuit arrangement, power supply and method for

Step-Out of an Input Voltage” can be applied.

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As can be seen from the above exemplary embodiments, the switch arrangements according to the invention 100; 200 and 300 a low-loss

Switching the semiconductor switches at a stable, for example negative,

share of electricity can be achieved. In particular, a period of time

Be fixed magnetization phase and a period of time

Demagnetization phase as a function of the, for example negative,

Current share can be changed. In particular, the, for example negative,

Share of current across a measuring resistor to one or a few predetermined

Points in time during a period comprising an up and

demagnetization phase are measured.

Although the invention has been described in terms of exemplary embodiments, those skilled in the art will appreciate that various

Modifications can be made and equivalents can be used as substitutes. Furthermore, many modifications can be made to adapt a particular situation or material to the teachings of the invention. Consequently, the invention is not limited to that disclosed

exemplary embodiments, but includes all exemplary embodiments that fall within the scope of the appended claims.

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Reference List

Conventional Buck Converter Circuitry 10

diode 12

Step-down converter circuit arrangement 100

First pole of current source 102-1

Second pole of current source 102-2

Inductor 104

Capacity 106

Load / electrical consumer 108

current measuring point, optional measuring resistor or shunt 110-1; 110-2; 110-3

First semiconductor switch (S1) 112

Second semiconductor switch (Sz) 114

Third semiconductor switch (Ss) 116

Fourth semiconductor switch (Sa) 118

First node 122

Second node 124

Third node 126

Fourth node 128

Fifth node 130

Sixth Node 132

Current path, positive half-wave, magnetization phase 140

Current path, positive half-wave, demagnetization phase 142

Current path, negative half-wave, magnetization phase 144

Current path, negative half-wave, demagnetization phase 146

control unit 150

Step-up converter circuit arrangement 200

Fifth semiconductor switch (Ss) 202

Sixth semiconductor switch (Se) 204

Flyback circuit arrangement 300

Second inductance 302

Third inductor 304

Fixed duration ton of the magnetization phase 1202

variable duration gate of the depletion phase 1204-1; 1204-2; 1204-3

period T period 1206-1; 1206-2; 1206-3

Change tortset FROM torr, Tperiod 1208

Current through first semiconductor switch (S1) 1210

Current through second semiconductor switch (Sz) 1212

Measured lower current value 1214

Deviation of the lower current value from the reference current value 1216-1; 1216-2

Reference current value 1218

Input voltage (Vin) 1302

Output voltage (Vout) 1304

Reference output voltage (Vout ref) 1306

Comparison of voltage values 1312

Comparison of current values 1314

Equation 1316

Proportional integral controller (PIl controller) 1318

Current regulator 1320

Timer (or timer) of the period 1322

Timer (or timer) of the magnetization phase 1324

PWM output 1326

Claims (16)

patent claims 1. Step-down converter circuit arrangement (100) for the power supply of an electrical load (108), comprising: an inductance (104) connected between a first node (122) and a second node (124); a capacitance (106) connected between the second node (124) and a third node (126); a DC voltage output connected in parallel with the capacitance (106) between the second node (124) and the third node (126) for connecting the load (108); an input unit for connecting a current source (102) feeding the buck converter circuit arrangement (100), the input unit having a first pole (102-1) which acts as a positive pole at least in a positive half-wave, and a second pole (102-2), which acts as a negative pole at least in the positive half-wave; a first semiconductor switch (112) arranged to selectively conductively connect the first pole (102-1) to the first node (122); a second semiconductor switch (114) arranged to selectively conductively connect the first node (122) and the third node (126) through a fourth node (128); at least one current measuring point (110-1; 110-2; 110-3) which is arranged downstream of the third node (126) in a current path comprising the first node (122), the second node (124) and the third node (126). is; and a control unit (150) which is designed to conduct the first semiconductor switch (112) during a fixed period of time, ton, a magnetization phase of the inductance (104) at least in the positive half-cycle and during a variable period of time, tor, one to switch the demagnetization phase of the inductance (104) non-conductive at least in the positive half-wave, and to switch the second semiconductor switch (114) non-conductive during the specified time period, ton, the magnetization phase of the inductance (104) at least in the positive half-wave and during the variable Duration, tor, of the demagnetization phase of the inductor (104) to switch it on at least in the positive half-wave; wherein the specified length of time, ton, of the magnetization phase of the inductor (104) is specified as a function of a predetermined maximum current through the inductor (104); and wherein the changeable duration, tor, of the demagnetization phase of the inductor (104) depends on a comparison of a predetermined minimum current through the inductor (104) and a current across the at least one current measuring point (110-1; 110-2; 110-3) measurable current is changeable. 2. Step-down converter circuit arrangement (100) according to claim 1, wherein the current source (102) feeding the input unit comprises an alternating current source, the first pole (102-1) acting as a negative pole in a negative half-cycle, the second pole (102-2 ) acts as a positive pole in the negative half-wave; wherein the step-down converter circuit arrangement (100) also has a third semiconductor switch (116) which selectively conductively connects the fourth node (128) to the first pole (102-1) via a fifth node (130), and a fourth semiconductor switch (118) selectively conductively connecting the fourth node (128) to the second pole (102-2) via the fifth node (130); wherein the control unit (150) is designed to switch the third semiconductor switch (116) non-conductive and the fourth semiconductor switch (118) conductive during the positive half-wave; wherein the control unit (150) is designed to switch the third semiconductor switch (116) conductive and the fourth semiconductor switch (118) non-conductive during the negative half-wave; wherein the control unit (150) is designed to switch the first semiconductor switch (112) non-conductive and the second semiconductor switch (114) conductive during the specified period of time, ton, of the magnetization phase in the negative half-wave; and wherein the control unit (150) is designed to switch the first semiconductor switch (112) conductive and the second semiconductor switch (114) non-conductive during the variable time duration, tor, of the demagnetization phase in the negative half-wave. 3. Step-up converter circuit arrangement (200) for the power supply of an electrical load, comprising: an inductance (104) connected between a first node (122) and a second node (124); a capacitance connected between a third node (126) and a fourth node (128); a DC voltage output connected in parallel with the capacitance (106) between the third node (126) and the fourth node (128) for connecting the load (108); an input unit for connecting a current source (102) feeding the step-up converter circuit arrangement (200), the input unit having a first pole (102-1) which acts as a positive pole at least in a positive half-wave, and a second pole (102-2), which acts as a negative pole at least in the positive half-wave; a first semiconductor switch (112) arranged to selectively conductively connect the first pole (102-1) to the first node (122); a second semiconductor switch (114) arranged to selectively conductively connect the first node (122) and the fourth node (128) through a fifth node (130) and a sixth node (132); a third semiconductor switch (116) arranged to selectively conductively connect the second node (124) and the third node (126); a fourth semiconductor switch (118) arranged to selectively conductively connect the second node (124) and the fifth node (130); at least one current measuring point (110-1; 110-2), which is arranged in a current path comprising the fourth node (128) and the fifth node (130) and/or the fourth semiconductor switch (118) and the fifth node (130). is; and a control unit (150) which is designed to conduct the first semiconductor switch (112) during a specified period of time, ton, a magnetization phase of the inductor (104) at least in the positive half-wave in a function as a buck converter of the boost-buck converter circuit arrangement (200). and during a variable period of time, to, of a demagnetization phase of the inductor (104), at least in the positive half-wave, to switch the second semiconductor switch (114) non-conductive during the specified period of time, ton, of the magnetization phase of the inductor (104 ) non-conductive at least in the positive half-wave and conductive during the variable period of time tor, the demagnetization phase of the inductor (104) at least in the positive half-wave, to switch the third semiconductor switch (116) conductive in the function as step-down converter and the fourth switching semiconductor switches (118) non-conductive; wherein the control unit (150) in a function as step-up converter of the step-up converter circuit arrangement (200) is also designed to switch the first semiconductor switch (112) conductive and the second semiconductor switch (114) non-conductive at least in a positive half-wave, the Control unit (150) in its function as a step-up converter is also designed to conduct the fourth semiconductor switch (118) during the specified period of time, ton, the magnetization phase of the inductance (104) at least in the positive half-wave and during the variable period of time, tor, of the demagnetization phase of the inductance (104) non-conductive at least in the positive half-wave, and in the function as step-up converter the third semiconductor switch (116) during the defined period of time, ton, the magnetization phase of the inductance (104) non-conductive at least in the positive half-wave and during the variable period of time, torr, of the demagnetization phase of the inductance (104) to switch it on at least in the positive half-wave: the specified period of time, ton, of the magnetization phase of the inductance (104) depending on a predetermined maximum current through the inductance (104 ) is fixed; and wherein the changeable duration, tor, of the demagnetization phase of the inductor (104) depends on a comparison of a predetermined minimum current through the inductor (104) and a current across the at least one current measuring point (110-1; 110-2; 110-3) measurable current is changeable. 4. Step-up converter circuit arrangement (200) according to claim 3, wherein the current source (102) feeding the input unit comprises an alternating current source, the first pole (102-1) acting as a negative pole in a negative half cycle, the second pole (102-2 ) acts as a positive pole in the negative half-wave: the step-up converter circuit arrangement (200) also having a fifth semiconductor switch (202) which selectively conductively connects the sixth node (132) to the first pole (102-1), and a sixth semiconductor switch ( 204) selectively conductively connecting the sixth node (132) to the second pole (102-2); wherein the control unit (150) is designed to switch the fifth semiconductor switch (202) non-conductive and the sixth semiconductor switch (204) conductive during the positive half-wave; 44 / 51 LU501057 wherein the control unit (150) is designed to switch the fifth semiconductor switch (202) conductive and the sixth semiconductor switch (204) non-conductive during the negative half-wave; wherein the control unit (150) is designed to switch the first semiconductor switch (112) non-conductive and the second semiconductor switch (114) conductive during the defined period of time, ton, of the magnetization phase in the negative half-wave in the function as step-down converter; wherein the control unit (150) is designed to switch the first semiconductor switch (112) conductive and the second semiconductor switch (114) non-conductive during the variable time duration, tor, of the demagnetization phase in the negative half-wave in the function as step-down converter; wherein the control unit (150) is designed to switch the first semiconductor switch (112) non-conductive and the second semiconductor switch (114) conductive during the defined period of time, ton, of the magnetization phase in the negative half-wave in the function as step-up converter; and wherein the control unit (150) is designed to switch the first semiconductor switch (112) non-conductive and the second semiconductor switch (114) conductive in the function as step-up converter in the negative half-wave. 5. flyback converter circuit arrangement (300) for the power supply of an electrical load, comprising: a first inductor (104) and a second inductor (302), wherein the first inductor (104) and the second inductor (302) are inductively coupled, wherein the first inductance (104) and the second inductance (302) are galvanically isolated, and wherein the second inductance (302) is connected to a first node (112); a capacitance (106) connected between the first node (122) and a second node (124); a DC voltage output connected in parallel with the capacitance (106) between the first node (122) and the second node (124) for connecting the consumer (108); an input unit for connecting a flyback converter The current source (102) feeding the circuit arrangement (300), the input unit having a first pole (102-1) which acts as a positive pole at least in a positive half-wave, and a second pole (102-2) which acts as a negative pole at least in the positive half-wave acts, has; a first semiconductor switch (112) which is arranged to selectively conductively connect the first inductance (104) to the second pole (102-2) at least in the positive half cycle; a second semiconductor switch (114) disposed between the second node (124) and the second inductance (302) for selectively conductively connecting the second inductance (302) and the capacitance (106); at least one current measuring point (110-1; 110-2), which is arranged in a current path comprising the first semiconductor switch (112) and the current source (102) and/or in a current path comprising the second node (124) and the second semiconductor switch (114). is; and a control unit (150) which is designed to conduct the first semiconductor switch (112) during a fixed period of time, ton, a magnetization phase of the first inductor (104) and the second inductor (302) and during a variable period of time, tor to switch the demagnetization phase of the first inductor (104) and the second inductor (302) non-conductive, and to switch the second semiconductor switch (114) during the specified period of time, ton, the magnetization phase of the first inductor (104) and the second inductor (302) at least to switch the first inductor (104) and the second inductor (302) to be conductive during the variable period of time tor, the demagnetization phase, at least in the positive half-cycle; 46 / 51 LU501057 wherein the specified duration, ton, of the magnetization phase of the inductor (104) is specified as a function of a specified maximum current through the inductor (104); and wherein the changeable duration, tor, of the demagnetization phase of the inductor (104) depends on a comparison of a predetermined minimum current through the inductor (104) and a current across the at least one current measuring point (110-1; 110-2; 110-3) measurable current is changeable. 6. Flyback converter circuit arrangement (300) according to claim 5, wherein the current source (102) feeding the input unit comprises an alternating current source, the first pole (102-1) acting as a negative pole in a negative half cycle, the second pole (102-2 ) acts as a positive pole in the negative half-wave; wherein the flyback converter circuit arrangement (300) further comprises a third semiconductor switch (116), a fourth semiconductor switch (118), a fifth semiconductor switch (202) and a sixth semiconductor switch (204), wherein the third semiconductor switch (126) is designed to to connect the first inductance (104) selectively to the first pole (102-1), the fourth semiconductor switch (118) being designed to selectively connect the first inductance (104) to the second pole (102-2), the fifth semiconductor switch (130) is arranged to selectively connect the first semiconductor switch (112) to the second pole (102-2), and wherein the sixth semiconductor switch (132) is arranged to selectively connect the first semiconductor switch (112) to the first connect pole (102-1); wherein the control unit (150) is designed to conduct the third semiconductor switch (116) and the fifth semiconductor switch (202) during the defined period of time, ton, of the magnetization phase in the positive half-wave and during the variable period of time, tor, of the demagnetization phase of the positive half-wave To switch half-wave non-conductive, and the third semiconductor switch (116) and the fifth Switching the semiconductor switch (202) non-conductive during the negative half-wave, wherein the control unit (150) is also designed to switch the fourth semiconductor switch (118) and the sixth semiconductor switch (202) non-conductive during the positive half-wave, and to switch the fourth semiconductor switch (118) and the sixth semiconductor switch (204) conductive during the fixed period of time, ton, of the magnetization phase in the negative half-wave and non-conductive during the variable period of time, tor, of the demagnetization phase of the negative half-wave. 7. Flyback converter circuit arrangement (300) according to claim 5, wherein the current source (102) feeding the input unit comprises an alternating current source, the first pole (102-1) acting as a negative pole in a negative half cycle, the second pole (102-2 ) acts as a positive pole in the negative half-wave; wherein the flyback converter circuit arrangement (300) further comprises a third inductance (304) and a third semiconductor switch (116), the third semiconductor switch (116) being designed to selectively connect the third inductance (304) to the first node (122) and connect to the second node (124); wherein the control unit (150) is designed to switch the second semiconductor switch (114) non-conductive during the negative half-wave; wherein the control unit (150) is designed to make the third semiconductor switch (116) non-conductive during the positive half-wave and during the fixed time period ton, the magnetization phase of at least the first inductor (104) in the negative half-wave and during the variable time period, torr, to turn on the demagnetization phase of at least the first inductor (104) of the negative half-wave. 48 / 51 LU501057 8. Circuit arrangement (100; 200; 300) according to any one of claims 1 to 7, wherein one or each of the semiconductor switches (112; 114; 116; 118; 202; 204) a MOSFET, in particular an n-channel MOSFET; a bipolar transistor; a thyristor and/or an insulated gate bipolar transistor, IGBT. 9. Circuit arrangement (100; 200; 300) according to any one of claims 1 to 8, wherein the control unit (150) is further adapted to operate the circuit arrangement in at least one of continuous operation, CCM; intermittent operation, DCM; and to operate on a boundary between non-gap and gap operation, BCM. 10. Circuit arrangement (100; 200; 300) according to any one of claims 1 to 9, wherein the at least one current measuring point (110-1; 110-2; 110-3) at least one measuring resistor (110-1; 110-2; 110- 3) or comprises at least one Hall sensor or at least one inductive current transformer. 11. Circuit arrangement (100; 200; 300) according to any one of claims 1 to 10, wherein the at least one current measuring point (110-1; 110-2; 110-3) is arranged in the current path of the first semiconductor switch (112), and wherein the Control unit (150) is also designed to measure at least one current value during the magnetization phase in the positive half-wave and/or in the negative half-wave across the at least one current measuring point (110-1; 110-2; 110-3). 12. Circuit arrangement (100; 200; 300) according to claim 11, wherein the at least one current value includes exactly one current value at a specified point in time of the magnetization phase, preferably at the beginning of the magnetization phase and/or in the vicinity of a switching point from the non-conductive to the conductive state of the first semiconductor switch (112). 13. Circuit arrangement (100; 200; 300) according to any one of claims 1 to 12, wherein the at least one current measuring point (110-1; 110-2; 110-3) is arranged in the current path of the second semiconductor switch (114), and wherein the Control unit (150) is also designed to measure at least one current value during the demagnetization phase in the positive half-wave and/or in the negative half-wave across the at least one current measuring point (110-1; 110-2; 110-3). 14. Circuit arrangement (100; 200; 300) according to any one of claims 1 to 13, wherein the control unit (150) is further adapted to at least one or each semiconductor switch (112; 114; 116; 118; 202; 204) in a dead State and / or to turn on in a currentless state of the inductor (104). 15. Circuit arrangement (100; 200; 300) according to any one of claims 1 to 14, wherein the control unit (150) comprises at least one of a digital signal processor, DSP; a microcontroller with control software; a Field Programmable Gate Array, FPGA; and an application specific integrated circuit, ASIC. 16. Method for controlling the semiconductor switches of a circuit arrangement (100; 200; 300) during a magnetization phase and a demagnetization phase of an inductance (104), comprising: measuring a current value via at least one current measuring point (110-1; 110-2; 110-3) one of the circuit arrangements (100; 200; 300) of claims 1 to 14, wherein the current value during a fixed time of a period comprising a fixed time duration, ton, of a magnetization phase and a variable time duration, tor, of a demagnetization phase of an inductance (104; 302; 304) is measured, the specified time duration, ton, of the magnetization phase of the inductance (104) being specified as a function of a predetermined maximum current through the inductance (104); Comparing the measured current value with a reference current value specified for the time of measurement; and changing the variable time duration, tor, of the demagnetization phase of the inductor (104) depending on a result of comparing the measured current value with the reference current value.