LU500894B1 - Soi cmos radio frequency switch structure with low insertion loss and low harmonics - Google Patents

Abstract

A SOI CMOS radio frequency switch structure for realizing low insertion loss and low harmonics, which comprises a plurality of resistors, a plurality of BC nMOS switch transistors and a plurality of FB pMOS bias transistors, wherein the body region of the BC nMOS switch transistors is connected to the anode of the FB pMOS bias transistors that connected with diodes, and the gate of the BC nMOS switch transistors is connected to the cathode of the FB pMOS bias transistors connected with diodes. According to the technical scheme provided by the invention, the radio frequency switch can simultaneously obtain low insertion loss and low second and third harmonics; on the other hand, with the increase of the number of switch throws, the invention can effectively simplify the contact between the internal wiring of the radio frequency switch and the node, reduce the parasitic coupling effect and saving chip area.

Description

DESCRIPTION SOI CMOS RADIO FREQUENCY SWITCH STRUCTURE WITH LOW INSERTION LOSS AND LOW HARMONICS

TECHNICAL FIELD The invention relates to the field of radio frequency switches, in particular to a SOI CMOS radio frequency switch structure for realizing low insertion loss and low harmonics.

BACKGROUND Modern wireless mobile terminal devices, such as smart phones, tablet computers and other wireless communication devices, have integrated a number of cellular communication services using different frequency bands (GSM/EDGE, TD-SCDMA/WCDMA, FDD/TD- LTE). Meanwhile, these mobile terminal devices not only need to operate in multi-mode and multi-band cellular frequency bands, but also provide WiFi, WiMAX, GPS, Bluetooth, RFID and other non-cellular communication services. Radio frequency switch can realize the use of multi-mode and multi-band power amplifiers, thus reducing the complexity of design and reducing the cost and power consumption. WiFi, Bluetooth and other modules also need to rely on radio frequency switch to switch between transmitting and receiving signals. In addition, in order to improve sensitivity and avoid crosstalk, multi-antenna design is becoming more and more popular. For these reasons, the radio frequency switch plays an increasingly important role in the radio frequency front-end design of wireless mobile terminals. GaAs pHEMT switch is dominant in radio frequency switch design because of its low DC power consumption, low insertion loss, high isolation and good power tolerance. However, by using high resistivity substrate materials, SOI CMOS technology can achieve favorable radio frequency performance comparable to GaAs process. In addition, with the wider application of baseband CMOS chips and the continuous reduction of total DC power consumption, and the trend of integrating radio frequency front-end circuits on a single chip, SOI MOSFET switches have certain advantages in terms of low control voltage, high throw-count switch and high integration applications. For the partially depleted SOI technology, there are two kinds of MOS transistors: floating body field effect transistor (FB FET) and body contact field effect transistor (BC FET).

The body region of FB FET 1s floating and can not be directly biased, while the potential of the body region of BC FET can be controlled and directly biased to a specific potential. Figure 1 1s a structural diagram of a transmitting and receiving single-pole double-throw radio frequency switch using SOI FB nMOS FET in the prior art. The transmit port TX 1s connected to the drain of the transmitting path FB nMOS switch transistor 104, the source of which 1s connected to the antenna port ANT and the drain of the receiving path FB nMOS switch transistor 124, and the source of the receiving path FB nMOS switch transistor 124 is connected to the receive port RX. The resistor 106 has one end connected to the drain of the transmitting path FB nMOS switch transistor 104 and the other end connected to the source of the transmitting path FB nMOS switch transistor 104. The resistor 126 has one end connected to the drain of the receiving path FB nMOS switch transistor 124 and the other end connected to the source of the receiving path FB nMOS switch transistor 124. The gate of the transmitting path FB nMOS switch transistor 104 is connected to the control signal VG1 through a resistor 102, and the gate of the receiving path FB nMOS switch transistor 124 is connected to the control signal VG2 through a resistor 112. At the same time, VG1 and VG2 keep one of them at high level VH (typically

2.5 V) and the other at low level VL (typically -2.5V). When VGI is at high level VH and VG? is at low level VL, the transmitting path FB nMOS switch transistor 104 is turned on and the receiving path FB nMOS switch transistor 124 is turned off. When VG is at low level VL and VG2 is at high level VH, the transmitting path FB nMOS switch transistor 104 is turned off and the receiving path FB nMOS switch transistor 124 is turned on. Low insertion loss can be obtained by using FB MOSFETs because FB MOSFET devices have very large equivalent body resistance. Therefore, FB MOSFET is considered as the preferred radio frequency switch transistor. This is correct for low throw switch design. However, from the cross-sectional structure diagram of SOI nMOS transistor in Figure 2, it can be seen that the main problem of FB MOS transistor is that as a switch transistor device, the linear and harmonic characteristics of the switch can not meet the specification requirements under the condition of large signal input. When the switch transistor is turned on, the potential of the body region 204 of the FB MOS transistor will closely follow the potential of the source electrode 206, and there will be no problem here. However, when the switch transistor is turned off with a high input power, there will be an issue of unbalanced voltage distribution in the stacked transistor. Uncontrollable potential of the body region 204 will cause the forward conduction of the source-body diode 202 and the drain-body diode 222 in part of the period of large signals, which will lead to heavy distortion of the waveform of large signals. Especially, with the increase of the number of switch throws, the second and third harmonic characteristics of the signal will be greatly deteriorated by using FB MOS as the switch transistor.

Figure 3 1s a structural diagram of a transmitting and receiving SPDT radio frequency switch using SOI BC nMOS FET in the prior art. The transmit port TX is connected to the drain of the transmitting path BC nMOS switch transistor 304, the source of which is connected to the antenna port ANT and the drain of the receiving path BC nMOS switch transistor 324, and the source of the receiving path BC nMOS switch transistor 324 is connected to the receive port RX. The resistor 306 has one end connected to the drain of the transmitting path BC nMOS switch transistor 304 and the other end connected to the source of the transmitting path BC nMOS switch transistor 304. The resistor 326 has one end connected to the drain of the receiving path BC nMOS switch transistor 324 and the other end connected to the source of the receiving path BC nMOS switch transistor 324. The gate of the transmitting path BC nMOS switch transistor 304 is connected to the control signal VGI through a resistor 302, and the gate of the receiving path BC nMOS switch transistor 324 1s connected to the control signal VG2 through a resistor 322. The body region of the transmitting path BC nMOS switch transistor 304 is connected to the control signal VB1 through a resistor 308, and the body region of the receiving path BC nMOS switch transistor 324 1s connected to the control signal VB2 through a resistor 328. At the same time, VG1 and VG2 keep one of them at high level VH (typically 2.5V) and the other at low level VL (typically -2.5). In order to obtain good harmonic characteristics, it is common practice to keep one of VB1 and VB2 at high level VBH (typically 0 V) and the other at low level VBL (typically -2.5) at the same time. When VGI is at high level VH, VBI is at high level VBH, VG2 is at low level VL and VB2 is at low level VBL, the transmitting path BC nMOS switch transistor 304 is turned on and the receiving path BC nMOS switch transistor 324 is turned off. While when the switch is turned off, VGI1 is at low level VL, VBI is at low level VBL, VG2 is at high level VH, VB2 is at high level VBH, the transmitting path BC nMOS switch transistor 304 is turned off, and the receiving path BC nMOS switch transistor 324 1s turned on. As shown in Figure 2, the body region 204 is biased by 0 V in the on state and negatively biased in the off state. This biasing method can avoid the forward conduction of the source-body diode 202 and the drain-body diode 222 of the off-state switch transistor when a high power is input, thereby reducing power loss and greatly improving the harmonic characteristics of the waveform. However, the main disadvantage of this technical scheme is that placing a large resistor and an applied bias voltage on the body region 204 can be regarded as adding a leakage path to the ground for the radio frequency signal, which is essentially equivalent to reducing the body resistance, which makes the insertion loss of the BC nMOS switch using this technical scheme larger. On the other hand, with the increase of the number of switch throws, the disadvantages of this technical scheme will be more exposed. Because each BC nMOS transistor needs extra large resistance and extra body bias, it will lead to more connections and contacts, more complex logic control, slightly increase the area of the switch chip, and introduce more serious parasitic effect and greater insertion loss.

SUMMARY The purpose of the present invention is to propose a radio frequency switch structure with the use of SOI BC nMOS transistor which can reduce insertion loss and second-order and third-order harmonics, named "Body Voltage Self-adaptive Bias" structure. This invented switch structure connects the body region of BC nMOS switch transistor to the anode of diode-connected FB pMOS transistor, and connects the gate of BC nMOS switch transistor to the cathode of diode-connected FB pMOS transistor, thus avoiding adding extra large resistance and extra bias voltage in the body region. As a result, the switch can simultaneously obtain lower insertion loss and lower second and third harmonic performance; On the other hand, with high-throw switch applications, the invention can also simplify the connection and node contact of the radio frequency switch, reduce the parasitic effect and save the chip area.

To this end, the invention adopts the following technical scheme: a SOI CMOS radio frequency switch structure for realizing low insertion loss and low harmonics comprises a BC nMOS switch transistor 404, a first bias resistor 402, a second bias resistor 406, and a FB pMOS bias transistor 408.

The FB pMOS bias transistor 408 has a drain connected to its own gate and then connected to the gate of the BC nMOS switch transistor 404. The FB pMOS bias transistor has a source connected to the body region of the BC nMOS switch transistor 404. The gate of the BC nMOS switch transistor 404 is connected to the control signal Vbias through a first bias resistor 402. One end of the second bias resistor 406 is connected to the drain of the BC nMOS switch transistor 404 and the other end is connected to the source of the BC nMOS switch transistor 404. The BC nMOS switch transistors can be stacked in series with more than one. According to the above contents, compared with the existing technical scheme of Figure 1, the present invention can obtain similar insertion loss at low frequency, but can obtain lower insertion loss at high frequency than the existing technical scheme of Figure 1. In addition, the invention can effectively avoid the forward conduction of the source-body diode and the drain-body diode of the switch transistor, and can obtain lower harmonic performance. Compared with the existing technical scheme in Figure 3, the invention can achieve similar DC bias, but the invention does not need to place extra large resistors and bias voltages in the body region, thus preventing the addition of a radio frequency signal leakage path to the ground, so the invention can reduce the insertion loss of the switch by 0.1 dB to 0.15 dB. In addition, the invention avoids a series of complicated wiring, contact and logic control under the condition of high switch throw number, simplifies the design of the switch, and effectively reduces the area and parasitic effect of the switch chip.

BRIEF DESCRIPTION OF THE FIGURES Figure 1 is a structural diagram of a transmitting and receiving single-pole double-throw radio frequency switch using SOI FB nMOS FET in the prior art. Figure 2 is a simplified cross-sectional structure diagram of SOI nMOS FET. Figure 3 is a structural diagram of a transmitting and receiving single-pole double-throw radio frequency switch using SOI BC nMOS FET in the prior art. Figure 4 1s a schematic circuit diagram of an embodiment of the present invention. Figure 5 is a characteristic diagram of DC gate voltage and body voltage of a switching transistor to which one embodiment of the present invention is applied.

Figure 6 is a schematic diagram of a single-pole double-throw radio frequency switch according to an embodiment of the present invention. Figure 7 is a comparison diagram of insertion loss between the single-pole eight-throw radio frequency switch according to an embodiment of the present invention and the switches in the prior art described in figures 1 and 3. Figure 8 is a comparison diagram of isolation between the single-pole eight-throw radio frequency switch according to an embodiment of the present invention and the switches in the prior art described in figures 1 and 3. Figure 9 is a comparison diagram of the second harmonic between the single-pole eight- throw radio frequency switch according to an embodiment of the present invention and the switches in the prior art described in figures 1 and 3. Figure 10 is a comparison diagram of the third harmonic between the single-pole eight- throw radio frequency switch according to an embodiment of the present invention and the switches in the prior art described in figures 1 and 3.

DESCRIPTION OF THE INVENTION In the following, the technical scheme of the present invention will be further explained with reference to the attached drawings and specific embodiments. As shown in Figure 6, a single-pole double-throw SOI CMOS radio frequency switch structure with low insertion loss and low harmonics includes a transmitting path BC nMOS switch transistor 604, a receiving path BC nMOS switch transistor 624, bias resistors 602, 606, 622 and 626 and FB pMOS bias transistors 608 and 628. The above components are connected as follows: the transmit port TX is connected to the drain of the transmitting path BC nMOS switch transistor 604, the source of the transmitting path BC nMOS switch transistor 604 1s connected to the antenna port ANT and the drain of the receiving path BC nMOS switch transistor 624, and the source of the receiving path BC nMOS switch transistor 624 is connected to the receive port RX. The resistor 606 has one end connected to the drain of the transmitting path BC nMOS switch transistor 604 and the other end connected to the source of the transmitting path BC nMOS switch transistor 604. The resistor 626 1s connected at one end to the drain of the receiving path BC nMOS switch transistor 624 and at the other end to the source of the receiving path BC nMOS switch transistor 624. The gate of the transmitting path BC nMOS switch transistor 604 is connected to the control signal VG1 through a resistor 602, the gate of the receiving path BC nMOS switch transistor 624 is connected to the control signal VG2 through a resistor 622, and the FB pMOS bias transistor 608 has a drain connected to its own gate and then connected to the gate of the transmitting path BC nMOS switch transistor 604. The FB pMOS bias transistor 608 has its source connected to the body region of the transmitting path BC nMOS switch transistor 604, and the FB pMOS bias transistor 628 has a drain connected to its own gate and then connected to the gate of the receiving path BC nMOS switch transistor 624. The source of FB pMOS bias transistor 628 is connected to the body region of the receiving path BC nMOS switch transistor 624.

Thesingle-pole double-throw SOI CMOS radio frequency switch realized above employs the present invention, which includes BC nMOS switch transistor 404, bias resistors 402 and 406 and FB pMOS bias transistor 408. The above components are connected as follows: the FB pMOS bias transistor 408 has a drain connected to its own gate and then connected to the gate of BC nMOS switch transistor 404; the source of FB pMOS bias transistor 408 is connected to the body region of BC nMOS switch transistor 404; the gate of BC nMOS switch transistor 404 is connected to control signal Vbias through resistor 402; one end of resistor 406 is connected to the drain of BC nMOS switch transistor 404 and the other end is connected to the source of BC nMOS switch transistor 404.

At the same time, VGI1 and VG2 keep one of them at high level VH (typically 2.5 V) and the other at low level VL (typically -2.5V). When VGI is at high level VH and VG2 is at low level VL, the transmitting path BC nMOS switch transistor 604 is turned on and the receiving path BC nMOS switch transistor 624 is turned off. While when VGI is at low level VL and VG2 is at high level VH, the transmitting path BC nMOS switch transistor 604 1s turned off and the receiving path BC nMOS switch transistor 624 is turned on.

It should be noted that in SOI CMOS process, the source and drain of MOSFET are interchangeable in general, so in the description of the present invention, the source and drain of all MOSFETs are interchangeable.

The values of DC bias voltages VH and VL, the component values of bias resistors, and the size values of BC nMOS switch transistor and FB pMOS bias transistor mentioned in the present invention need to be designed according to the specific conditions of the radio frequency switch, which is easy to understand for the skilled person.

In addition, according to the radio frequency power that the radio frequency switch needs to bear, besides adjusting the size of a single switch transistor, it is also necessary to adopt the stacked-FETs method.

The number of stacked transistors is also determined according to the radio frequency power that needs to be borne in specific applications.

This is also easily understood by those skilled in the art.

The technical scheme provided by the invention can be easily extended to applications of single-pole multi-throw switches (such as single-pole eight-throw switches, single-pole fourteen-throw switches, etc.) and multi-pole multi-throw switches (such as double-pole double-throw switches, four-pole ten-throw switches, etc.). The following is a comparison of the radio frequency performance of typical single-pole eight-throw radio frequency switch examples in Figures 1 and 3, including insertion loss, isolation, second harmonic and third harmonic.

It should be noted that the following comparison of radio frequency switch performance is obtained under the condition that the gate DC bias voltage, all bias resistors, the size of switch transistors and the number of switch transistors stacked in series are equal.

This is also easily understood by those skilled in the art.

Figure 7 is a comparison diagram of insertion loss between the single-pole eight-throw radio frequency switch according to an embodiment of the present invention and the switches in the prior art described in figures 1 and 3. The graph includes a switch insertion loss curve 701 applying the prior art scheme of Figure 1, a switch insertion loss curve 703 applying the prior art scheme of Figure 3, and a switch insertion loss curve 707 applying the technical scheme of the present invention.

It can be seen that curve 707 has the lowest insertion loss.

When the frequency is below 1 GHz, 701 and 707 have almost the same insertion loss.

However, as the frequency increases, the insertion loss of 707 decreases the slowest.

At 3 GHz, the insertion loss of 707 is 0.5 dB less than that of 701. On the other hand, the insertion loss of curve 703 is the largest, and at 3GHz, the insertion loss of curve 707 is 1.3 dB less than that of curve 703. Figure 8 is a comparison diagram of isolation between the single-pole eight-throw radio frequency switch according to an embodiment of the present invention and the switches in the prior art described in Figures 1 and 3. The graph includes a switch isolation curve 801 applying the prior art scheme of Figure 1, a switch isolation curve 803 applying the prior art scheme of Figure 3, and a switch isolation curve 807 applying the technical scheme of the present invention. It can be seen that curve 807 and curve 803 have almost no difference in isolation performance, while curve 801 has the worst isolation performance. At 3 GHz, the isolation degree of 807 is almost equal to 803, and the isolation degree of 807 is 2.5 dB higher than that of 801.

Figure 9 is a comparison of the second harmonic between the first technical scheme of the present invention and the existing switch technical schemes of Figure 1 and Figure 3 at 900 MHz. The graph includes a switching second harmonic curve 901 applying the prior art scheme of Figure 1, a switching second harmonic curve 903 applying the prior art scheme of Figure 3, and a switching second harmonic curve 907 applying the technical scheme of the present invention. It can be seen that curve 907 has the lowest second harmonic, followed by curve 903, and the second harmonic performance of curve 901 is the worst. At Pin=26 dBm, the second harmonic of 907 is about 5 dBm lower than that of 903 and about 12 dBm lower than that of 901.

Figure 10 is a comparison of the third harmonic between the first technical scheme of the present invention and the existing switch technical schemes of Figure 1 and Figure 3 at 900 MHz. The graph includes a switching third harmonic curve 1001 applying the prior art scheme of Figure 1, a switching third harmonic curve 1003 applying the prior art scheme of Figure 3, and a switching third harmonic curve 1007 applying the technical scheme of the present invention. It can be seen that curve 1007 has slightly lower third harmonic performance than curve 1003, but the difference is not obvious, while curve 1001 has the worst third harmonic performance. At Pin=26 dBm, the third harmonic of 1007 is only 1.5 dBm higher than that of 1003, but about 25 dBm lower than that of 1001.

The technical principle of the present invention has been described in combination with the above specific embodiments. These descriptions are only for the purpose of explaining the principle of the present invention, and cannot be interpreted as limiting the scope of protection of the present invention in any way. Based on the explanation here, the person skilled in the art can think of other specific embodiments of the present invention without creative labor, and these methods will fall within the protection scope of the present invention.

Claims (4)

1. A SOI CMOS radio frequency switch structure for realizing low insertion loss and low harmonics, characterized in comprising a transmitting path BC nMOS switch transistor, a receiving path BC nMOS switch transistor, a first class bias resistor and a first class FB pMOS bias transistor, wherein the first class bias resistor comprises a first bias resistor, a second bias resistor, a third bias resistor and a fourth bias resistor; the FB pMOS bias transistor includes a first bias transistor and a second bias transistor; a drain of the transmitting path BC nMOS switch transistor is connected to a transmission signal TX, a source of the transmitting path BC nMOS switch transistor is connected to an antenna ANT and a drain of the receiving path BC nMOS switch transistor; a source of the receiving path BC nMOS switch transistor is connected to a reception signal RX; the second bias resistor is connected at one end to the drain of the transmitting path BC nMOS switch transistor and at the other end to the source of transmitting path BC nMOS switch transistor; the fourth bias resistor has one end connected to the drain of the receiving path BC nMOS switch transistor and the other end connected to the source of the transmitting path BC nMOS switch transistor; the receiving path BC nMOS switch transistor is provided with a gate connected to the control signal VG1 through the first bias resistor; the gate of the receiving path BC nMOS switch transistor is connected to the control signal VG2 through a third bias resistor; the drain of the first bias transistor is connected to the gate of the transmitting path BC nMOS switch transistor; the source of the first bias transistor is connected to the body region of the transmitting path BC nMOS switch transistor; the drain of the second bias transistor is connected to the gate of the receiving path BC nMOS switch transistor; and the source of the second bias transistor is connected to the receiving path BC nMOS switch transistor.

2. The SOI CMOS radio frequency switch structure for realizing low insertion loss and low harmonics according to claim 1, characterized in that the SOI CMOS radio frequency switch structure is provided with a bias structure, which comprises an independent BC nMOS switch transistor, a second class of bias resistor and a second class of FB pMOS bias transistor, and the second class of bias resistor comprises a fifth bias resistor and a sixth bias resistor;

the second class FB pMOS bias transistor has a drain connected to its own gate and then connected to the gate of the independent BC nMOS switch transistor 404; the second class FB pMOS bias transistor has a source connected to the body region of the independent BC nMOS switch transistor; the gate of the independent BC nMOS switch transistor is connected to the control signal Vbias through the fifth bias resistor; one end of the sixth bias resistor is connected to the drain of the independent BC nMOS switch transistor and the other end is connected to the source of the independent BC nMOS switch transistor.

3. The SOI CMOS radio frequency switch structure for realizing low insertion loss and low harmonics according to claim 1 or 2, wherein the source and drain of at least one of the transmitting path BC nMOS switch transistor and the receiving path BC nMOS switch transistor can be interchanged.

4. The SOI CMOS radio frequency switch structure for realizing low insertion loss and low harmonics according to claim 1 or 2, characterized in that more than one transmitting path BC nMOS switch transistor and receiving path BC nMOS switch transistor are stacked in series.