KR980013130A - Replacement write-back cycle processor and method for multiprocessor systems - Google Patents

Abstract

The present invention relates to an apparatus and a method for processing a write back cycle in a multiprocessor system, the apparatus comprising: address storage means for storing an address of a write back cycle generated by a second cache miss; Outputting means for outputting: data storing means for storing the data of the replacement writeback cycle generated by the secondary cache miss; Data output means for outputting data: a first comparator for comparing an address stored in the address storage means with an address driven by a processor in a new cache line fill cycle; A second comparator for comparing the address stored in the address storage means with the snoop address; And a bus cycle controller for controlling the progress of the snoop write back cycle or the replacement write back cycle.

According to the present invention, it is possible to shorten the time required for the processor to cycle and to use the system bus only when necessary, thereby improving the performance of the entire system

Description

Replacement write-back cycle processor and method for multiprocessor systems

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to cache cycles associated with caching in a multiprocessor system, and more particularly, to a bus cycle in which a secondary cache is placed on the outside of the processor, Apparatus and method.

Generally, each processor in a multiprocessor system based on a bus and based on a shared memory accesses shared memory resources via the system bus. At this time, as the number of processors constituting the system increases, the processor becomes a master requesting a bus, so competition for the system bus use is intensified. As the processing speed of the microprocessor is getting faster, the difference in the processing speed between the microprocessor and the system bus becomes more apparent.

Therefore, in today's multiprocessor systems, it is becoming a common practice to load cache memory with high speed in each processor. Instead of accessing the shared memory resources through the system bus, the cache memory is used to store the most frequently accessed data of each processor itself in a fast memory in the processor board, thereby improving system performance It is a fast memory that allows it. With the adoption of cache memory, the competition for bus masters' rights to use the system bus is eased, and the use efficiency of the bus is increased.

Meanwhile, in order to ensure data consistency between the data in the cache memory in each board and the data in the shared memory on the system bus, it is inevitable that the protocol of the system bus to support it is somewhat complicated.

The microprocessor mounted on the processor board to which the present invention can be applied is a Pentium P54C of Intel Corporation, which houses a primary cache memory. The secondary cache memory includes a cache / snoop / snoop / cycle) controller C5C and cache memory C8C. Of course, if a different device is used, a secondary cache memory of 1 MB or 2 MB can be implemented. However, the present invention will be described with reference to an example of 512 KB for the sake of convenience. Unlike the primary cache memory, Memory is a unified cache without distinction between data and code. In order to guarantee data consistency, the memory has a structure in which all the data in the primary cache memory is included in the secondary cache memory, The inclusion property is observed.

In more detail, the cache memory is composed of a 2-way set associative tag memory and a 2-way data memory for storing addresses corresponding to specific data. For the cache line size, which is the basic unit of cache operation, the secondary cache memory is set to 64 bytes. Here, the 512KB secondary cache memory is described from the viewpoint of the data cache memory size, and if mechanically explained, it can be said that the 2-way cache structure is composed of two 256KB data cache memories. The Pentium processor P54C uses a 32-bit address signal (A31-A0) to access a total of 4GB of memory space, so the secondary cache memory is configured to contain any of the 4GB of data in total . That is, 4GB: 512KB mapping structure is implemented. To this end, the cache / snoop / cycle controller C5C can access a 2-way tag memory having 4096 allocation locations using A17-A6 (set address) among the address signals. Here, 2-way means that the location of each 4096 tag memories has a dual structure that can contain two tag information (tag address: A31-A18) FMF. 512KB = number of set locations (4096 or 4K) X 2-way X 64 bytes (cache line size).

Next, the data access cycles of the processor will be described. FIG. 1 is a block diagram of a multiprocessor system having a symmetric structure based on a shared memory to which the present invention and a conventional processor board are applied.

The M.E.S.I protocol used to maintain data consistency is a cache related protocol used in the Intel Pentium processor, and the M.ES.I indicates the state of the cache line. The M is an abbreviation of Modified. The state of the cache line is M, which means that only one cache can use M, and the data of the cache line is different from the main memory. E is an abbreviation of Exclusive and can be used in only one cache. The cache line E means that the data is the same as the data in the main memory. If data is written in the cache line in the E state, Is changed to M. And S is an abbreviation of Shared, which indicates that at least two or more caches have the same data at the same address. When data is written in the S-state cache line, the state of the cache line is changed to M, and data of other cache lines must be invalidated. Lastly, I is an abbreviation of Invalid, and if the state of the cache line is I, it indicates that the data of the cache line is invalid. That is, the processor is no longer usable.

2 shows a block diagram of a conventional processor board. Reference numeral 200 denotes a processor (CPU), which is a Pentium processor having a built-in primary cache memory. Reference numeral 205 denotes a snoop controller , Snooping shared memory accesses of other processor boards based on the MESI protocol, and initiating a system bus cycle to access the shared memory in response thereto, if necessary. 210 is a cache controller, The address tag of the secondary cache memory 215 is managed based on the MESI protocol in accordance with the access to the memory 215 and the read / write access to the system bus shared memory, the snooping of the snoop controller 205, Initiates a system bus cycle and proceeds with the help of the bus cycle controller 235 and proceeds to step 215. Then, A.

220 is a multilevel (non-cacheable), non-cacheable single write, write-through single write and snoop write back burst write multi-level pipelined registers.

And 225 is a data buffer for single write, write-through, and cacheable burst reads that are not cache-enabled and can be implemented as a single-level or multilevel register, depending on the design. 230 is an address latch and tri-state buffer that latches a cacheable or non-cacheable read cycle address, a single write cycle address and a snoop write back cycle address.

Reference numeral 235 denotes a bus cycle controller which receives cycle type and command signals from the processor 200 and prepares a corresponding system bus access cycle, participates in a system bus arbitration to acquire a license of the bus, Performs a read / write access to the memory and ends the bus cycle of the processor 200. [

In this series of bus cycle processing, it controls the opening / closing and load / unload of the address latch / buffer, data register / buffer, and various system bus interface bus transceiver logic as a whole.

240 is a system bus interface transceiver logic for snooping shared memory read / write access to other processor boards and delivering the corresponding snoop response. The snoop response is sent to the processor board (snoop controller) The processor board that has responded to the snoop response sets the cache line tag state at the end of its cycle to an appropriate value, Thereby ensuring overall system-level data consistency.

245 transfers its address for the system bus cycle of its processor board to the system bus and also monitors its address to monitor the system bus address for access to the shared memory of the other processor board, It is the system bus interface transceiver logic used to receive the signal.

250 is a system bus interface transceiver logic for requesting the use of the system bus for access to its system bus and for sending and receiving a series of signals needed to participate in the arbitration and acquire the license of the bus.

255 is a system bus interface transceiver logic for transferring data to and from the system bus in accordance with its own system bus access cycle type (read / write).

On the other hand, the signal 3 is the output enable signal of the address latch and tri-state buffer of the normal cycle, that is, the read cycle, the single write cycle, and the snoop write back cycle, and the signal 4 is the address latch & It is the latch enable signal of the tri-state buffer.

Signal 7 is a write data output enable signal in a single write or snoop write cycle and signal 8 is a write data load enable signal in a single write or snoop write back cycle. Signal 11 is a read data load enable signal, and signal 12 is a read data output enable signal.

On the other hand, in the case of the secondary cache memory, there are additional tag state allocation locations, which are separate areas, for storing the M.ESI information in each of 4096 2-way tag memory allocation locations.

The following will describe the data access cycles of the processor with reference to FIG. 1 and FIG.

1) Data read cycle (data read cycle)

When the data requested by the processor 200 is not in the primary cache memory, that is, when the primary cache is a read miss, the processor 200 reads data from the secondary cache / snoop / And the controllers 205 and 210 open the allocation place in the two tag memories corresponding to A17-A6 of the processor addresses, and store therein the address of the desired data (the same value as A31-A18 of the processor) The secondary cache data memory 215 supplies the data corresponding thereto to the processor 200. In this case, If there is no desired address, that is, if there is a secondary cache miss, the controllers 205 and 210 request the bus cycle controller 235 shown in FIG. 2 to access the shared memory through the system bus to supply read data. The bus cycle controller 235 drives signals requesting the use of the system bus, acquires the right to use the bus through an arbitration of the system bus, and then transmits information signals (address, cycle type, etc.) ) To the shared memory in accordance with the bus protocol. This address cycle is retried in response to a snoop response from another processor (processor component board) located on the system bus at this point retry or retry the snoop response, and if there is a data response from the shared memory, The base bus cycle controller 235 delivers this to the secondary cache memory 215. At this time, the tag state delivery location is marked with one of the MESIs according to the previously described snoop response If the snoop response is not shared, the tag state is denoted by E. If the snoop response is shared, the tag state is denoted by S. In this manner, the read data requested by the processor 200 is stored in the primary or secondary cache memory 215 and is then read hits in order to read the data thereafter, All operations without request can be processed quickly in cache memory.

2) Data write cycle (data write cycle)

In the case where the line to be written by the processor 200 is already in the primary cache, that is, the cache write hit, the cache data line of the primary cache is directly accessed without a separate data access request to the secondary cache. The primary tag state allocation location is changed to M in the case of E and to M in the case of M and to E in the case of S and to the secondary cache memory A write-through cycle is requested for the system bus 215 and subsequently requests the system bus access to write the data to the shared memory.

If the write cycle request for the primary cache of the processor 200 is miss and the write cycle request for the secondary cache memory 215 is (secondary cache wrte hit), then the controller 205,210 ) Writes data to the corresponding data cache memory allocation location, and changes the tag state allocation location to M for M, M for M, and E for S, Request access and write the data in shared memory in a single data write-through cycle.

If the write request of the processor 200 is missed in both the primary and secondary caches, the controller 205,210 requests a bus cycle controller 235 for a system bus access cycle and the bus cycle controller 235 requests the system bus usage An exclusive read cycle is performed in place of the write cycle to supply cacheable burst data, which is line-by-line data, from the shared memory, and then the cacheable burst data is transferred to the secondary cache 215. The controller 205 or 120 drives the controller 205 or 120 to write the original write data from the processor to the required portion of the line data so as to write the original write data to the second cache 210 And writes it to the corresponding data cache memory allocation position. The secondary tag state allocation location is indicated by M. At this time, no data enters the primary cache.

3) A replacement write back cycle

In the case of a general cacheable read cycle and a cachable exclusive read cycle as described above, the location of the secondary cache memory corresponding to the processor address A17-A6, (4 bytes) is mapped to 512 KB, which is a very small size. Therefore, in the second-order cache memory of the 2-way structure, A17-A6 The data of the same line size can only be stored in a maximum of 2. Therefore, the corresponding place of the dividend is already replaced by the previous cache line fill data, If the cash line is filled by filling and the new cache line must be filled again at the dividend location, If the location is ES or I on the tag corresponding to the line dividing place to be replaced, it can be just replaced, but if it is M, the data matching it is necessary to follow the process of transferring the data to the shared memory in order to ensure consistency. This is referred to as 'alternate write back cycle' and all of the replaced lines are burst write through the system bus, Cycle (operation of dividing the line-size data into the data bus width of the system bus and sequentially writing in succession in one write cycle).

4) Snoop write back cycle (snoop write back cycle)

The cache / snoop / cycle controllers 205 and 210 and the snoop control logic, which is additionally present for snooping in the processor board, will be collectively referred to as a snoop controller 205. In a multiprocessor system using the MESI protocol, the snoop controller in one processor board is responsible for always snooping the system bus access of all other processors, which corresponds to the system bus access addresses A17-A6 of the other processors The address value stored in the cache tag delivery location is compared with its address A31-A18, and at the end of the system bus access address cycle of another processor according to the MESI marking state of the tag state delivery location, The snoop controller 205 determines whether the hit state (i.e., address is the same) and the state of the tag state allocation place is M by comparing the addresses with each other, To delay the access to the shared memory of the other processor, And requests the bus cycle controller 235 to perform a burst write back cycle for writing data into the shared memory. This is referred to as the 'snoop writeback cycle.' The shared memory access cycle of another processor that has been delayed will not resume until after this snoop writeback cycle has ended.

5) Non-cacheable read / write cycles (non cachable read / write cycle)

Processor 200 may declare some of the total 4 GB memory areas as non-cacheable areas for read / write, in which case any cache line fill to the primary and secondary cache memory Only a single data read / write cycle through the system bus is performed through the controllers 205 and 210 and the bus cycle controller 235 without any change in the cache tag state and no change in the cache tag state.

As shown in FIG. 3, the addresses of all system bus access cycles of the processor are all accessed by the bus cycle controller 235 via the single address latch & tri-state buffer 230 The data of all the write cycles is passed through the single pipelined write data register 220 without distinguishing between the single write and the alternate write back and the read data is stored in the data buffer 225 as a single path As described above, if the cache line filling performed through the system bus access causes a replacement for the cache line existing in the M state, the replacement write back cycle is followed. The problem is that the processor on the processor board that performed this alternate writeback cycle has no choice but to defer or delay any further system bus access cycles until the cycle is terminated normally.

When one processor reads data from the shared memory through the system bus and fills the cache line, if the place of the existing cache data line whose tag state is M is to be replaced, the replacement write back cycle must be followed by the system bus This means that the processor has to wait for the alternate writeback cycle to terminate normally even if the request for accessing the system bus internally occurs, and if you look at it from the point of view of the processor running the program, In contrast, a relatively small amount of cache memory is mapped to the entire shared memory area, so that the processor actually requires only one read. In terms of the system bus access cycle, however, two cycles necessarily occur This alternate writeback cycle is a cycle in which no one on the system bus needs its data immediately, that is, it does not need to be urgently written to shared memory, and eventually transfers it to shared memory or another processor board The data consistency can be ensured.

As the system bus is used for cycles that do not need to be performed immediately, the use of the system bus becomes inefficient, which is one of the factors that degrade the performance of the overall system.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to improve system performance by increasing the processing speed of a processor, more effectively using a system bus while ensuring consistency of data in a multiprocessor system using a cache memory And to provide a replacement writeback processing apparatus and method for a multi-processor system.

FIG. 1 is a block diagram of a multiprocessor system having a symmetric structure based on a shared memory to which the present invention and a conventional processor board are applied.

FIG. 2 shows a block diagram of a conventional processor board,

Figure 3 shows a recording block diagram of the present invention,

FIG. 4 shows the expanded configuration of FIG.

According to an aspect of the present invention, there is provided a processor system including at least two processor boards in which a secondary cache is mounted on the exterior of a processor, An address storing means for storing an address of a replacement write back cycle generated by a secondary cache reading error of the processor; an outputting means for outputting an address stored in the address storing means; Data storing means for storing data of a write back cycle; Data output means for outputting alternate write-back data of the data storage means; A first comparator for comparing an address held by said address storage means with an address driven by a processor in a new cache line fill cycle; A second comparator for comparing the address stored in the address storage means with an address (snoop address) driven by another processor on the system bus; And a bus cycle controller for controlling a series of processes for advancing a snoop write-back cycle or a write-right write-back cycle through arbitration of the system bus according to the comparison result of the first comparator and the second comparator desirable.

The bus cycle controller supplies the stored alternate write back data to the processor when the comparison result of the first comparator is equal to the comparison result. If the compared addresses are different from each other, the bus cycle controller stores the address of the new alternate write back cycle A write back cycle is carried out to replace the stored address and data with a shared memory, and if the comparison result addresses of the second comparator are equal to each other , And controls the stored write right back cycle to proceed in a snoop write back cycle.

According to another aspect of the present invention, there is provided a processor system including a processor board having a plurality of processor boards, The method includes the steps of storing the address and data of the alternate write back cycle generated by the secondary cache miss of the processor in its processor board; And comparing the address of the stored alternate write back cycle with the address on the system bus driven by another processor board. If the addresses are the same, the address and data of the stored alternate write back cycle are stored in a shared memory And if the processor again requests a new cache line fill, it checks if there is a place to store the new cache line fill address and data, if there is a place to store it, and if there is no place, And rewriting the data to the shared memory by proceeding with the system bus cycle and storing the stored spare back address and data into the shared memory.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings. FIG. 3 shows a basic block diagram of the present invention. The basic structure of FIG. 3 is similar to that of FIG. 2, but in comparison with FIG. 2, a replacement write back addressless latch & address comparator block 300 and a register 320 is added, and the bus cycle controller 310 is slightly modified.

The substitute write back address latch & address latch & address comparator 300 is a latch & tri-state buffer for latching a replacement write back address and stores the shared memory read cycle address of its own processor 200 A comparator 302 for comparing the already latched replacement write back address and a snoop comparator 304 for comparing the snoop address, which is the shared memory access cycle address of another processor board, with the already latched replacement write back address ).

And the register 320 for the replacement write back is a multi-level pipelined register for loading data for replacement write back or burst writes. The bus cycle controller 310 is a bus cycle controller that adds signal 1, signal 2, signal 5, signal 6, signal 9, and signal 10 to the bus cycle controller 235 of FIG. 2 to achieve the object of the present invention.

The signal 1 is the alternate write back cycle address latch and the output enable signal of the tri-state buffer, and the signal 2 is the alternate write back cycle address latch and the latch enable signal of the tri-state buffer.

Signal 5 is a read hit signal, that is, an output signal of the alternate write back address latch & address comparator 300. The signal is a CPU for comparing the shared memory read cycle address of its own processor 200 with the already- The bit cycle controller 310 does not use the system bus for its read cycle and instead uses the system bus for the read cycle of the alternate light 200. In this case, Outputs the data from the register 320 for back and transfers the data to the processor 200 via the data buffer 225.

Signal 6 is an output signal of the above-mentioned replacement write back address latch & address comparator 300 and is driven when two addresses match in a snoop address comparator 304 which is a shared memory access cycle address of another processor board The bus cycle controller 310 drives a system bus write cycle for snoop write back and outputs the data from the register 320 to the system bus interface transceiver 255 via the system bus interface transceiver 255. [ .

Signal 9 is the write data output enable signal for the alternate write back cycle and signal 10 is the write data load enable signal for the alternate write back cycle.

3, the basic matter is the same as that of FIG. 3, but the replacement write back address latch & address comparator 300 and the register 320 are expanded. As a result, The signals 2 and 10, which are signals used for loading addresses and data into the back address latch & address comparator 300 and the register 320, are composed of a plurality of signals, The comparator, which is a component of the drag latch & address comparator 400, is more complicated and controls the comparator according to the size of the extended alternate write back address latch & address comparator 400 and the register 410 and the implementation of the comparator Signals are added to inform the result to the bus cycle controller 420. The extended alternate write back address latch & address comparator 400 and the extended < RTI ID = 0.0 > As can be seen from the register 410, a multiplexer (MUX 402, 412) logic is required in the functional aspects thereof, and a signal for controlling the multiplexer is required.

Before describing the operation of the present invention based on the above-mentioned drawings, the basic concept of the present invention will be described as follows. The present invention focuses on the characteristics of the alternate write back cycle in that writeback data is written to latches 300 and 400 and registers 320 and 410 in the processor board in a writeback cycle that follows the cache line fill of the processor, And terminates the processor cycle immediately without requesting a separate system bus access so that the processor 200 can newly drive a cycle for system bus access if necessary.

The stored address and data may be used as follows. Can be used to acknowledge this through a snooping when the other processor board asks it and to modify the snoop writeback cycle if the alternate writeback address latch & address comparator 300,400 is hit and to drive the system bus access cycle When the processor 200 requests the data again, it immediately supplies the stored data without requesting a separate system bus access, thereby quickly terminating the processor cycle, thereby improving the performance of the processor. When a new system bus access request for filling the cache line of the own process occurs, the system receives the license through the arbitration of the system bus. Then, the replacement write back address stored before the read cycle cache line fill is first driven, In such a manner as to drive a dress as a system bus use (hereinafter referred to as the cycle rear rendering (reordering)) may perform two system bus cycle.

This is particularly effective in the case of a system bus that has a separate buffer queue for address / command queues and write data in the shared memory board and adopts the pended protocol, Data is transferred to the system bus together, but in the case of a read cycle, after a certain time delay after the address is transferred from the processor to the system bus, the shared memory will send data to the system bus when the data is ready. It is possible to perform the processing by reordering two cycles with respect to each other. As a result, it is possible to see the effect that two cycles are overlapped and processed in a unit time.

The operation of FIG. 3 showing a block diagram of the basic configuration of the present invention will be described. The processor 200 requests a system bus read cycle by a secondary cache read miss and the bus cycle controller 310 receives data from the system bus after acquiring a bus license and terminates the cache line filling. This cache line fill replaces the cache data line where the tag state was previously M, which causes the processor 200 to request a replacement write back cycle.

The bus cycle controller 310 stores the replacement write back cycle address and data in the address latch & address comparator 300 and the register 320, respectively, and immediately terminates the cycle of the processor 200 so that the processor 200 Allows you to do the following and does not perform a separate system bus cycle for replacement writeback.

When the processor again requests a new cache line fill, the bus cycle controller 310 performs a system bus cycle by reordering the stored write back cycle and the cache line fill cycle.

Meanwhile, when the result of snooping the system bus access address of the other processor board by the address latch & address comparator 300 is a hit, that is, when the bus cycle controller 310 receives the system bus access address of the other processor board from the snoop comparator 304, If the address on the system bus driven by the board is the same as the address stored in the address latch, which is the address storage means in the address latch & address comparator 300, the replacement write back address stored in the address latch and the data in the register 320 And performs a system bus access cycle for a snoop writeback cycle using data stored in a register as a storage means.

And the bus cycle controller 310 determines if a new cache line fill request address from the processor 200 matches a stored replace write back address, i.e., the address stored in the address latch in the comparator 302, The cache line request addresses are compared with each other and the replacement write back data stored in the register 320 is transferred to the data output means in the register 320 without performing a separate system bus cycle It is possible to quickly terminate the cycle by supplying it to the processor 200 through the tristate buffer.

4, which is an expanded block diagram of the basic configuration of the present invention, will be described. First, the processor 200 requests a system bus read cycle by a secondary cache read miss and the bus cycle controller 420 receives data from the system bus after acquiring a bus license and terminates the cache line filling. The filling causes the cache data line, which was previously tagged with M, to be replaced, which causes the processor 200 to request a replacement write back cycle. At this time, the bus cycle controller 420 stores the replacement write back cycle address and data in the extended address latch & address comparator 400 and the extended register 410, respectively, and immediately terminates the cycle of the processor 200 So that the processor 200 can do the next thing and does not perform a separate system bus cycle for the replacement write back. Processor cycles are performed smoothly and quickly without the need for a separate system bus access for alternate write back to the extent that the size of the extended address register & address comparator 400 and the extended register 410 allows.

Since the extended address & address comparator 400 and the extended register 410 are composed of a plurality of units rather than a single structure, the bus cycle controller 420 may control the system bus access address The result of snooping by the extended address & address comparator 400 is often a hit, and thus the system bus access cycle for the snoop writeback cycle using the stored replacement write back address and data, Is performed more frequently.

In addition, in the extended structure, the bus cycle controller 420 also frequently matches a new cache line fill request address from the processor 200 with a stored replacement write back address, and does not need to perform a separate system bus cycle By supplying the stored replacement writeback data to the processor 200, the cycle can be quickly terminated.

Cycle reordering occurs only when the extended address register & address comparator 400 and the extended register 410 are filled with the existing replacement write back. Therefore, the extended address & address comparator 400 and the size of the extended register 410 is larger, the frequency of occurrence of cycle reordering will be reduced.

3 and 4, the operation principle of the present invention is the same, but its detailed operation and effect are considerably different. For example, in the bus cycle controller 310 of FIG. 3 and the bus cycle controller 310 of FIG. 4, The timing at which the bus cycle controller 420 decides to rearrange the alternate write back cycle with a new read cycle may be different.

In the basic configuration of FIG. 3, when a replacement write-back cycle is already latched and another processor board accesses the existing latched address through a system bus, the system bus access cycle The address register & address comparator 400 and the register 410 must be left empty for a new replacement writeback that may be caused by a new read by performing only one latch and one pipeline register It is a unavoidable phenomenon because it is a single structure.

4, the bus cycle controller 420 determines whether a new read cycle request is generated only when the extended address & address comparator 400 and the extended register 410 are full, And rearranges to perform the system bus cycle. Until a situation requiring such rearranging comes, the extended address & address comparator 400 can perform only snooping and operate accordingly. Here, it is determined in consideration of the design specifications of the entire system, that is, the 'price: performance ratio', the complexity in the implementation of the extended address latch & address comparator 400, etc., do. The replacement writeback data is inevitably replaced by the replacement of the cache data line. Considering that the data is highly likely to be requested again by the processor in the near future, the configuration with the appropriate scale expansion is relatively large in the system It is possible to achieve an effect more than placing a cache memory.

According to the present invention, address / command / data information of a replacement writeback cycle that does not require a system bus cycle immediately is stored, and when necessary, when its own processor again requests the data, When a board is detected through snooping that the data is needed by the system bus access, it is newly requested by the processor when the place to use or store such information is full (full) By allowing the system bus access cycle to be performed by cycling and re-cycling for cache line filling, it is possible to reduce the time it takes the processor to cycle, reduce the frequency of use of the system bus, It is effective to make use of the whole system The function can be remarkably improved.

Claims (5)

There is provided a write back cycle processing apparatus in a multiprocessor system in which at least two processor boards having a secondary cache are mounted on the outside of the processor and the processor boards are connected based on a bus, Storage means for storing an address of a replacement writeback cycle generated by the storage means; Output means for outputting an address stored in the address storage means; Data storage means for storing data of a replacement writeback cycle generated by a secondary cache miss of a processor; Data output means for outputting alternate write-back data of the data storage means; A first comparator for comparing an address stored in the address storage means with an address driven by a processor in a new cache line fill cycle; A second comparator for comparing the address stored in the address storage means with an address (snoop address) driven by another processor on the system bus; And a bus cycle controller for controlling a series of processes for proceeding with a snoop writeback cycle or a replacement writeback cycle through arbitration of the system bus according to the comparison result of the first comparator and the second comparator Characterized in that the replacement light-back cycle processor of the multiprocessor system. The bus cycle controller according to claim 1, wherein the bus cycle controller supplies the stored alternate write back data to the processor when the comparison results of the first comparator are equal to each other, And if there is a storage location storing an address, performs a series of control to store the address and data in a storage location, and if not, perform a write back cycle to replace the stored replacement write back address and data with the shared memory, And controls the stored replace write back cycle to proceed to a snoop write back cycle if the comparison result indicates that the addresses are equal to each other. The apparatus of claim 1, wherein the address output means and the data output means are tri-state buffers. 2. The semiconductor memory device according to claim 1, wherein the address storage means and the data storage means comprise a plurality of registers, and the address output means and the data output means are operable to receive addresses or data output from the plurality of latches, And a multiplexer for outputting data, and a tri-state buffer for receiving an address or data output from the multiplexer as an input and outputting the received address or data according to a predetermined control signal from the bus cycle controller. Back cycle processing device. There is provided a method for processing a write back cycle in a multiprocessor system having at least two processor boards in which a secondary cache is mounted outside the processor and the processor boards are connected based on a bus, Storing the address and data of the alternate writeback cycle generated by the processor in its own processor board; And comparing the address of the stored alternate write back cycle with the address on the system bus driven by another processor board. If the addresses are the same, the address and data of the stored alternate write back cycle are stored in a shared memory And if the processor again requests a new cache line fill, the new cache line fill address and data are checked for a memory location to resist, and if there is a memory location, And then writing back the stored replacement writeback address and data to the shared memory by proceeding with a system bus cycle. ※ Note: It is disclosed by the contents of the first application.