KR980012566A - Method of erasing nonvolatile semiconductor memory device - Google Patents

Abstract

The present invention relates to a method of erasing a nonvolatile semiconductor memory device in which a positive voltage is applied to a control gate when data stored in a memory cell is erased, wherein the voltage difference between the source region of the memory cell and the semiconductor substrate is +5 volts The reliability of the nonvolatile semiconductor memory device can be improved by suppressing the occurrence of hot holes due to tenneling between the bands. It is possible to simplify the configuration of the circuit for applying a positive voltage of at least 0 volts to the control gate to apply the voltage to the control gate during programming, reading and erasing operations of the flash memory cell. Thus, high integration of the nonvolatile semiconductor memory device can be realized.

Description

Method of erasing nonvolatile semiconductor memory device

FIG. 1 is a cross-sectional view showing a memory cell structure of a conventional nonvolatile semiconductor memory device.

1, a memory cell includes a p-type semiconductor substrate 10 and source and drain regions 14 and 16 of an n-type impurity are formed in the semiconductor substrate 10 with a channel 12 therebetween Have; An oxide film 17, a floating gate 18, an ONO film 19, and a control gate 20 are sequentially formed on the channel 12 to partially over the source and drain regions 14 and 16 He said; Vb, Vs, Vd, Vg, 1, 2, 3, 4 (hereinafter, referred to as "Vg") to which a predetermined voltage is externally applied to the semiconductor substrate 10, the source 14, the drain 16 and the control gate 20, ) Is connected

The operation of the conventional unsolicited semiconductor memory device, that is, the flash memory, causes hot electron injection in the floating gate 18 in the channel region 12 adjacent to the drain region 16, The cell is programmed meaning that electrons are accumulated in the floating gate 18 formed between the oxide film 17 and the ONO film 19 on the channel 12. [ In the injection method, a voltage of 0 V is applied to the semiconductor substrate 10 through the power terminals 1 and 2 of the source region 14. A high voltage of about +12 volts is applied to the control gate 20 and a positive voltage of about 6 to 7 volts is applied to the drain region 16 to generate hot electrons, Electrons are injected. Negative charges are accumulated in the floating gate 18 by the program gate. Thus, the negative potential of the floating gate 18 serves to raise the threshold voltage of the memory cell to a predetermined level during a series of read operations. The reading of the data stored in the memory cell applies a positive voltage of about 1-2 volts to the drain region 16 of the memory cell. Then, a predetermined voltage or a power source voltage is applied to the control gate 20 and 0 volts is applied through the power source terminal of the source region 14.

Although not shown in the figure, all the memory cells of the flash memory cell array are simultaneously erased because each source region 14 of the memory cell is connected by a common source line (CSL). The high voltage of about 12 volts is applied to the common source line CSL of the memory cell and the zero voltage is applied to the control gate 20 and the semiconductor substrate 10, Negative charges are simultaneously erased. At this time, the drain region 16 is maintained in a high impedance state, that is, a floating state, in order to enhance the erase effect. A strong electric field is formed between the control gate 20 and the source region 14 by the above-described erase method. As a result, Fowler-Nordheim tunneling (F-N tenneling) occurs and negative charges accumulated in the floating gate 18 are discharged to the source region 14. Typically, the F-N tunneling occurs when an electric field of 6 - 7 MV / cm is applied between the oxide films 17. Since the oxide film 17 formed between the floating gate 18 and the source region 14 is thinly formed to a thickness of about 100 angstroms or less, F-N tunneling is possible. 2 shows the voltages applied to the power supply terminals 1, 2, 3 and 4 in the program, read and erase operations for a typical flash memory cell

However, the above-described method of erasing the nonvolatile semiconductor memory device has the following problems.

First, various voltages (+6 - +9 volts, +5 volts, +12 volts) are applied to the source and train regions 14 and 16 while the program, read and erase operations are performed. Therefore, in order to operate the semiconductor memory device having the memory cell, two or more kinds of voltages are required. Users using flash memory want to operate the semiconductor memory device with only +5 volts voltage. A high voltage of +12 volts is applied to the source region 14 in order to erase the data stored in the memory cell of the flash memory. At this time, a leakage current of about several tens nA or more per memory cell flows from the source region 14 to the semiconductor substrate 10. When data stored in memory cells of 512 kbit or more are erased, a leakage current of about 20-300 mA flows. Therefore, it is difficult to supply the leakage current by using a charge pump circuit in the semiconductor device. Therefore, a high voltage of +12 volts applied to the source region 14 in the erase operation of the memory cell must be applied from the outside.

Second, a high voltage of +12 volts in the reverse direction is applied between the source region 14 and the semiconductor substrate 10. A dubble-diffused architecture (as disclosed in detail in patent publication number 4698787), invented by Mukherjee in October 1987, provides a breakdown caused by the reverse high voltage of the PN junction . However, the double-diffused structure requires a relatively large area compared to a single-diffused architecture. As a result, there is a difficulty in realizing high integration of the nonvolatile semiconductor device

Third, a high-energy hot hole (hot), which is caused by an avalanche effect or a band-to-band conduction mechanism in the source region 14 to which a high high voltage is applied, hole. The hot holes generated in the source region 14 are trapped in the oxide film 17 formed between the channel 12 and the floating gate 18. The hot hole generation phenomenon is described in detail in " Drainholes Avalanche and Hole-Trapping Induced Gate Leakage in Thin-Oxide MOS Devices "issued to IEEE Electron Device Letters, chi clang, Hot holes or holes trapped in the oxide film 17 move to the floating gate 18 by a series of program, read and erase operations to neutralize the negative charges accumulated in the floating gate 18 Thereby causing interference that moves the threshold voltage of the memory cell to the negative region. This is called a gate disturb phenomenon or a charge loss phenomenon. If the hot holes formed in the source region 14 of the memory cell are trapped in the oxide film 17, the data stored in the plurality of memory cells can not be erased simultaneously. In addition, the hot holes reduce the charge retention time of the floating gate 18 by neutralizing negative charges in the floating gate 18. The memory cell having the oxide film 17 capturing the hot hole is easily interfered with compared to the memory cell in which holes are not trapped in the oxide film 17 during the program operation of the adjacent memory cell. Therefore, the holes trapped in the oxide film 17 between the floating gate 18 and the semiconductor substrate 10 are electrically connected to the programming characteristics of the erased cell and the floating gate 18, Thereby deteriorating the grip retention characteristic

In order to solve the above-mentioned problem of the erase method, a negative voltage, which is disclosed in detail in the "Flash EEPROM Array with Negative Gate Voltage Erase Operation ", Patent Publication No. 5077691 published on Dec. 31, Was introduced. FIG. 3 shows the voltages applied to the respective power terminals in the erase operation of the flash memory cell using the negative voltage. A negative voltage of about 12-17 volts is applied to the control gate 20 of each memory cell to erase the data stored in the selected memory cell among the flash memory cells, do. Then, a positive voltage of about 0.55 volts is applied to the source region 14, and the drain region 16 is maintained in a high impedance state. A strong electric field is formed between the control gate 20 and the source region 14 by the voltage application method as described above. As a result, negative charges accumulated in the floating gate 18 are discharged to the source region 14 by the FN tunneling. Further, a reverse voltage of +5 volts or less between the source region 14 and the semiconductor substrate 10 The leakage current flowing from the source region 14 to the semiconductor substrate 10 can be reduced. The low reverse voltage between the source region 14 and the semiconductor substrate 10 becomes equal to or lower than the power source voltage applied from the outside and the erase operation can be performed by the same voltage as the power source voltage.

In the erase operation, the source region 14 has a double-diffused structure due to a high voltage difference (about +12 volts) between the source region 14 and the semiconductor substrate 10, The source region 14 can be realized as a single-diffused structure by a low voltage difference between the semiconductor substrate 10 and the semiconductor substrate 10. In addition, since the source region 14 can be realized in a single-diffused structure, high integration of the nonvolatile semiconductor memory device can be realized. The reduced voltage between the source region 14 and the semiconductor substrate 10 reduces the occurrence of hot holes due to the "avalanche effect mechanism ", thereby greatly improving the reliability of the flash memory. ) Requires +12 volts for program operation and -12 volts for erase operation. This voltage can be implemented by a charge pump having a small capacity because a large current consumption is not generated.

However, according to the erase method using the negative voltage as described above, a circuit for generating -12 volts to be applied to the control gate 20 in the erase operation and a circuit for generating the generated negative voltage to the control gate 20 It is difficult to implement the circuit of the part to be processed. A circuit diagram (detailed in Patent Publication No. 5077691) used for applying the negative voltage to the control gate in the AMD company shown in Fig. 4 is shown. According to the circuit diagram shown in Fig. 4, -2 volts must be applied to the gate of the PMOS transistor Q2 to cut off the PMOS transistor 02 in the erase operation. The PMOS transistors Q1, Q2 and Q4 must be constructed so as to withstand a reverse voltage of +18 volts or more between the source and drain regions (-13 volts) and the semiconductor substrate (+5 volts). In order to withstand a high reverse voltage of +18 volts or more, the source and drain regions 14 and 16 must have a double-diffused structure. Therefore, in the configuration of a circuit for applying a specific voltage to the control gate 20, the size of one memory cell must be configured as shown in FIG. 4. Therefore, when the double-diffused structure is used, Which is difficult to realize.

Therefore, an object of the present invention is to provide a method of erasing a non-volatile semiconductor memory device which applies a positive voltage to a control gate when erasing data stored in a memory cell.

FIG. 1 is a cross-sectional view showing a memory cell structure of a conventional nonvolatile semiconductor memory device; FIG.

FIG. 2 is a view showing a voltage applied to each operation mode of FIG. 1; FIG.

FIG. 3 is a cross-sectional view showing a memory cell structure of a conventional nonvolatile semiconductor memory device and a voltage applied in an erase operation; FIG.

4 is a circuit diagram showing a circuit for supplying a negative voltage;

FIG. 5 is a cross-sectional view showing a memory cell structure of a non-volatile semiconductor memory device according to a preferred embodiment of the present invention and a voltage applied in an erase operation,

DESCRIPTION OF REFERENCE NUMERALS

10: semiconductor substrate 12: channel

14: source region 16: drain region

18: floating gate 20: control gate

According to an aspect of the present invention, there is provided a semiconductor device comprising: a P-type semiconductor substrate; source and drain regions of N-type impurities are formed in the semiconductor substrate with a channel therebetween; An oxide film, a floating gate, an ONO film, and a control gate are sequentially formed on the channel in an upper portion of the source and drain regions; A method for erasing a nonvolatile semiconductor memory device having a plurality of memory cells connected to a power source terminal to which a predetermined voltage is externally applied to each of a semiconductor substrate, a source, a drain, and a control gate, A first high voltage is applied, and a ground voltage is applied through a power supply terminal of the gate gate; And the second high voltage is applied through the power supply terminal of the source.

In a preferred embodiment of the method, the first high voltage applied to the semiconductor substrate is applied in a range of about +12 - +16 volts.

In a preferred embodiment of the method, the second high voltage applied to the source region is applied in a range of about +13 - +17 volts.

In a preferred embodiment of the method, the drain region is maintained in a high impedance state.

In a preferred embodiment of the method, the source and the drain regions are formed in a single-diffused structure.

In a preferred embodiment of the method, the source region is connected to adjacent cells by a diffusion layer.

With this method, it is possible to implement a method of erasing a nonvolatile semiconductor memory device which can erase data stored in a memory cell by applying a voltage applied to the control gate at a positive voltage.

Reference will now be made in detail to the preferred embodiments of the present invention with reference to FIG. 5, a method for erasing a nonvolatile semiconductor memory device according to the present invention comprises a P-type semiconductor substrate 10, a source of N-type impurities with a channel 12 sandwiched between the semiconductor substrate 10 and the channel 12, And drain regions (14, 16) are formed; An oxide film 17, a floating gate 18, an ONO film 19, and a control gate 20 are sequentially formed on the channel 12 to partially over the source and drain regions 14 and 16 He said; A plurality of memory cells (1, 2, 3, 4) to which power terminals (1, 2, 3, 4) to which a predetermined voltage is applied are applied to the semiconductor substrate (10), the source (14), the drain Wherein a first high voltage is applied through a power supply terminal (1) of the semiconductor substrate (10) and a ground voltage is applied through a power supply terminal (4) of the control gate (20) Lt; / RTI > And the second high voltage is applied through the power supply terminal 2 of the source region 14. Here, the first high voltage applied to the semiconductor substrate 10 is applied in a range of about +12 - +16 volts. The second high voltage applied to the source region 14 is applied in a range of about +13 - +17 volts.

According to this erase method, the memory. Not only the voltage difference between the source region 14 of the cell and the semiconductor substrate 10 can be reduced to +5 volts, but also the occurrence of hot holes due to interband tunneling is suppressed to improve the reliability of the nonvolatile semiconductor memory device Can be improved. It is possible to simplify the structure of the circuit for applying a voltage to the control gate 20 only by applying a positive voltage of at least 0 volts to the control gate during programming, reading and erasing operations of the flash memory cell. Thus, high integration of the nonvolatile semiconductor memory device can be realized.

In Fig. 5, the same reference numerals are used for components having the same functions as the components shown in Figs. 1 to 4. Fig.

FIG. 5 shows a memory cell structure of a nonvolatile semiconductor memory device according to a preferred embodiment of the present invention and a cross-sectional view illustrating a voltage applied during an erase operation.

Referring to FIG. 5, the P-type semiconductor substrate 10 and the P- Source and drain regions 14 and 16 of an N-type impurity are formed in the semiconductor substrate 10 with a channel 12 therebetween; An oxide film 17, a floating gate 18, an ONO film 19, and a control gate 20 are sequentially formed on the channel 12 to partially over the source and drain regions 14 and 16 He said; A plurality of memory cells connected to the power source terminals 1, 2, 3 and 4 to which a predetermined voltage is externally applied are connected to the semiconductor substrate 10, the source 14, the drain 16 and the control gate 20, Wherein a first high voltage is applied through the power supply terminal (1) of the semiconductor substrate (10) and the power supply terminal (4) of the control gate (20) And the second high voltage is applied through the power supply terminal 2 of the source region 14. [ Here, the first high voltage applied to the semiconductor substrate 10 is about +12 - +16 volts, and the second high voltage applied to the source region 14 is about +13 - +17 volts Lt; / RTI > Then, the drain region 16 is maintained in a high impedance state. The source and drain regions 14 and 16 are of a single-diffused structure and the source region 14 is connected to neighboring memory cells by a diffusion layer.

When data stored in the memory cell is erased, as shown in FIG. 5, voltages are applied to the power supply terminals 1, 2, 3 and 4 as follows. A voltage of 0 volts is applied to the control gate 20 and a voltage of +13 - + l7 volts is applied through the power source terminal of the source region 14. [ A voltage of +12 - +16 volts is applied to the semiconductor substrate 10 and a drain region 16 is maintained in a high impedance state, that is, a floating state. A strong electric field is formed in the direction of the control gate 20 in the source region 14 where negative charges are accumulated. By this electric field, the negative charge accumulated in the hot electron injection during the program operation is discharged to the source region 14 to reduce the threshold voltage of the memory cell and erase the data of the programmed cell

As described above, not only the voltage difference between the source region of the memory cell and the semiconductor substrate can be reduced to +5 volts, but also the occurrence of hot holes due to interband tunneling is suppressed to improve the reliability of the nonvolatile semiconductor memory device Can be improved. It is possible to simplify the structure of the circuit for applying a positive voltage of at least 0 volts to the control gate and applying the voltage to the control gate in the program / read erase operation of the flash memory cell. Thus, high integration of the nonvolatile semiconductor memory device can be realized.

Claims (6)

Source and drain regions 14 and 16 of an N-type impurity are formed in the semiconductor substrate 10 with a channel 12 interposed therebetween. A floating gate 18, an ONO film 19, and a control gate 20 are sequentially formed on an upper portion of the source and drain regions 14 and 16; A plurality of memory cells connected to the power source terminals 1, 2, 3 and 4 to which a predetermined voltage is externally applied are connected to the semiconductor substrate 10, the source 14, the drain 16 and the control gate 20, Wherein a first high voltage is applied through a power supply terminal (1) of the semiconductor substrate (10) and a ground voltage is applied through a power supply terminal (4) of the control gate (20) Lt; / RTI > And a second high voltage is applied through the power supply terminal (2) of the source region (14). The method of claim 1, wherein the first high voltage applied to the semiconductor substrate (10) is applied in a range of about +12 - +16 volts. The method of claim 1, wherein the second high voltage applied to the source region (14) is applied in a range of about +13 - + 17 volts. 2. The method of claim 1, wherein the drain region (16) is maintained in a high impedance state during an erase operation. The method of claim 1, wherein the source and drain regions (14, 16) are formed in a single-diffused structure. 2. The method according to claim 1, wherein the source region (14) is connected to adjacent cells by a diffusion layer. ※ Note: It is disclosed by the contents of the first application.