KR980012142A - Semiconductor lead frame - Google Patents
Semiconductor lead frame Download PDFInfo
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- KR980012142A KR980012142A KR1019960028613A KR19960028613A KR980012142A KR 980012142 A KR980012142 A KR 980012142A KR 1019960028613 A KR1019960028613 A KR 1019960028613A KR 19960028613 A KR19960028613 A KR 19960028613A KR 980012142 A KR980012142 A KR 980012142A
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- semiconductor
- semiconductor chip
- lead frame
- heat sink
- heat
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 230000017525 heat dissipation Effects 0.000 claims abstract description 5
- 238000005336 cracking Methods 0.000 abstract description 2
- 238000007599 discharging Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 9
- 230000001681 protective effect Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- -1 polyethylene Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229920001169 thermoplastic Polymers 0.000 description 2
- 239000004416 thermosoftening plastic Substances 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 239000004743 Polypropylene Substances 0.000 description 1
- 239000004793 Polystyrene Substances 0.000 description 1
- XTXRWKRVRITETP-UHFFFAOYSA-N Vinyl acetate Chemical compound CC(=O)OC=C XTXRWKRVRITETP-UHFFFAOYSA-N 0.000 description 1
- BZHJMEDXRYGGRV-UHFFFAOYSA-N Vinyl chloride Chemical compound ClC=C BZHJMEDXRYGGRV-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000001311 chemical methods and process Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229920006122 polyamide resin Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
본 발명은 반도체 칩과의 배선을 위하여 연속적으로 마련되는 단위 프레임과 열방출을 위해 상기 반도체 칩의 하면과 접합되어 있는 방열판을 포함하는 반도체 리드프레임에 있어서, 상기 방열판은 상기 반도체 칩과 접합되어 있는 면의 반대면에 홈이 형성되어 있는 것을 특징으로 하는 반도체 리드프레임을 제공한다. 본 발명에 따르면, 반도체 칩으로부터 발생되는 열을 효과적으로 방출시킴로써 열적 변형에 의한 반도체 칩의 크랙을 효과적으로 방지할 수 있을 뿐만 아니라, 신뢰성이 우수한 반도체 팩키지를 얻을 수 있다.The present invention provides a semiconductor lead frame including a unit frame continuously provided for wiring with a semiconductor chip and a heat sink coupled to a lower surface of the semiconductor chip for heat dissipation, wherein the heat sink is bonded to the semiconductor chip And a groove is formed on the opposite surface of the semiconductor chip. According to the present invention, it is possible to effectively prevent cracking of the semiconductor chip due to thermal deformation by effectively discharging heat generated from the semiconductor chip, and also to obtain a semiconductor package having excellent reliability.
Description
본 발명은 반도체 리드프레임에 관한 것으로서, 열방출 효과가 우수한 방열판이 구비된 반도체 리드프레임에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor lead frame, and more particularly, to a semiconductor lead frame having a heat dissipating plate.
반도체 리드프레임은 반도체 기판과 함께 반도체 팩키지를 이루는 핵심 구성 요소중의 하나이다. 여기에서 반도체 리드프레임은 반도체 팩키지의 내부와 외부를 연결해주는 도선의 역할과 반도체 칩을 지지해주는 지지체의 역할을 동시에 한다.Semiconductor leadframes are one of the key components of semiconductor packages together with semiconductor substrates. Here, the semiconductor lead frame serves both as a conductor for connecting the inside and the outside of the semiconductor package and as a support for supporting the semiconductor chip.
상기 반도체 리드프레임은 기억소자인 칩을 탑재하여 정적인 상태로 유지하여 주는 패드와 와이어 본딩에 의해 칩내 소자의 각 단자와 연결되는 내부리드 및 기판과의 납땜을 위한 외부리드를 구비하고 있다.The semiconductor lead frame includes a pad for holding a chip as a storage element and holding it in a static state, an inner lead connected to each terminal of the device by wire bonding, and an outer lead for soldering to the substrate.
반도체 리드프레임은 통상 스탬핑(stamping)공정이나 에칭(etching)공정에 의하여 제조된다. 여기에서 스탬핑 공정은 프레스 금형장치를 이용하여 박판의 소재를 소정 형상으로 타발하는 것으로서, 대량생산시 주로 이용되는 방법이다. 에칭공정은 화학약품을 이용하여 소재의 국소부위를 부식시킴으로써 제품을 형성해 나가는 화학적 방법으로서, 소량생산시 주로 이용되는 공정이다.The semiconductor lead frame is usually manufactured by a stamping process or an etching process. Here, the stamping process is a method of stamping a material of a thin plate into a predetermined shape using a press die apparatus, and is mainly used in mass production. The etching process is a chemical process that forms a product by corroding a local part of a material by using a chemical, and is a process mainly used in a small amount of production.
반도체 리드프레임은 상기 스탬핑공정 또는 에칭공정을 이용하여 제조되어 기억소자인 칩 등 다른 부품과의 조립과정을 거쳐 반도체 팩키지를 이루게 된다.The semiconductor lead frame is manufactured using the stamping process or the etching process, and is assembled with other components such as a chip, which is a memory device, to form a semiconductor package.
최근, 반도체 칩의 고집적화, 박형화 및 소형화추세에 따라 리드프레임도 소형화되고 있는 추세이다. 이렇게 반도체 칩이 고집적화, 고밀도화되면 집적회로의 소비전력이 증가하게 되고, 이로 인하여 반도체 리드프레임에 우수한 방열성이 요구되어진다.2. Description of the Related Art In recent years, leadframes have also been downsized due to high integration, thinness and miniaturization of semiconductor chips. When the semiconductor chip is highly integrated and densified, the power consumption of the integrated circuit is increased, and the semiconductor lead frame is required to have excellent heat dissipation.
도 1은 방열판이 보호막에 완전히 덮여 있는 형태 즉, 내장형 방열판(heat sink)이 구비되어 있는 반도체 팩키지를 개략적으로 나타낸 도면이고, 도 2는 방열판 일부가 보호막의 외부로 노출되어 있는 형태 즉, 노출형 방열판(heat spread)이 구비된 반도체 팩키지를 개략적으로 나타낸 도면이다.FIG. 1 is a schematic view of a semiconductor package in which a heat sink is completely covered with a protective film, that is, a semiconductor package having a built-in heat sink. FIG. 2 is a cross- FIG. 1 is a schematic view of a semiconductor package having a heat spread.
도 1과 도 2를 동시에 참조하면, 리드 (12) 및 (22)의 하부에 절연테이프층 (13) 및 (23)이 형성되어 있고, 이 절연 테이프층에 테두리영역이 맞닿도록 방열판 (16) 및 (26)이 부착되어 있다. 그러므로 상기 방열판 (16) 및 (26)은 상기 리드프레임의 중앙 공간으로 그 상면 일부가 노출되어 있으며, 그 노출 부위상에 반도체 칩 (11) 및 (21)이 탑재된 구조를 이루고 있다.Referring to FIGS. 1 and 2, the insulating tape layers 13 and 23 are formed under the leads 12 and 22, and the heat radiating plate 16 is bonded to the insulating tape layer, And 26 are attached. Therefore, the heat sinks 16 and 26 are partially exposed from the central space of the lead frame, and the semiconductor chips 11 and 21 are mounted on the exposed portions.
상기 반도체 칩 (11) 및 (21)의 내부 기억소자와 내부리드는 본딩 와이어 (14) 및 (24)에 의하여 연결되어 있으며, 내부리드의 외측에는 기판과의 접촉을 위한 외부리드가 구비되어 있다.The internal leads and the internal leads of the semiconductor chips 11 and 21 are connected by bonding wires 14 and 24 and external leads for contact with the substrate are provided outside the internal leads .
상기 리드프레임의 상면과 하면에는 에폭시 수지 등의 몰딩을 통하여 형성된 보호막 (15) 및 (25)이 구비되어 있다.On the top and bottom surfaces of the lead frame, protective films 15 and 25 formed through molding of epoxy resin or the like are provided.
상기와 같은 구조를 갖는 반도체 팩키지에 전기를 인가하면, 반도체 칩에 소정의 열이 발생된다. 그러나, 상기 방열판들이 반도체 칩으로부터 발생된 열을 방출시키는 능력이 충분치 않다. 그 결과, 반도체 칩이 열적 변화를 받게 되어 냉각과정에서 내부응력이 발생된다. 이러한 내부응역으로 인하여 빈틈이 생기고 이 빈틈에 수분 등이 침투되어 반도체 칩에 크랙이 발생된다.When electricity is applied to the semiconductor package having the above-described structure, predetermined heat is generated in the semiconductor chip. However, the ability of the heat sinks to emit heat generated from the semiconductor chip is not sufficient. As a result, the semiconductor chip is subjected to thermal change, and internal stress is generated in the cooling process. Due to this internal reaction, gaps are formed and moisture penetrates into the gaps and cracks are generated in the semiconductor chips.
본 발명이 이루고자 하는 기술적 과제는, 반도체 칩으로부터 방출된 열을 효과적으로 방출시킬 수 있는 방열판을 구비함으로써 열적 변화에 대한 영향이 최소화된 반도체 리드프레임을 제공함에 그 목적을 두고 있다.SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor lead frame in which the influence of thermal change is minimized by providing a heat sink capable of effectively emitting heat emitted from a semiconductor chip.
제1도는 종래의 내장형 방열판이 구비된 리드프레임을 포함하는 반도체 팩키지를 개략적으로 나타낸 단면도이고,FIG. 1 is a cross-sectional view schematically showing a semiconductor package including a lead frame having a conventional built-in heat sink,
제2도는 종래의 노출형 방열판이 구비된 리드프레임을 포함하는 반도체 팩키지를 개략적으로 나타낸 단면도이고,FIG. 2 is a cross-sectional view schematically showing a semiconductor package including a lead frame having a conventional exposed heat sink,
제3도는 본 발명의 바람직한 일실시예에 따른 내장형 방열판이 구비된 리드프레임을 적용한 반도체 팩키지를 개략적으로 나타낸 단면도이고,FIG. 3 is a cross-sectional view schematically showing a semiconductor package to which a lead frame having a built-in heat sink according to a preferred embodiment of the present invention is applied,
제4도는 본 발명의 바람직한 일실시예에 따른 노출형 방열판이 구비된 리드프레임을 적용한 반도체 팩키지를 개략적으로 나타낸 단면도이다.FIG. 4 is a cross-sectional view schematically illustrating a semiconductor package to which a lead frame having an exposed heat sink according to a preferred embodiment of the present invention is applied.
* 도면의 주요 부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
11, 21, 31, 41. 반도체 칩 12, 22, 32, 42. 리드11, 21, 31, 41. Semiconductor chips 12, 22, 32, 42. Lead
13, 23, 33, 43. 절연 테이프층 14, 24, 34, 44. 본딩 와이어13, 23, 33, 43. Isolation tape layer 14, 24, 34, 44. Bonding wire
15, 25, 35, 45. 보호막 16, 26, 36, 46. 방열판15, 25, 35, 45. Protective film 16, 26, 36, 46. Heat sink
상기 과제를 이루기 위하여 본 발명에서는 반도체 칩과의 배선을 위하여 연속적으로 마련되는 단위 프레임과 열방출을 위해 상기 반도체 칩의 하면과 접합되어 있는 방열판을 포함하는 반도체 리드프레임에 있어서, 상기 방열판은 반도체 칩과 접합되어 있는 면의 반대면에 홈이 형성되어 있는 것을 특징으로 하는 반도체 리드프레임을 제공한다.According to an aspect of the present invention, there is provided a semiconductor lead frame including a unit frame continuously provided for wiring with a semiconductor chip and a heat sink connected to a lower surface of the semiconductor chip for heat dissipation, And a groove is formed on a surface opposite to a surface bonded to the semiconductor chip.
본 발명은 내장형 또는 노출형 방열판의 하면에 홈을 형성하여 방열판의 표면적을 확대시킴으로써 열방출 효과를 최대화시키고자 함에 그 특징을 두고 있다.The present invention is characterized in that grooves are formed in the lower surface of the built-in or exposed heat sink to maximize the heat radiation effect by enlarging the surface area of the heat sink.
본 발명의 바람직한 일실시예에 따른 반도체 팩키지는 본 발명을 특징지우는 방열판을 제외하고는, 종래의 반도체 팩키지와 동일한 구조를 가지고 있다.A semiconductor package according to a preferred embodiment of the present invention has the same structure as a conventional semiconductor package except for a heat sink which characterizes the present invention.
도 3은 본 발명의 바람직한 일실시예에 따른 내장형 방열판이 구비된 리드프레임을 적용한 반도체 팩키지를 개략적으로 나타낸 단면도이고, 도 4는 본 발명의 바람직한 일실시예에 따른 노출형 방열판이 구비된 리드프레임을 적용한 반도체 팩키지를 개략적으로 나타낸 단면도이다.3 is a cross-sectional view schematically showing a semiconductor package to which a lead frame having a built-in heat sink according to an exemplary embodiment of the present invention is applied. FIG. 4 is a cross-sectional view illustrating a lead frame having an exposed heat sink according to a preferred embodiment of the present invention. Sectional view schematically showing a semiconductor package to which the present invention is applied.
도 3과 도 4를 참조하면, 리드 (32) 및 (42)의 하부에 절연 테이프층 (33) 및 (43)이 각각 형성되어 있다. 여기에서 절연 테이프층은 리드와 방열판을 서로 고정하는 역할을 하며, 기저 필름을 중심으로 하고 그 양면에 열가소성 필름이 형성되어 있는 3층 구조를 가지고 있다.Referring to FIGS. 3 and 4, insulating tape layers 33 and 43 are formed below the leads 32 and 42, respectively. The insulating tape layer serves to fix the lead and the heat sink to each other, and has a three-layer structure in which a thermoplastic film is formed on both sides of the base film as a center.
상기 기저필름은 폴리이미드로 형성되는 것이 바람직하며, 상기 열가소성 필름은 염화비닐수지, 초산비닐수지, 폴리스티렌, 아크릴수지, 폴리에틸렌, 폴리프로필렌, 불소수지, 폴리아미드 수지, 폴리카보네이트, 폴리에테르 이미드 및 폴리이미드중에서 선택된 수지로 형성된다.The base film is preferably formed of polyimide, and the thermoplastic film may be formed of at least one selected from the group consisting of a vinyl chloride resin, a vinyl acetate resin, a polystyrene, an acrylic resin, a polyethylene, a polypropylene, a fluororesin, a polyamide resin, a polycarbonate, And polyimide.
상기 절연 테이프층 (33) 및 (43)에 테두리 영역이 맞닿도록 방열판 (36) 및 (46)이 부착되어 있다. 이러한 방열판은 상기 리드프레임의 중앙 공간으로 그 상면 일부가 노출되어 있으며, 그 노출 부위에 접착제가 도포되어 있고 그 위에 반도체 칩 (31) 및 (41)이 안착되어 있다.And heat dissipation plates 36 and 46 are attached to the insulating tape layers 33 and 43 so that the edge regions thereof are in contact with each other. The heat radiating plate is partially exposed to the center space of the lead frame, and an adhesive is applied to the exposed portion, and the semiconductor chips 31 and 41 are seated thereon.
상기 반도체 칩의 내부 기억소자와 내부리드는 본딩 와이어 (34) 및 (44)에 의하여 연결되어 있으며, 내부리드의 외측에는 기판과의 접촉을 위한 외부리드가 구비되어 있다.Internal memory elements of the semiconductor chip and internal leads are connected by bonding wires 34 and 44, and external leads for contact with the substrate are provided outside the internal leads.
상기 리드프레임의 상면과 하면에는 에폭시 수지 등의 몰딩을 통하여 형성된 보호막 (35) 및 (45)이 구비되어 있다.The upper and lower surfaces of the lead frame are provided with protective films 35 and 45 formed through molding of epoxy resin or the like.
상기 방열판 (36) 및 (46)에서는 반도체 칩 (31) 및 (41)과 접합되는 면의 반대면에 홈이 형성되어 있다. 이러한 방열판은 프레스를 이용하여 소정, 변형시킴으로써 제조할 수 있다.In the heat dissipating plates 36 and 46, grooves are formed on the opposite surfaces of the surfaces to be bonded to the semiconductor chips 31 and 41. Such a heat sink can be manufactured by pressing and deforming it in a predetermined manner.
본 발명에서는 방열판 후면에 형성된 홈을 형상이 특별히 제한되지 않으나, 그 방열판의 표면적을 최대화시킬 수 있는 홈의 형상이 바람직하다.In the present invention, the shape of the groove formed on the back surface of the heat sink is not particularly limited, but a groove shape that maximizes the surface area of the heat sink is preferable.
본 발명에 따르면, 반도체 칩으로부터 발생되는 열을 효과적으로 방출시킴로써 열적 변형에 의한 반도체 칩의 크랙을 효과적으로 방지할 수 있을 뿐만 아니라, 신뢰성이 우수한 반도체 팩키지를 얻을 수 있다.According to the present invention, it is possible to effectively prevent cracking of the semiconductor chip due to thermal deformation by effectively discharging heat generated from the semiconductor chip, and also to obtain a semiconductor package having excellent reliability.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960028613A KR100195158B1 (en) | 1996-07-15 | 1996-07-15 | Semiconductor lead frame |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960028613A KR100195158B1 (en) | 1996-07-15 | 1996-07-15 | Semiconductor lead frame |
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| Publication Number | Publication Date |
|---|---|
| KR980012142A true KR980012142A (en) | 1998-04-30 |
| KR100195158B1 KR100195158B1 (en) | 1999-06-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019960028613A KR100195158B1 (en) | 1996-07-15 | 1996-07-15 | Semiconductor lead frame |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100799562B1 (en) * | 2002-03-25 | 2008-01-31 | 페어차일드코리아반도체 주식회사 | Semiconductor power module and method for fabricating the same |
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1996
- 1996-07-15 KR KR1019960028613A patent/KR100195158B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100799562B1 (en) * | 2002-03-25 | 2008-01-31 | 페어차일드코리아반도체 주식회사 | Semiconductor power module and method for fabricating the same |
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| KR100195158B1 (en) | 1999-06-15 |
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