KR980012111A - Manufacturing Method of Gear Type Heterojunction Bipolar Transistor - Google Patents
Manufacturing Method of Gear Type Heterojunction Bipolar Transistor Download PDFInfo
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- KR980012111A KR980012111A KR1019960028762A KR19960028762A KR980012111A KR 980012111 A KR980012111 A KR 980012111A KR 1019960028762 A KR1019960028762 A KR 1019960028762A KR 19960028762 A KR19960028762 A KR 19960028762A KR 980012111 A KR980012111 A KR 980012111A
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- 238000000034 method Methods 0.000 claims abstract description 41
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- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000001020 plasma etching Methods 0.000 claims abstract description 8
- 238000007747 plating Methods 0.000 claims abstract description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- 239000010931 gold Substances 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 7
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- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010953 base metal Substances 0.000 claims description 4
- 239000011651 chromium Substances 0.000 claims description 4
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- 239000000463 material Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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- 230000005855 radiation Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
- H01L29/66318—Heterojunction transistors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
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- H01L21/02395—Arsenides
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02463—Arsenides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42304—Base electrodes for bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
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Abstract
본 발명은 단위 능동 소자를 방사형상을 배치하여 열적 특성을 개선한 기어형 이종접합 바이폴라 트랜지스터의 제조방법에 관한 것으로, 다수개의 단위능동소자를 방사형상으로 배열하여 기어형 이종접합 바이폴라 트랜지스터를 형성한 후 절연영역 상면에 크롬을 얇게 증착하고 그 상면에 금을 증착하여 리프트오프 공정에 의해 금속패드를 형성하며, 포스트 마스크로 접촉창을 형성한 후 공중배선공정을 통하여 단위능동소자의 에미터전극을 금속패드에 연결하며, 상기 기판의 뒷면을 연마하고 반응성이온식각 공정으로 비아홀을 형성한 후, 금으로 도금하여 금속패드와 접지를 연결하는 공정으로 실현되는 기어형 이종접합 바이폴라 트랜지스터 제조방법을 구비함으로써 소자에서 발생되는 열을 골고루 분포시켜 모든 단위능동소자가 비슷한 온도 분포를 갖도록 함과 동시에 단위능동소자를 최단거리로 접지금속에 연결함으로써 단위능동소자에서 발생하는 열을 빨리 방사시켜 고출력 HBT의 열파괴 현상을 효과적으로 방지할 수 있다. 또한 단위능동소자의 면적을 크게 줄여 소자크기를 최소하는 장점도 가지고 있다.The present invention relates to a method of manufacturing a gear type heterojunction bipolar transistor in which a unitary active element is arranged in a radial shape to improve thermal characteristics, and in which a plurality of unit active elements are radially arranged to form a gear type heterojunction bipolar transistor After forming a contact pad by a post-mask, the emitter electrode of the unit active device is connected to the electrode pad through a public wiring process. The method of manufacturing a heterojunction bipolar transistor according to claim 1, further comprising a step of forming a via hole by a reactive ion etching process, plating the back surface of the substrate with a metal pad, By distributing the heat generated by the device uniformly, So as to have a distribution, and at the same time by connecting the active element unit to a ground metal with the minimum distance to quickly radiate heat generated from the unit active element can be prevented from thermal destruction phenomenon of high power HBT effectively. It also has the advantage of minimizing the device size by greatly reducing the area of the unit active device.
Description
제1도는 종래의 단위능동소자를 일렬로 배열한 HBT의 평면도.1 is a plan view of an HBT in which conventional unit active elements are arranged in a line.
제2a도는 본 발명에 의한 단위능동소자의 마스크 평면도, 제2b도는 단위능동소자를 기어형으로 배열한 GSHBT의 마스크 평면도.FIG. 2a is a plan view of a mask of a unit active device according to the present invention, and FIG. 2b is a plan view of a mask of a GSHBT in which unit active elements are arranged in a gear configuration.
제3a도 내지 제3i도는 본 발명에 의한 GSHBT의 제조방법을 도시한 공정단면도 및 공정사시도.FIGS. 3a to 3i are a process sectional view and a process perspective view showing a process for producing GSHBT according to the present invention.
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
10 : 단위능동소자 11 : 기판10: unit active element 11: substrate
12 : 에미터 전극 13 : 베이스 전극12: emitter electrode 13: base electrode
14 : 콜렉터 전극 15 : 절연영역14: collector electrode 15: insulating region
16a : 베이스 금속패드 16b : 에미터 금속패드16a: base metal pad 16b: emitter metal pad
16c : 콜렉터 금속패드 17 : 공중배선16c: collector metal pad 17: aerial wiring
18 : 비아홀 19 : 접지금속18: via hole 19: ground metal
20 : 콜렉터층 21 : 베이스층20: collector layer 21: base layer
22 : 에미터층22: Emitter layer
본 발명은 이종접합 바이폴라 트랜지스터(Heterojunction Bipola Transisters ; HBT라 약칭함)의 제조방법에 관한 것으로, 특히 단위 능동 소자를 방사형상으로 배치하여 열적 특성을 개선한 기어형 이종접합 바이폴라 트랜지스터(Gear-shaped Heterojunction Bipola Transisters : GSHBT라 약칭함)의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing heterojunction bipolar transistors (HBTs), and more particularly, to a method of manufacturing a heterojunction bipolar transistor Bipola Transisters: abbreviated as GSHBT).
두가지 반도체 물질로 형성되어 접합된 이종접합 바이폴라 트랜지스터 (이하 HBT라 약칭함)는 두 반도체 물질의 에너지 대역갭이 달라 이종접합의 에너지 대역도가 접합 계면에서 불연속을 나타내는 특성을 소자의 응용에 적용한 것이다.Heterojunction bipolar transistors (hereinafter abbreviated as HBTs) formed of two semiconductor materials have different energy band gaps of the two semiconductor materials and are applied to the application of the characteristic that the energy band of the heterojunction exhibits discontinuity at the junction interface .
즉, 에미터의 베이스보다도 밴드 갭이 넓은 반도체를 사용해서 베이스 에미터 접합을 형성하는 것에 의해서, 베이스에서 에미터로 주입되는 소수 캐리어를 억제시킨 것이다.That is, by forming a base emitter junction using a semiconductor having a band gap wider than that of the base of the emitter, the minority carriers injected from the base to the emitter are suppressed.
이에 의해서, 에미터로부터 베이스로의 다수 캐리어의 주입효율이 높아지는 것과 동시에 베이스 농도를 높게할 수 있어 고전류 증폭율, 저베이스 저항의 트랜지스터를 실현할 수 있도록 한 것이다.As a result, the injection efficiency of the majority carriers from the emitter to the base can be increased, and the base concentration can be increased, thereby realizing a transistor with a high current amplification factor and a low base resistance.
특히, 종래의 고출력 HBT 는 단위능동소자를 일렬로 배치시키는 방법으로 설계되어 있다.In particular, the conventional high output HBT is designed by arranging unit active elements in a row.
제1도는 종래의 단위능동소자를 일려로 배열한 HBT의 평면도이다.FIG. 1 is a plan view of an HBT in which conventional unit active elements are arranged in a line.
그러나 이와같이 단위능동소자를 일려로 배치시킨 종래의 HBT 는 단위능동소자(1)에서 발생되는 열을 효과적으로 방사시키지 못해 중심부에 위치한 단위능동소자(1)의 온도가 높아짐에 따라 이 소자의 베이스-에미터 턴온(Turn-on)전압이 낮아지고 이 단위능동소자(1)를 통하여 전체 소자의 전류가 흘러 단위능동소자(1)의 이득이 감소하는 등 올바른 전력 소자로서의 기능을 잃게되는 문제가 발생되었다.However, in the conventional HBT in which the unit active elements are arranged in a line, the heat generated in the unit active element 1 can not be efficiently radiated and the temperature of the unit active element 1 located at the center becomes higher, There has been a problem that the turn-on voltage is lowered and the current of all the elements flows through the unit active element 1, thereby reducing the gain of the unit active element 1, thereby losing the function as a proper power element .
또한, 일렬로 배치된 종래의 HBT 는 열원과 접지사이의 연결경로가 길어 접지 인덕턴스가 증가되는 문제가 있었다.In addition, the conventional HBTs arranged in a row have a problem that the ground inductance is increased due to a long connection path between the heat source and the ground.
본 발명은 상술한 종래의 문제점을 극복하기 위한 것으로서, 단위능동소자를 방사형상으로 배치하고 단위능동소자를 공중배선 공정(Airbridge plating)과 비아홀(Via-hole)을 통해 접지와 최단거리로 연결함으로써 단위능동소자에서 발생하는 열을 골고루 분포시키고 열을 효율적으로 방사시켜 HBT의 열적특성을 개선하고 신뢰도를 확보할 수 있는 기어형 이종접합 바이폴라 트랜지스터(Gear-shaped Heterojunction Bipola Transisters)의 제조방법을 제공하는데 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to overcome the above-mentioned problems of the prior art, and it is an object of the present invention to provide a method of manufacturing a semiconductor integrated circuit device in which unit active elements are radially arranged and unit active elements are connected to ground and shortest distance through airbridge plating and via- The present invention provides a method of manufacturing a gear-shaped heterojunction bipolar transistor capable of uniformly distributing heat generated by a unit active element and efficiently radiating heat to improve the thermal characteristics of the HBT and ensure reliability thereof There is a purpose.
상기 목적을 실현하기 위한 본 발명은 다수개의 단위능동소자를 방사현상으로 배열하여 기어형 이종접합 바이폴라 트랜지스터를 형성한 후 절연영역 상면에 크롬(Cr)을 얇게 증착하고 그 상면에 금(Au)을 증착하여 리프트오프 (Lift off) 공정에 의해 금속패드를 형성하며, 접촉창 마스크로 접촉창을 형성한 후 공중배선공정을 통하여 단위능동소자의 에미터 전극을 패드전극에 연결하며, 상기 기판의 뒷면을 연마하고 반응성이온식각(Reactive Ion Etching ; RIE)공정으로 비아홀을 형성한 후, 금으로 뒷면을 도금하여 금속패드와 접지를 연결하는 공정으로 실현되는 기어형 이종접합 바이폴라 트랜지스터 제조방법을 제안한다.In order to achieve the above object, the present invention provides a heterojunction bipolar transistor in which a plurality of unit active elements are arranged in a radiation phenomenon to form a gear type heterojunction bipolar transistor, chromium (Cr) is deposited thinly on the upper surface of the insulating region, Forming a metal pad by a lift-off process, forming a contact window with a contact window mask, connecting the emitter electrode of the unit active element to the pad electrode through an air wiring process, , A via hole is formed by a reactive ion etching (RIE) process, and a metal pad is connected to a ground by plating the back surface with gold. The present invention also provides a method of manufacturing a heterojunction bipolar transistor of a gear type.
이하, 본 발명에 다른 바람직한 실시예를 첨부한 도면에 따라 보다 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2a도는 본 발명에 의한 단위능동소자의 마스크들의 평면도이고, 제2b도는 제2도의 단위능동소자를 기어형으로 배열한 GSHBT의 마스크 평면도이며, 제3a도 내지 제3i도는 본 발명에 의한 GSHBT의 제조방법을 도시한 단면 공정도이다.FIG. 2a is a plan view of the masks of the unit active device according to the present invention, FIG. 2b is a plan view of the mask of the GSHBT in which the unit active elements of FIG. 2 are arranged in a gear configuration, Sectional view showing the manufacturing method.
본 발명은 기판(11)상에 콜렉터층(20), 베이스층(21), 에미터층(22)으로 이루어진 동작영역을 에피텍셜 공정에 의해 방사형상으로 형성하고, 에미터층(22)의 상면에 에미터 전극(12)을 리프트오프 공정으로 형성하며, 반응성 이온식각 공정에 의한 선택적 건식 식각공정과 습식식각공정으로 에미터층(22)을 에칭하여 베이스층(21)을 노출하고 베이스층(21)의 상면에 베이스 전극(13)을 증착하며, 상기 베이스층(21)을 에칭하여 콜렉터층(20)을 노출하고 콜렉터층(20)의 상면에 콜렉터전극(14)을 증착하며, 콜렉터층(20)의 측부에 저항성 접촉을 형성한 후 절연 임프랜트 공정으로 절연영역(15)을 형성한다.The present invention is characterized in that an operating region consisting of a collector layer 20, a base layer 21 and an emitter layer 22 is formed in a radial shape by an epitaxial process on a substrate 11 and is formed on the upper surface of the emitter layer 22 The emitter electrode 12 is formed as a lift-off process, and the emitter layer 22 is etched by the selective dry etching process and the wet etching process by the reactive ion etching process to expose the base layer 21, A base electrode 13 is deposited on the upper surface of the collector layer 20 and the collector layer 20 is exposed by etching the base layer 21 to deposit a collector electrode 14 on the upper surface of the collector layer 20, ), And then an insulating region 15 is formed by an insulating imprint process.
다음에 상기 절연영역(15) 상면에 크롬을 얇게 증착하고 그 상면에 금을 증착하여 리프트오프 공정에 의해 금속패드(16)를 형성하며, 접촉창 마스크로 접촉창을 형성한 후 공중배선(17)공정을 통하여 단위능동소자(10)의 에미터 전극(12)을 금속패드(16)에 연결하며, 상기 기판(11)의 뒷면을 연마하고 절연영역(15)에 반응성이온식각 공정으로 비아홀(18)을 형성하며, 기판 뒷면을 금으로 도금하여 금속패드(16)와 접지금속(19)을 연결하는 공정으로 실현되는 기어형 이종접합 바이폴라 트랜지스터 제조방법을 포함한다.Next, a thin film of chromium is deposited on the upper surface of the insulating region 15, and gold is deposited on the upper surface of the insulating region 15 to form a metal pad 16 by a lift-off process. A contact window is formed by a contact window mask, The emitter electrode 12 of the unit active element 10 is connected to the metal pad 16 through the process of polishing the back surface of the substrate 11 and the via hole is formed in the insulating region 15 by a reactive ion etching process 18 and a step of connecting the metal pad 16 and the grounding metal 19 by plating the rear surface of the substrate with gold to thereby form a heterojunction bipolar transistor of the gear type.
실시예는 GaX-1AlXAs-GaAs의 이종접합을 사용한 바이폴라 트랜지스터의 예이지만, 이하에 구체적으로 표시한 이종접합의 경우에 한정되는 것은 아니며, 예를 들면 InGaAs-AlInAs, InGaAs-InGaAsP, Si-SiGe 등에 적용 가능한 것은 물론이다.The embodiment is an example of a bipolar transistor using heterojunctions of Ga x-1 Al x As-GaAs. However, the present invention is not limited to the case of hetero-junctions specifically described below. For example, InGaAs-AlInAs, InGaAs-InGaAsP, Si-SiGe, and the like.
단위능동소자(10)의 제조에 있어서는 먼저 GaAs기판(11) 상면에 콜렉터응(20)의 n+GaAs층, n-GaAs이 에피택셜 결정성장에 의해 형성되며, 더불어서 베이스층(21)의 P+GaAS층, 에미터층(22)의 nGaX-1AlXAs층을 순차적으로 에피택셜 성장시킨다.The n + GaAs layer and the n - GaAs layer of the collector electrode 20 are formed on the upper surface of the GaAs substrate 11 by the epitaxial crystal growth and the P + GaAs layer and the nGa x-1 Al x As layer of the emitter layer 22 are successively epitaxially grown.
이어서 상기 에미터층(22)의 상면에 감광제 및 소정의 에미터 전극 마스크(#1)를 이용하여 창을 형성한 후 n 형 금속을 리프트오프시켜 에미터 전극(12)을 형성한다(제3도의 A 참조).Next, a window is formed on the upper surface of the emitter layer 22 using a photosensitive agent and a predetermined emitter electrode mask (# 1), and then the n-type metal is lifted off to form the emitter electrode 12 A).
다음에 상기 에미터 전극(12) 하부를 제외한 에미터층(22)을 에칭공정으로 제거하는데 에미터 전극(12) 하부의 에미터층(22)의 폭이 에미터 전극(12)의 폭보다 적게 형성되도록 선택적으로 반응성이온식각을 이용한 선택적 식각공정과 리세스 식각(Recess etching)을 행한다.The width of the emitter layer 22 under the emitter electrode 12 is less than the width of the emitter electrode 12 so that the width of the emitter electrode 22 is less than the width of the emitter electrode 12. [ The selective etching process and the reactive etching process are selectively performed using reactive ion etching.
이는 다음단계에서 증착되는 베이스 전극(13)이 에미터 전극(12)을 마스크로 이용하여 에미터 전극(12)의 둘레에 형성될 때 에미터층(22)과 분리되도록 하기 위함이다.This is to ensure that the base electrode 13 deposited in the next step is separated from the emitter layer 22 when it is formed around the emitter electrode 12 using the emitter electrode 12 as a mask.
상기 에미터층(22)과 베이스 전극(13) 사이의 간격은 0.2㎛ 범위를 유지하는 것이 바람직하다(제3도의 B 참조).It is preferable that the interval between the emitter layer 22 and the base electrode 13 is kept within a range of 0.2 mu m (see B in FIG. 3).
이어서 상기 베이스층(21) 상면에 감광제 및 소정의 베이스 전극(13) 마스크(#2)를 이용하여 에미터 전극(12) 둘레에 창을 형성한 후 p형 금속을 리프트오프하여 베이스 전극(13)을 형성한다. 이때 에미터 전극(12)이 베이스 금 속의 자기정열(Self-Align) 마스크로 작용하게된다(제3도의 C 참조).A window is formed around the emitter electrode 12 using a photoresist and a predetermined base electrode 13 mask (# 2) on the upper surface of the base layer 21 and then the p-type metal is lifted off to form a base electrode 13 ). At this time, the emitter electrode 12 acts as a self-alignment mask of the base metal (see C in FIG. 3).
이어서 콜렉터 식각 마스크(#3)을 이용하여 에미터 전극(12) 및 베이스 전극(13)의 하부를 제외한 베이스층(21)과 상부 n-콜렉터층(20)을 식각공정으로 제거하여 하부 n+콜렉터층(20)을 노출하고(제3도의 D 참조), 베이스 전극(13)의 양단에 감광제 및 콜렉터 전극(14) 마스크(#4)를 이용하여 창을 형성한 후 n 형 금속을 리프트 오프하여 콜렉터 전극(14)을 형성한다(제3도의 E 참조).Was then used in the emitter electrode 12 and the base layer, except for the lower portion of the base electrode 13, 21 and the upper n the collector etch mask (# 3) by removing the collector layer 20 in the etching process the lower n + The collector layer 20 is exposed (see D in FIG. 3), a window is formed by using a photoresist and a collector electrode 14 mask (# 4) at both ends of the base electrode 13, Thereby forming a collector electrode 14 (see E in FIG. 3).
이어서 저항성 접촉을 향상시킬 수 있도록 420℃ 온도에서 약 20초간 얼로이공정을 행한 후 절연 임프랜트 마스크(#5)를 이용하여 절연영역(15)을 형성함으로써 단위능동소자(10)의 제조를 완료한다(제3도의 F 참조).Subsequently, the insulating layer 15 is formed by using an insulating intrinsic mask (# 5) after the alloying process is performed at a temperature of 420 ° C. for about 20 seconds so as to improve resistive contact, thereby completing the fabrication of the unit active element 10 (See F in Fig. 3).
이어서 제2도와 같이 기어형상으로 배열된 다수개의 단위능동소자(10)에 금속패드 마스크(#6a)를 이용하여 베이스 전극(13)이 단위능동소자(10)의 단면과 직각방향으로 링모양의 베이스 금속패드(16a)에 연결되고 콜렉터 전극(14)은 콜렉터 금속패드 마스크(#6c)를 이용하여 기어형상으로 배열된 단위능동소자(10)의 외곽에 일측이 개방된 원형밴드 형상의 콜렉터 금속패드(16c)에 연결된다.Subsequently, a plurality of unit active elements 10 arranged in a gear shape as shown in FIG. 2 are formed by using a metal pad mask (# 6a) so that the base electrode 13 is formed in a ring shape The collector electrode 14 is connected to the base metal pad 16a and the collector electrode 14 is connected to a collector metal electrode pad 16a having a circular band shape with one side opened to the outside of the unit active element 10 arranged in a gear shape using a collector metal pad mask # And is connected to the pad 16c.
이때 에미터 금속(12)이 공중배선(17) 공정으로 연결될 기어형상으로 배열된 단위능동소자(10)의 중심부에 에미터 금속패드 마스크(#6b)를 이용하여 에미터 금속패드(16b)가 동시에 리프트오프되어 형성된다(제3도의 G 참조).At this time, the emitter metal pad 16b is formed by using the emitter metal pad mask (# 6b) in the central part of the unit active element 10 in which the emitter metal 12 is arranged in a gear shape to be connected by the air wiring 17 process And simultaneously lift-off (see G in FIG. 3).
이어서 접촉창 마스크(#7)를 이용하여 에미터 전극(12) 상면과 금속패드(16) 상면에 접촉창을 형성하고 200Å 두께의 금을 스퍼터링하여 기판(11)의 전면에 증착시킨 후 공중배선 마스크(#8)를 이용하여 상기 스퍼터링 증착된 금의 상면에 금을 도금한 후 아세톤으로 감광성 수지를 제거하여 도금된 금이 없는 부분의 스퍼터링된 금은 감광성 수지와 함께 없어지게 되어 공중배선(17)이 이루어지게 되며 이와같이 단위능동소자(10)의 에미터 전극(12)을 에미터 금속패드(16b)에 연결하여 GSBT의 전면공정을 완료한다(제3도의 H 참조).Next, a contact window is formed on the upper surface of the emitter electrode 12 and the upper surface of the metal pad 16 using a contact window mask (# 7), and a 200 Å thick gold is sputtered on the entire surface of the substrate 11, The upper surface of the sputter deposited gold is plated with gold (# 8), and then the photosensitive resin is removed with acetone to remove the plated gold-free portion of the gold-free portion with the silver wiring. The emitter electrode 12 of the unit active element 10 is connected to the emitter metal pad 16b to complete the front face process of the GSBT (see H in FIG. 3).
이어서 기판(11) 뒷면을 연마하고 비아홀 식각 마스크(#9)를 이용하여 에미터 금속패드(16b) 저면에 창을 형성한 후 반응성 이온식각공정으로 식각하여 비아홀(18)을 형성한다.Next, a back surface of the substrate 11 is polished, a window is formed on the bottom surface of the emitter metal pad 16b by using a via hole etching mask (# 9), and a via hole 18 is formed by a reactive ion etching process.
이어서 기판(11) 뒷면 도금공정으로 접지금속(19)이 형성되면서 비아홀(18)을 통하여 접지금속(19)와 에미터 금속패드(16b)가 전기적으로 연결된다.The ground metal 19 is formed in the back surface plating process of the substrate 11 and the ground metal 19 and the emitter metal pad 16b are electrically connected through the via hole 18. [
특히, 기판(11) GaAs와의 선택도를 높이기 위하여 접지금속(19)를 증착하기 전에 크롬을 200Å 정도의 두께로 얇게 증착하는 것이 바람직하다.Particularly, in order to increase the selectivity of the substrate 11 with GaAs, it is preferable to deposit chrome thinly to a thickness of about 200 Å before depositing the ground metal 19.
이와같이 본 발명은 단위능동소자를 방사형상으로 배치하여 소자에서 발생되는 열을 골고루 분포시켜 모든 단위능동소자가 비슷한 온도 분포를 갖도록 함으로써 고출력 HBT에서 발생하는 열파괴현상을 효과적으로 방지할 수 있다.As described above, the unit active elements are radially arranged to uniformly distribute the heat generated by the devices, and all the unit active devices have a similar temperature distribution, thereby effectively preventing the thermal breakdown phenomenon occurring in the high output HBTs.
또한, 이와같은 GSBT는 단위능동소자와 접지사이를 공중배선 공정 및 비아홀을 통해 열원을 접지에 퇴단거리로 연결함으로써 접지 인덕턴스를 최소화하고 단위능동소자에서 발생되는 열을 효율적으로 방사시켜 고출력 HBT의 열적 특성을 개선하여 고출력 기어형 HBT의 신뢰도를 확보할 수 있다. 아울러 같은 출력의 HBT를 제작하는데 있어서 GSHBT는 종전의 HBT에 비해 면적을 크게 줄일 수 있는 효과를 얻을 수 있다.This GSBT minimizes the ground inductance and efficiently radiates the heat generated by the unit active device by connecting the heat source to the ground through the air wiring process and the via hole between the unit active device and the ground, The reliability of the high output gear type HBT can be ensured. In addition, GSHBT can reduce the area of the HBT compared to the conventional HBT.
Claims (12)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20030075993A (en) * | 2002-03-22 | 2003-09-26 | 삼성전자주식회사 | Heterojunction bipolar transistor having horse shoe type emitter node and method of manufacturing the same |
| KR100808166B1 (en) * | 2002-02-06 | 2008-02-29 | 주식회사 엘지이아이 | Base Feeding Line of Heterojunction Bipolar Transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100808166B1 (en) * | 2002-02-06 | 2008-02-29 | 주식회사 엘지이아이 | Base Feeding Line of Heterojunction Bipolar Transistor |
| KR20030075993A (en) * | 2002-03-22 | 2003-09-26 | 삼성전자주식회사 | Heterojunction bipolar transistor having horse shoe type emitter node and method of manufacturing the same |
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