KR980007367A - Duplication circuit of time slot switch and device matching device in all electronic exchanges - Google Patents

Duplication circuit of time slot switch and device matching device in all electronic exchanges Download PDF

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Publication number
KR980007367A
KR980007367A KR1019960024064A KR19960024064A KR980007367A KR 980007367 A KR980007367 A KR 980007367A KR 1019960024064 A KR1019960024064 A KR 1019960024064A KR 19960024064 A KR19960024064 A KR 19960024064A KR 980007367 A KR980007367 A KR 980007367A
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South Korea
Prior art keywords
time slot
slot switch
buffer
data
act
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KR1019960024064A
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Korean (ko)
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KR100202991B1 (en
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김주용
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유기범
대우통신 주식회사
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54575—Software application
    • H04Q3/54591—Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/22—Arrangements for supervision, monitoring or testing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/08—Time only switching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/54566—Intelligent peripherals, adjunct processors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13393—Time slot switching, T-stage, time slot interchanging, TSI

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

본 발명은 타임 슬롯 스위치(TS A, TS B) 와 디바이스간의 데이터를 정합시키는 정합 회로(IA, IB)를 타임 슬롯 스위치(TS A, TS B)와 이중화 구성시에 데이터를 상호 통신 시키는 전전자 교환기의 이중화 회로에 관한 것으로서, 상기 (TS A)로부터 인가되는 데이터를 수신하고, 액티브 신호(ACT-A)를 출력하는 제1수신부(11)와; 타임 슬롯 스위치(TS B)로부터 인가되는 데이터를 수신하고, 액티브 신호(ACT-B)를 출력하는 제2수신부(12)와; 구동 신호에 따라 상기 수신부(11)로부터 인가되는 타임 슬롯 스위치(TS A)의 데이터를 상기 정합장치(IA)에 선택적으로 인가하는 제1버퍼(B11)와; 구동 신호에 따라 상기 수신부(12)로부터 인가되는 타임 슬롯 스위치(TS B)의 데이터를 상기 정합 장치(IA)에 데이터를 인가하는 제2버퍼(B12)와; 액티브 신호(ACT-A, ACT-B)의 인가를 따라 구동 신호를 상기 제1또는 제2버퍼(B11, B122)에 선택적으로 출력하는 구동 신호 발생부(13)와; 정합 장치(IA)로부터 데이터를 수신하는 버퍼(B13)와, 버퍼(13)로부터의 데이터를 상기 정합 장치(IA)로부터의 액티브 신호(ACT-IA)에 따라 상기 타임 슬롯 스위치(TS A)에 선택적으로 인가되는 송신부(14)를 구비하는 제1통신부(10)와; 타임 슬롯 스위치(TS A)로부터 인가되는 데이터를 수신하고, 액티브 신호(ACT-A)를 출력하는 제3수신부(21)와; 타임 슬롯 스위치(TS B)로부터 인가되는 데이터를 수신하고, 액티브 신호(ACT-B)를 출력하는 제4수신부(22)와; 구동 신호에 따라 상기 수신부(21)로부터 인가되는 타임 슬롯 스위치(TS A)의 데이터를 상기 정합 장치(IB)에 선택적으로 인가하는 제3버퍼(B21)와; 구동 신호에 따라 상기 수신부(22)로부터 인가되는 타임 슬롯 스위치(TS B)의 데이터를 상기 정합 장치(IB)에 선택적으로 인가하는 제4버퍼(B22)와; 액티브 신호(ACT-A, ACT-B)의 인가에 따라 구동 신호를 상기 제3또는 제4버퍼(B21, B22)로부터 선택적으로 출력하는 구동 신호 발생부(23)와; 정합 장치(IB)로부터 데이터를 수신하는 버퍼(B23)와; 버퍼(B23)로부터의 데이터를 상기 정합 장치(IB)로부터의 액티브 신호(ACT-IB)에 따라 상기 타임 슬롯 스위치(TS B)에 선택적으로 인가하는 송신부(24)를 구비하는 제2통신부(20)로 구성된다. 즉 본 발명은 타임 슬롯 스위치와 정합 장치가 이중화로 구성할 때에 액티브 상태의 타임 슬롯 스위치 데이터를 정합 장치들에 인가하며, 액티브 상태의 정합 장치로부터 인가되는 디바이스들의 데이터를 타임 슬롯 스위치들에 인가할 수 있다는 효과가 있다.The present invention relates to a time slot switch (TS A, TS B) and a time slot switch (TS A, TS B) and a matching circuit (IA, IB) A first receiving unit 11 for receiving data from the base station TS A and outputting an active signal ACT-A; A second receiving section 12 for receiving data applied from a time slot switch TS B and outputting an active signal ACT-B; A first buffer B11 for selectively applying the data of the time slot switch TS A applied from the receiving unit 11 to the matching unit IA according to a driving signal; A second buffer B12 for applying data of the time slot switch TS B applied from the receiver 12 to the matching device IA according to a driving signal; A drive signal generator 13 for selectively outputting a drive signal to the first or second buffer B11 or B122 according to the application of the active signals ACT-A and ACT-B; A buffer B13 for receiving data from the matching device IA and a buffer 13 for receiving data from the buffer 13 in accordance with the active signal ACT-IA from the matching device IA A first communication unit (10) having a transmitting unit (14) selectively applied thereto; A third receiving section 21 for receiving data applied from the time slot switch TS A and outputting an active signal ACT-A; A fourth receiving section 22 for receiving data applied from the time slot switch TS B and outputting an active signal ACT-B; A third buffer B21 for selectively applying the data of the time slot switch TS A applied from the receiving unit 21 to the matching apparatus IB according to a driving signal; A fourth buffer B22 for selectively applying the data of the time slot switch TS B applied from the receiving unit 22 to the matching apparatus IB according to a driving signal; A drive signal generator 23 for selectively outputting a drive signal from the third or fourth buffer B21 or B22 according to the application of the active signals ACT-A and ACT-B; A buffer B23 for receiving data from the registration device IB; And a transmitting section (24) for selectively applying the data from the buffer (B23) to the time slot switch (TS B) in accordance with an active signal (ACT-IB) ). That is, the present invention applies active time slot switch data to the matching devices when the time slot switch and the matching device are configured to be redundant, and applies the data of the devices applied from the active state matching device to the time slot switches Can be effective.

Description

전전자 교환기의 타임 슬롯 스위치와 디바이스간 정합 장치의 이중화 회로Duplication circuit of time slot switch and device matching device in all electronic exchanges

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도는 본 발명에 따른 전전자 교환기의 타임 슬롯 스위치와 디바이스간 정합 장치의 이중화 회로도.FIG. 1 is a redundant circuit diagram of a time slot switch and a device-to-device matching device of a full electronic switching system according to the present invention. FIG.

제2도는 본 발명에 따른 전전자 교환기의 타임 슬롯 스위치와 디바이스간 정합 장치의 이중화 회로의 상태 변환을 도시한 도면.FIG. 2 is a diagram showing a state transition of a redundant circuit of a time slot switch and a device-to-device matching apparatus of an electric electronic switching system according to the present invention. FIG.

Claims (2)

타임 슬롯 스위치(TS A, TS B) 와 디바이스간의 데이터를 정합시키는 정합 회로(IA, IB)를 타임 슬롯 스위치(TS A, TS B)와 이중화 구성시에 데이터를 상호 통신시키는 전전자 교환기의 이중화 회로로서, 상기 하임 슬롯 스위치 (TS A)로부터 인가되는 데이터를 수신하고, 액티브 신호(ACT-A)를 출력하는 제1수신부(11)와; 상기 타임 슬롯 스위치(TS B)로부터 인가되는 데이터를 수신하고, 액티브 신호(ACT-B)를 출력하는 제2수신부(12)와; 구동 신호에 따라 상기 수신부(11)로부터 인가되는 타임 슬롯 스위치(TS A)의 데이터를 상기 정합장치(IA)에 선택적으로 인가하는 제1버퍼(B11)와; 구동 신호에 따라 상기 수신부(12)로부터 인가되는 타임 슬롯 스위치(TS B)의 데이터를 상기 정합 장치(IA)에 선택적으로 인가하는 제2버퍼(B12)와 상기 액티브 신호(ACT-A, ACT-B)의 인가에 따라 구동 신호를 상기 제1또는 제2버퍼(B11, B122)에 선택적으로 출력하는 구동 신호 발생부(13)와; 상기 정합 장치(IA)로부터 데이터를 수신하는 버퍼(B13)와; 상기 버퍼(13)로부터의 데이터를 상기 정합 장치(IA)로부터의 액티브 신호(ACT-IA)에 따라 상기 타임 슬롯 스위치(TS A)에 선택적으로 인가되는 송신부(14)를 구비하는 제1통신부(10)와; 상기 타임 슬롯 스위치(TS A)로부터 인가되는 데이터를 수신하고, 액티브 신호(ACT-A)를 출력하는 제3수신부(21)와; 상기 타임 슬롯 스위치(TS B)로부터 인가되는 데이터를 수신하고, 액티브 신호(ACT-B)를 출력하는 제4수신부(22)와; 구동 신호에 따라 상기 수신부(21)로부터 인가되는 타임 슬롯 스위치(TS A)의 데이터를 상기 정합 장치(IB)에 선택적으로 인가하는 제3버퍼(B21)와; 구동 신호에 따라 상기 수신부(22)로부터 인가되는 타임 슬롯 스위치(TS B)의 데이터를 상기 정합 장치(IB)에 선택적으로 인가하는 제4버퍼(B22)와; 상기 액티브 신호(ACT-A, ACT-B)의 인가에 따라 구동 신호를 상기 제3또는 제4버퍼(B21, B22)로부터 선택적으로 출력하는 구동 신호 발생부(23)와; 상기 정합 장치(IB)로부터 데이터를 수신하는 버퍼(B23)와; 상기 버퍼(B23)로부터의 데이터를 상기 정합 장치(IB)로부터의 액티브 신호(ACT-IB)에 따라 상기 타임 슬롯 스위치(TS B)에 선택적으로 인가하는 송신부(24)를 구비하는 제2통신부(20)로 구성한 전전자 교환기의 타임 슬롯 스위치와 디바이스간 정합 장치의 이중화 회로.The multiplexing circuits IA and IB for matching the data between the time slot switches TS A and TS B and the devices with the time slot switches TS A and TS B and the redundancy Circuit, comprising: a first receiving section (11) for receiving data applied from the heightslot switch (TS A) and outputting an active signal (ACT-A); A second receiving unit 12 for receiving data applied from the time slot switch TS B and outputting an active signal ACT-B; A first buffer B11 for selectively applying the data of the time slot switch TS A applied from the receiving unit 11 to the matching unit IA according to a driving signal; A second buffer B12 for selectively applying the data of the time slot switch TS B applied from the receiver 12 to the matching device IA according to a driving signal and a second buffer B12 for applying the active signals ACT- A driving signal generator 13 for selectively outputting a driving signal to the first or second buffer B11 or B122 according to the application of the driving signal B; A buffer (B13) for receiving data from said matching device (IA); And a transmitting section (14) selectively applied to said time slot switch (TS A) in accordance with an active signal (ACT-IA) from said matching device (IA) 10); A third receiving unit 21 for receiving data applied from the time slot switch TS A and outputting an active signal ACT-A; A fourth receiving unit 22 for receiving data applied from the time slot switch TS B and outputting an active signal ACT-B; A third buffer B21 for selectively applying the data of the time slot switch TS A applied from the receiving unit 21 to the matching apparatus IB according to a driving signal; A fourth buffer B22 for selectively applying the data of the time slot switch TS B applied from the receiving unit 22 to the matching apparatus IB according to a driving signal; A driving signal generator 23 for selectively outputting a driving signal from the third or fourth buffer B21 or B22 according to the application of the active signals ACT-A and ACT-B; A buffer B23 for receiving data from the matching device IB; And a transmitting section (24) for selectively applying the data from said buffer (B23) to said time slot switch (TS B) in accordance with an active signal (ACT-IB) 20), a time-slot switch of the electronic exchanger and a device-to-device matching circuit. 제1항에 있어서, 상기 구동 신호 발생부(13, 23)는, 타임 슬롯 스위치(TS-B)가 스탠바이 상태인 경우에 타임 슬롯 스위치(TS A)의 데이터를 버퍼(B11, B21)가 출력할 수 있도록 구동 신호를 버퍼(B11, B21)에만 인가하며; 타임 슬롯 스위치(TS B)가 액티브 상태, 타임 슬롯 스위치(TS-A)가 스탠 바이 상태인 경우에 타임 슬롯 스위치(TS B)의 데이터를 버퍼(B12, B22)가 출력할 수 있도록 구동 신호를 버퍼(B12, B22)에만 인가하고; 액티브 상태의 타임 슬롯 스위치(TS A, TS B)가 설정되면, 스탠 바이 상태였던 타임 슬롯 스위치(TS A 또는 TS B)가 액티브 상태로 변경되어도 선택되었던 타임 슬롯 스위치(TS A, TS B)를 변경하지 않으며, 타임 슬롯 스위치(TS A, TS B) 모두가 스탠 바이 상태가 되어도 선택되었던 타임 슬롯 스위치(TS A, TS B)를 변경하지 않게 구성한 전전자 교환기의 타임 슬롯 스위치와 디바이스간 정합 장치의 이중화 회로.The drive signal generator according to claim 1, wherein the drive signal generator (13, 23) outputs the data of the time slot switch TS A to the buffers B11, B21 when the time slot switch TS- The driving signals are applied to the buffers B11 and B21 only; The drive signal is supplied to the buffers B12 and B22 so that the data of the time slot switch TS B can be output by the buffers B12 and B22 when the timeslot switch TS B is in the active state and the time slot switch TS- Applies only to the buffers B12 and B22; When the active time slot switch TS A, TS B is set, even if the time slot switch TS A or TS B in the standby state is changed to the active state, the selected time slot switch TS A, And the time slot switch of the electronic exchanger configured to not change the selected time slot switch (TS A, TS B) even if all the time slot switches (TS A, TS B) are in the standby state, Of the redundant circuit.
KR1019960024064A 1996-06-26 1996-06-26 Duplication circuit for matching apparatus between device and time slot of switching system KR100202991B1 (en)

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KR1019960024064A KR100202991B1 (en) 1996-06-26 1996-06-26 Duplication circuit for matching apparatus between device and time slot of switching system

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KR1019960024064A KR100202991B1 (en) 1996-06-26 1996-06-26 Duplication circuit for matching apparatus between device and time slot of switching system

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KR980007367A true KR980007367A (en) 1998-03-30
KR100202991B1 KR100202991B1 (en) 1999-06-15

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