KR980007196A - Asynchronous Transmission Mode Host Connection Device Sending and Receiving Data by Channel Numbering - Google Patents
Asynchronous Transmission Mode Host Connection Device Sending and Receiving Data by Channel Numbering Download PDFInfo
- Publication number
- KR980007196A KR980007196A KR1019960022445A KR19960022445A KR980007196A KR 980007196 A KR980007196 A KR 980007196A KR 1019960022445 A KR1019960022445 A KR 1019960022445A KR 19960022445 A KR19960022445 A KR 19960022445A KR 980007196 A KR980007196 A KR 980007196A
- Authority
- KR
- South Korea
- Prior art keywords
- descriptor
- transmission
- data
- host
- information
- Prior art date
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9057—Arrangements for supporting packet reassembly or resequencing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
Abstract
본 발명은 호스트의 외부장치 접속용 호스트 버스에 장착되어 비동기 전달모드(ATM: Asynchoronus Transfer Mode) 프로토콜을 사용하는 망에 연결시키는 고성능 ATM 호스트 접속장치에 있어서, 호스트의 상위 프로토콜에서 ATM 프로토콜에 관계없이 데이타를 전달하기 위해 채널 번호를 부여하여 사용자 데이타를 고속으로 전달하기 위한 송/수신 방법에 관한 것이다. 본 발명은 ATM 호스트 접속장치와 상기 프로토콜 사이에서 ATM 정보의 하드웨어 연결 설정 정보와 채널번호를 1:1로 연관시켜 채널정보를 구성하는 제1단계, 고속의 데이타 송신을 위해 고정 분할된 송수신 패킷메모리와 디스크립터를 1:1로 연관시키는 제2단계, 데이터 송신 요구가 발생하면, 디스크립터를 할당하고 CPCS-PDU를 생성하고, 디스크립터 엔트리에 해당정보를 채우고 송신 디스크립터 큐에 디스크립터를 삽입하므로 송신하는 제3단계, 및 데이터 정보 및 CPCS-PDU를 추출하고 호스트 송신 대기 디스크립터 링크드 리스트에 삽입하므로 수신하는 제4단계로 이루어진다.The present invention is a high performance ATM host access device which is attached to a host bus for connecting an external device of a host to a network using an Asynchoronus Transfer Mode (ATM) protocol, regardless of the ATM protocol in the host's upper protocol. The present invention relates to a transmission / reception method for delivering user data at high speed by assigning a channel number for delivering data. The present invention provides a first step of configuring channel information by associating hardware connection configuration information of an ATM information with a channel number between an ATM host access device and the protocol in a 1: 1 manner, and the fixed divided transmission / reception packet memory for high speed data transmission. And the second step of associating the descriptor with a 1: 1, when a data transmission request occurs, assigns a descriptor, generates a CPCS-PDU, fills corresponding information in the descriptor entry, and inserts the descriptor in the transmission descriptor queue, thereby transmitting And a fourth step of receiving data information and CPCS-PDUs and inserting them into the host send queue descriptor linked list to receive them.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제4도는 본 발명에 따른 데이타 수신 처리 구성도.4 is a block diagram of a data receiving process according to the present invention.
제5도는 본 발명에 따른 송신 과정 흐름도.5 is a flowchart of a transmission process according to the present invention.
제6도는 본 발명에 따른 수신 과정 흐름도.6 is a flowchart of a receiving process according to the present invention.
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960022445A KR100204050B1 (en) | 1996-06-19 | 1996-06-19 | Data transmission method by allocating the channel number allocating in atm host connection device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960022445A KR100204050B1 (en) | 1996-06-19 | 1996-06-19 | Data transmission method by allocating the channel number allocating in atm host connection device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR980007196A true KR980007196A (en) | 1998-03-30 |
KR100204050B1 KR100204050B1 (en) | 1999-06-15 |
Family
ID=19462563
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960022445A KR100204050B1 (en) | 1996-06-19 | 1996-06-19 | Data transmission method by allocating the channel number allocating in atm host connection device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100204050B1 (en) |
-
1996
- 1996-06-19 KR KR1019960022445A patent/KR100204050B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100204050B1 (en) | 1999-06-15 |
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